Solid nanopore array and preparation method and application of solid nanopore array device

Abstract

The invention provides a preparation method and application of a solid-state nanopore array and a solid-state nanopore array device. The preparation method comprises the following steps: forming first-direction nanostrips and second-direction nanostrips in a first thin film layer, a second thin film layer, a third thin film layer and a fourth thin film layer respectively by combining a coating process and an etching process; and then selective etching is carried out on the intersection point of the first nano-strip and the second nano-strip, so that the required solid-state nano-pore array is formed in the functional material layer, and compared with the existing method for preparing the solid-state nano-pore array, the preparation method has the advantages of rapidness, high efficiency, large-area preparation, low cost and the like; the aperture and the array scale of the formed solid-state nanopores can be accurately controlled by adjusting process parameters; in addition, the preparation method is suitable for various solid materials and can be completely compatible with the existing CMOS process technology, and large-scale manufacturing of solid nanopore array devices can be achieved. In addition, the solid-state nanopore array device can be used for high-throughput analysis and detection of electrochemical signals and biomolecules such as DNA (Deoxyribose Nucleic Acid) or protein and the like.

Description

Technical Field

[0001] The present invention relates to the field of micro-nanostructure preparation, and in particular to a preparation method and application of a solid-state nanopore array and a solid-state nanopore array device. Background Art

[0002] Solid-state nanopore arrays have a wide range of applications in the fields of nanotechnology and nanoscience, especially in the fields of nanoelectronics, nanobiology, and nanosensors. For example, they can be used as components of single-molecule biosensors, and by controlling the pore size and chemical properties, high-sensitivity detection of biomolecules (such as DNA, proteins, etc.) can be achieved. In addition, solid-state nanopore arrays can also be used in nanofluid mechanics research, nanofiltration membranes, nanoelectronic devices, and other fields.

[0003] In 2001, researchers at Harvard University used a focused ion beam (FIB) to process the first solid-state nanopore on a SiNx film. In 2003, Storm used the electron beam of a transmission electron microscope (TEM) to prepare a nanopore with an aperture of about 20nm on a 30nm thick silicon oxide film. However, in the process of processing solid-state nanopores, both FIB and TEM face the problems of high prices and low processing efficiency. Electron beam lithography (EBL), as the main method for solid-state nanopore processing at present, can achieve a certain scale of small array nanopores, relying on the basic semiconductor process, which makes its repeatability very high, but it still has the problems of high cost and low efficiency.

[0004] In order to solve the cost problem, researchers are considering using electrochemical methods, such as dielectric breakdown (CBD) method or electrochemical etching method to prepare nanopore arrays. However, the dielectric breakdown (CBD) method cannot determine the location of the nanopore distribution, and the electrochemical etching method cannot achieve the processing requirements of nanopore arrays with controllable scale. Other methods such as chemical etching or metal-assisted chemical etching are also unable to achieve the preparation of nanopore arrays with controllable scale, size and shape. The laser etching process equipment is relatively complicated, and the geometry, size and distribution of the nanopores in the nanopore array prepared by the nanobubble-based electrodeposition method are uneven and difficult to control, while the method of nanopore processing using AFM has a low success rate and poor repeatability.

[0005] Therefore, how to develop a low-cost, mass-producible, size- and shape-controllable, and array-scale-controllable solid-state nanopore array and a process for solid-state nanopore array devices has become a challenge. Summary of the invention

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing a solid-state nanopore array and a solid-state nanopore array device and application thereof, so as to solve the problems faced in the prior art of the preparation process of the solid-state nanopore array, such as high cost, low efficiency, inability to achieve large-scale preparation, uneven geometry, size and distribution of the nanopores, and poor repeatability.

[0007] To achieve the above objectives and other related objectives, the present invention provides a method for preparing a solid-state nanopore array, comprising the following steps:

[0008] S1: providing a substrate, and forming a functional material layer on the front side of the substrate where nanopores need to be prepared;

[0009] S2: performing a deposition process on the functional material layer to form a first thin film layer;

[0010] S3: performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves;

[0011] S4: performing a deposition process on the first thin film layer to form a first sacrificial layer, wherein the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0012] S5: forming a second thin film layer on the first thin film layer, wherein the second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer, and the exposed first sacrificial layer serves as a first nano stripe;

[0013] S6: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves;

[0014] S7: performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer;

[0015] S8: forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so as to expose the second sacrificial layer as a second nano strip;

[0016] S9: performing an etching process at the intersection of the first nanostrip and the second nanostrip to form a first etching cavity;

[0017] S10: performing dry etching on the functional material layer based on the first etching chamber to form a solid nanopore array in the functional material layer.

[0018] Optionally, after forming the solid-state nanopore array in the functional material layer, the method further includes removing the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanostrip and the second nanostrip.

[0019] Optionally, the angle θ between the first direction and the second direction is in the range of 0<θ<180°.

[0020] Optionally, the deposition process is one of physical vapor deposition, chemical vapor deposition or atomic layer deposition.

[0021] Optionally, the first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide, and the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide.

[0022] Optionally, the material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound film, and the thickness d of the functional material layer is in the range of 0<d≤1μm.

[0023] Optionally, the first film layer and the second film layer are made of the same material, and the third film layer and the fourth film layer are made of the same material.

[0024] Optionally, the etching depth of the functional material layer subjected to dry etching is not less than the thickness of the functional material layer.

[0025] The present invention also provides a method for preparing a solid-state nanopore array device, the method for preparing a solid-state nanopore array device comprising the following steps:

[0026] S101: providing a substrate, forming a functional material layer on which nanopores need to be prepared on the front side of the substrate, and forming a mask layer on the back side of the substrate;

[0027] S102: performing a deposition process on the functional material layer to form a first thin film layer;

[0028] S103: performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves;

[0029] S104: performing a deposition process on the first thin film layer to form a first sacrificial layer, wherein the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0030] S105: forming a second thin film layer on the first thin film layer, wherein the second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer, and the exposed first sacrificial layer serves as a first nano stripe;

[0031] S106: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves;

[0032] S107: performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer;

[0033] S108: forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so that the exposed second sacrificial layer serves as a second nano stripe;

[0034] S109: performing a deposition process on the third thin film layer and the fourth thin film layer to form a first patterned layer, wherein the first patterned layer has a plurality of third grooves, and the third grooves reveal window areas;

[0035] S110: performing an etching process on the intersection of the first nanostrip and the second nanostrip in the window area to form a second etching cavity;

[0036] S111: dry-etching the functional material layer at the window region based on the second etching chamber to form a solid nanopore array;

[0037] S112: performing an alignment process on the back side of the substrate, and etching the substrate and the mask layer using an etching process to expose the solid-state nanopore array in the window area;

[0038] S113: removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nano-strip, the second nano-strip and the first patterned layer to form the solid-state nanopore array device.

[0039] Optionally, the angle θ between the first direction and the second direction is in the range of 0<θ<180°.

[0040] Optionally, the material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound film, and the thickness d of the functional material layer is in the range of 0<d≤1μm.

[0041] Optionally, the first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide, and the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide.

[0042] Optionally, the first film layer and the second film layer are made of the same material, and the third film layer and the fourth film layer are made of the same material.

[0043] Optionally, the etching depth of the functional material layer subjected to dry etching is not less than the thickness of the functional material layer.

[0044] The present invention also provides a solid-state nanopore array device, wherein the solid-state nanopore array device is obtained by any of the above-mentioned methods for preparing the solid-state nanopore array device.

[0045] The present invention also provides an application of a solid-state nanopore array device in electrochemical signal analysis, high-throughput analysis and detection of biological molecules such as DNA and protein.

[0046] As described above, the preparation method and application of the solid-state nanopore array and the solid-state nanopore array device of the present invention have the following beneficial effects: the preparation method of the solid-state nanopore array combines the deposition process coating and the dry etching process to form a first nano strip along the first direction in the first film layer and the second film layer, and forms a second nano strip along the second direction in the third film layer and the fourth film layer, and then selectively etches at the intersection of the first nano strip and the second nano strip, so as to form the required solid-state nanopore array pattern in the functional material layer. Compared with the existing FIB, EBL, TEM and CBD methods, the preparation method has the advantages of fast and efficient, large-area preparation, low cost, etc., and the aperture and array scale of the formed nanopores can be accurately controlled by adjusting the process parameters, and has high repeatability; the preparation method of the solid-state nanopore array device proposed based on the solid-state nanopore array can be applied to a variety of solid materials and is fully compatible with the existing CMOS process technology, realizing large-scale integrated manufacturing of solid-state nanopore array devices, thereby significantly reducing the preparation cost. In addition, the solid-state nanopore array device of the present invention can also realize high-throughput analysis and detection of electrochemical signals and biological molecules such as DNA or protein. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Shown is a schematic flow chart of a method for preparing a solid-state nanopore array in an embodiment of the present invention.

[0048] Figure 2 It is a schematic diagram of the structure after forming the substrate and the functional material layer in the solid-state nanopore array in an embodiment of the present invention.

[0049] Figure 3 It is a schematic diagram of the structure after forming the first thin film layer in the solid-state nanopore array in an embodiment of the present invention.

[0050] Figure 4 It is a schematic diagram of the structure after the first groove is formed in the solid-state nanohole array in an embodiment of the present invention.

[0051] Figure 5 It is a schematic diagram of the structure after forming the first sacrificial layer in the solid-state nanohole array in an embodiment of the present invention.

[0052] Figure 6 It is a schematic diagram of the structure after forming the second film layer in the solid-state nanopore array in an embodiment of the present invention.

[0053] Figure 7 It is a schematic diagram of the structure after the third thin film layer is formed in the solid-state nanopore array in an embodiment of the present invention.

[0054] Figure 8 It is a schematic diagram of the structure after forming the second groove and the second sacrificial layer in the solid-state nanohole array in an embodiment of the present invention.

[0055] Fig. 9 It is a schematic diagram of the structure after forming the fourth thin film layer in the solid-state nanopore array in an embodiment of the present invention.

[0056] Fig.10 It is a schematic diagram of the structure after the first etching cavity is formed in the solid-state nanopore array in an embodiment of the present invention.

[0057] Fig.11 Shown is a schematic structural diagram of a solid-state nanopore array in an embodiment of the present invention.

[0058] Fig.12 Shown is a schematic flow chart of a method for preparing a solid-state nanopore array device in an embodiment of the present invention.

[0059] Fig.13 It is a schematic diagram of the structure after forming a mask layer in the solid-state nanohole array device in an embodiment of the present invention.

[0060] Fig.14It is a schematic diagram of the structure after forming the first patterned layer in the solid-state nanohole array device in an embodiment of the present invention.

[0061] Fig.15 It is a schematic diagram of the structure after the second etching cavity is formed in the solid-state nanopore array device in the embodiment of the present invention.

[0062] Fig.16 Shown is a schematic diagram of the structure after nanopores are formed in the solid-state nanopore array device in an embodiment of the present invention.

[0063] Fig.17 It is a schematic diagram showing the structure after the etching grooves are formed in the solid-state nanopore array device in the embodiment of the present invention.

[0064] Fig.18 Shown is a schematic structural diagram of a solid-state nanopore array device in an embodiment of the present invention.

[0065] Fig.19 Shown is a schematic structural diagram of a single-hole / double-hole solid-state nanopore array device in an embodiment of the present invention when conducting conductivity testing and biomolecule detection analysis.

[0066] Fig. 20 Schematic diagram showing the conductivity results of a single-hole / double-hole solid-state nanopore array device in an embodiment of the present invention.

[0067] Fig.21 Shown is a schematic diagram of the relationship between current and time of a single-hole / double-hole solid-state nanopore array device in an embodiment of the present invention.

[0068] Fig. 22 Shown is a schematic diagram of signal statistics of a single-hole / double-hole solid-state nanopore array device in an embodiment of the present invention.

[0069] Description of Reference Numerals

[0070] 10. Substrate; 11. Functional material layer; 12. First thin film layer; 13. First groove; 14. First sacrificial layer; 15. Second thin film layer; 16. Third thin film layer; 17. Second groove; 18. Second sacrificial layer; 19. Fourth thin film layer; 20. First etching cavity; 21. Nanohole array; 22. Mask layer; 23. First patterned layer; 24. Window area; 25. Second etching cavity; 26. Etching groove; S1~S10, steps; S101~S113, steps. DETAILED DESCRIPTION

[0071] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0072] For ease of description, spatially relative terms such as "under," "below," "below," "below," "above," "on," etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0073] It should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the above components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0074] Example 1

[0075] The present invention provides a method for preparing a solid-state nanopore array. Figure 1 As shown, it is a process flow chart of the preparation method of the solid-state nanopore array, which includes the following steps:

[0076] S1: providing a substrate, and forming a functional material layer on the front side of the substrate where nanopores need to be prepared;

[0077] S2: performing a deposition process on the functional material layer to form a first thin film layer;

[0078] S3: performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves;

[0079] S4: performing a deposition process on the first thin film layer to form a first sacrificial layer, wherein the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0080] S5: forming a second thin film layer on the first thin film layer, wherein the second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer, and the exposed first sacrificial layer serves as a first nano stripe;

[0081] S6: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves;

[0082] S7: performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer;

[0083] S8: forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so as to expose the second sacrificial layer as a second nano strip;

[0084] S9: performing an etching process at the intersection of the first nanostrip and the second nanostrip to form a first etching cavity;

[0085] S10: performing dry etching on the functional material layer based on the first etching chamber to form a solid nanopore array in the functional material layer.

[0086] The following is a further introduction to the preparation method of the solid-state nanopore array in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the solid-state nanopore array protected by the present invention, and those skilled in the art may change it according to the actual preparation steps, as follows:

[0087] In step S1, see Figure 1 and Figure 2 , providing a substrate, and forming a functional material layer on the front side of the substrate where nanopores need to be prepared.

[0088] Specifically, Figure 2As shown, in an embodiment of the present invention, a substrate is provided, the substrate having a front side and a back side arranged relatively, the material of the substrate can be a silicon-based material, and its shape can be circular, square or any other desired shape. In addition, the material of the substrate can also include other element semiconductors (such as germanium), or other compound semiconductors (such as silicon carbide, gallium arsenide, indium arsenide, indium phosphide, etc.), which are not particularly limited here. The substrate is placed in an ultrasonic cleaning machine for cleaning, the liquid in the ultrasonic cleaning machine is an ethanol solution with a volume fraction of 60% to 75%, and the ultrasonic cleaning time is 5min to 15min, so as to ensure that the stains on the substrate can be effectively removed, and then the glass is rinsed with deionized water, and the water temperature is controlled at 25℃ to 45℃, and then the substrate 10 is subjected to a multi-angle blowing and drying treatment to form a functional material layer on the surface of the substrate, so that the nanopores formed subsequently are distributed in the functional material layer.

[0089] As an example, the material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound film, and the thickness d of the functional material layer is in the range of 0<d≤1 μm.

[0090] Specifically, the material of the functional material layer can be a semiconductor material, such as silicon oxide, silicon nitride and other materials, or a metal material and other etchable solid material, such as metal chromium and copper and other materials. In order to ensure the quality of the formed solid-state nanopore array, the thickness of the functional material layer should not be greater than the diameter of the formed nanopores. In this embodiment, the thickness d of the functional material layer is in the range of 0<d≤1μm, for example, it can be 0.1μm, 0.3μm, 0.5μm or 1μm. Of course, the value range of the thickness d of the functional material layer is not limited to this, and can be set according to actual needs.

[0091] In step S2, see Figure 1 and Figure 3 , performing a deposition process on the functional material layer to form a first thin film layer.

[0092] Specifically, Figure 3 As shown, a first thin film layer is formed on the functional material layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the first thin film layer is a chemical vapor deposition process; the material of the first thin film layer includes other suitable materials such as polysilicon or silicon oxide. Of course, the material of the first thin film layer is not limited to this. In this embodiment, the material of the first thin film layer is preferably polysilicon. It should be noted that the first thin film layer is used as a mask for forming a solid-state nanopore array and needs to be removed in subsequent processes. The thickness of the first thin film layer needs to be determined based on the thickness of the functional material layer and the etching selectivity ratio of the material used when etching to form the solid-state nanopore array. Its specific range is not limited here.

[0093] In step S3, see Figure 1 and Figure 4 , performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves.

[0094] As an example, the method for forming the plurality of first grooves includes dry etching or other suitable methods; specifically, in the present embodiment, the method for forming the plurality of first grooves includes: after growing the first thin film layer, setting a photoresist masking layer on the first thin film layer, exposing and developing the photoresist masking layer, and patterning the positions of the first grooves corresponding to the photoresist masking layer, such as Figure 4 As shown, the first film layer is etched along a first direction of the first film layer through a patterned photoresist mask layer to obtain a plurality of first grooves penetrating the first film layer to expose the functional material layer, and then the photoresist mask layer is removed.

[0095] As an example, the plurality of first grooves are arranged in parallel, and the shapes of the plurality of first grooves are designed as follows: Figure 4 The strips are shown, and there is a certain distance between adjacent grooves, for example, it can be 1μm, 5μm, 8μm or 10μm, and the arrangement period of multiple first grooves ultimately determines the density and scale of the solid-state nanopore array. Therefore, the distance between adjacent grooves can be designed according to the required density of the solid-state nanopore array, and is not particularly limited here.

[0096] In step S4, see Figure 1 and Figure 5 , performing a deposition process on the first thin film layer to form a first sacrificial layer, the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer.

[0097] As an example, a first sacrificial layer is formed on the first thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the first sacrificial layer is an atomic layer deposition process; the material of the first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide. Of course, the material of the first sacrificial layer is not limited thereto, but in order to distinguish it from the first thin film layer, in this embodiment, the material of the first sacrificial layer is preferably aluminum oxide. The thickness of the first sacrificial layer generally needs to be consistent with the diameter of the formed nanopore. Of course, the thickness of the first sacrificial layer is not limited thereto and can be set according to actual needs.

[0098] In step S5, refer to Figure 1 and Figure 6, forming a second film layer on the first film layer, wherein the second film layer covers the bottom of the first groove and has the same height as the first film layer, so as to expose the first sacrificial layer as a first nanostrip.

[0099] As an example, a second thin film layer is formed on the first thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, in this embodiment, the process for forming the second thin film layer is a chemical vapor deposition process; the material of the second thin film layer includes other suitable materials such as polysilicon or silicon oxide. In this embodiment, the material of the second thin film layer is preferably consistent with the material of the first thin film layer to facilitate removal in subsequent processes. Of course, the material of the first thin film layer is not limited to this and can be set according to actual needs.

[0100] Specifically, Figure 6 As shown, the formed second film layer covers the bottom of the first groove and the top of the first film layer, and then the CMP process is performed on the top of the first film layer, so that the second film layer at the bottom of the first groove has the same height as the first film layer, so as to expose the first sacrificial layer, and the exposed first sacrificial layer serves as the first nano strip. That is, the first sacrificial layer located on the side wall of the first groove is covered by the first film layer and the second film layer, and the surfaces of the first sacrificial layer, the first film layer and the second film layer are uniform and flat, which is conducive to improving the yield of the formed solid-state nanopore array.

[0101] In other embodiments, the process of forming the second thin film layer in step S5 can also be replaced by spin coating a leveling material. For example, SOG (spin on glass coating) or H-SiOx and other materials are first spin coated in the first groove, and then an annealing process or a high-temperature heating process is performed to form a hard material layer. The hard material layer is uniformly flat with the surfaces of the first sacrificial layer and the first thin film layer, and the exposed first sacrificial layer serves as the first nanostrip.

[0102] In step S6, refer to Figure 1 and Figure 7 , performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves.

[0103] Specifically, a third thin film layer is formed on the first thin film layer and the second thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the third thin film layer is a chemical vapor deposition process; the material of the third thin film layer includes other suitable materials such as polysilicon or silicon oxide. Of course, the material of the third thin film layer is not limited to this. In this embodiment, the material of the third thin film layer is preferably polysilicon. The thickness of the third thin film layer can be consistent with the thickness of the first thin film layer. Its specific thickness is not limited here. It should be noted that the third thin film layer also serves as a mask for the subsequently formed solid-state nanopore array and will be removed in the subsequent process.

[0104] As an example, the method for forming the plurality of second grooves includes dry etching or other suitable methods; specifically, in the present embodiment, the method for forming the plurality of second grooves includes: after growing the third thin film layer, setting a photoresist masking layer on the third thin film layer, exposing and developing the photoresist masking layer, and patterning the positions of the second grooves corresponding to the photoresist masking layer, such as Figure 7 As shown, the third thin film layer is etched along the second direction of the third thin film layer through a patterned photoresist mask layer to obtain a plurality of second grooves penetrating the third thin film layer to expose the first thin film layer and the first sacrificial layer, and then the photoresist mask layer is removed.

[0105] As an example, the plurality of second grooves are arranged in parallel, and the shapes of the plurality of second grooves are designed as follows: Figure 7 The strips shown have a certain distance between adjacent grooves, and the period of multiple second grooves ultimately determines the density and scale of the nanohole array. Therefore, the distance between adjacent grooves can be designed according to the required density of the nanohole array, and is not particularly limited here.

[0106] As an example, the angle θ between the first direction and the second direction is in the range of 0<θ<180°, for example, it can be 5°, 45°, 90°, 135° or 175°. Specifically, the angle between the first direction and the second direction directly affects the shape of the final nanopore. And the closer the angle is to 90°, the closer the shape of the final nanopore is to a standard square or circle.

[0107] In step S7, refer to Figure 1 and Figure 8 , performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer.

[0108] As an example, a second sacrificial layer is formed on the third thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the second sacrificial layer is an atomic layer deposition process; the material of the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide. Of course, the material of the second sacrificial layer is not limited to this. In this embodiment, the material of the second sacrificial layer is preferably an aluminum oxide layer. The thickness of the second sacrificial layer generally needs to be consistent with the diameter of the formed nanopore. Of course, the thickness of the second sacrificial layer is not limited to this and can be set according to actual needs.

[0109] In step S8, refer to Figure 1 and Fig. 9 , forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so that the exposed second sacrificial layer serves as a second nano stripe.

[0110] As an example, a fourth thin film layer is formed on the third thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the fourth thin film layer is a chemical vapor deposition process. The material of the fourth thin film layer includes other suitable materials such as polysilicon or silicon oxide. In the present embodiment, the material of the fourth thin film layer is preferably consistent with the material of the third thin film layer to facilitate removal in subsequent processes. Of course, the material of the fourth thin film layer is not limited to this and can be set according to actual needs.

[0111] Specifically, Fig. 9 As shown, the fourth film layer is formed to cover the bottom of the second groove and the top of the third film layer, and then the CMP process is performed on the top of the third film layer, so that the third film layer at the bottom of the first groove has the same height as the fourth film layer, so as to expose the second sacrificial layer as the second nano strip. That is, the second sacrificial layer located on the side wall of the second groove is covered by the third film layer and the fourth film layer, and the surfaces of the second sacrificial layer, the third film layer and the fourth film layer are uniform and flat, which is conducive to improving the yield of the formed solid-state nanopore array.

[0112] In other embodiments, the process of forming the fourth thin film layer in step S8 can also be replaced by spin coating a leveling material. For example, SOG (spin on glass coating) or H-SiOx and other materials are first spin coated in the second groove, and then an annealing process or a high-temperature heating process is performed to form a hard material layer. The hard material layer is uniformly flat with the surfaces of the second sacrificial layer and the third thin film layer, and the exposed second sacrificial layer can be used as a second nanostrip.

[0113] In step S9, refer to Figure 1 and Fig.10 , performing a wet etching process at the intersection of the first nanostrip and the second nanostrip to form a first etching cavity.

[0114] Specifically, in this embodiment, a wet etching process is performed on the intersection of the first nanostrip and the second nanostrip, so as to remove the first sacrificial layer and the second sacrificial layer at the intersection. Fig.10 As shown, a first etching cavity is formed at the intersection of the first nanostrip and the second nanostrip, and the first etching cavity is located in the first thin film layer and the second thin film layer. In the subsequent process, the first thin film layer with the first etching cavity is used as a mask for etching the functional material layer, thereby realizing the etching of the functional material layer.

[0115] In step S10, refer to Figure 1 and Fig.11 , dry-etching the functional material layer based on the first etching chamber to form a solid-state nanopore array in the functional material layer.

[0116] As an example, after forming the nanohole array in the functional material layer, the step of removing the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanostrip and the second nanostrip is also included.

[0117] Specifically, the first thin film layer having the first etching cavity is used as a mask for etching the functional material layer, and the functional material layer is etched at the position of the first etching cavity, thereby forming a plurality of nanopores in the functional material layer. After the plurality of nanopores are formed, the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nanostrip and the second nanostrip need to be removed, and only the substrate and the functional material layer are retained. At this time, the plurality of nanopores in the functional material layer constitute a solid-state nanopore array.

[0118] Specifically, as shown in the figure, the solid-state nanopore array formed in the embodiment of the present invention is a nanopore array with a two-dimensional periodic lattice arrangement, and the etching depth of the solid-state nanopore array is generally not less than the thickness of the functional material layer. For example: the etching depth of the nanopores in the solid-state nanopore array is less than the thickness of the functional material layer, which can be set according to actual needs.

[0119] In an embodiment of the present invention, a deposition process coating and a dry etching process are combined to form a first nanostrip along a first direction in the first thin film layer and the second thin film layer, and a second nanostrip along a second direction is formed in the third thin film layer and the fourth thin film layer. Then, selective etching is performed at the intersection of the first nanostrip and the second nanostrip, thereby forming a desired solid-state nanopore array pattern in the functional material layer. Compared with existing FIB, EBL, TEM, CBD and other methods, this preparation method has the advantages of fast and efficient, large-area preparation, low cost, etc., and the pore size and array scale of the formed nanopores can be accurately controlled by adjusting the process parameters, and has high repeatability.

[0120] Example 2

[0121] The present invention provides a method for preparing a solid-state nanopore array device. Fig.12 As shown, it is a process flow chart of the preparation method of the solid-state nanopore array device, which includes the following steps:

[0122] S101: providing a substrate, forming a functional material layer on which nanopores need to be prepared on the front side of the substrate, and forming a mask layer on the back side of the substrate;

[0123] S102: performing a deposition process on the functional material layer to form a first thin film layer;

[0124] S103: performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves;

[0125] S104: performing a deposition process on the first thin film layer to form a first sacrificial layer, wherein the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer;

[0126] S105: forming a second thin film layer on the first thin film layer, wherein the second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer, and the exposed first sacrificial layer serves as a first nano stripe;

[0127] S106: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves;

[0128] S107: performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer;

[0129] S108: forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so that the exposed second sacrificial layer serves as a second nano stripe;

[0130] S109: performing a deposition process on the third thin film layer and the fourth thin film layer to form a first patterned layer, wherein the first patterned layer has a plurality of third grooves, and the third grooves reveal window areas;

[0131] S110: performing an etching process on the intersection of the first nanostrip and the second nanostrip in the window area to form a second etching cavity;

[0132] S111: dry-etching the functional material layer at the window region based on the second etching chamber to form a solid nanopore array;

[0133] S112: performing an alignment process on the back side of the substrate, and etching the substrate and the mask layer using an etching process to expose the solid-state nanopore array in the window area;

[0134] S113: removing the first thin film layer, the second thin film layer, the third thin film layer, the fourth thin film layer, the first nano-strip, the second nano-strip and the first patterned layer to form the solid-state nanopore array device.

[0135] The following is a further introduction to the preparation method of the solid-state nanopore array device with reference to the accompanying drawings, as follows:

[0136] Among them, steps S101 to S108 are consistent with the contents of steps S1 to S8 in the method for preparing a solid-state nanopore array, and have been described in detail in the previous text, so they will not be repeated here.

[0137] Among them, see Fig.12 and Fig.13 In step S101, a mask layer is formed on the back side of the substrate.

[0138] As an example, a mask layer is formed on the back side of the substrate using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the mask layer is an atomic layer deposition process. The mask layer includes a silicon nitride layer or a silicon dioxide layer. Of course, the material of the mask layer is not limited thereto. In this embodiment, the material of the mask layer is preferably a silicon nitride layer. The thickness of the mask layer can be set according to actual needs.

[0139] Specifically, Fig.13 As shown, the formed mask layer covers the back side of the substrate, and the mask layer serves as a mask for a subsequent back side registration process on the back side of the substrate.

[0140] In step S109, refer to Fig.12 and Fig.14 , performing a deposition process on the third thin film layer to form a first patterned layer, wherein the first patterned layer has a plurality of third grooves, and the third grooves reveal a window area.

[0141] Specifically, a first patterned layer is formed on the third thin film layer using one of physical vapor deposition, chemical vapor deposition or atomic layer deposition. Preferably, the process for forming the first patterned layer is a chemical vapor deposition process; the material of the first patterned layer includes other suitable materials such as polysilicon or silicon oxide. Of course, the material of the first patterned layer is not limited to this.

[0142] As an example, the method for forming the first patterned layer includes dry etching or other suitable methods; specifically, in this embodiment, the method for forming the first patterned layer includes: sequentially growing a fifth thin film layer and a photoresist mask layer on the third thin film layer, exposing and developing the photoresist mask layer, and patterning the position of the third groove corresponding to the photoresist mask layer, such as Fig.14 As shown, the fifth thin film layer is etched through a patterned photoresist mask layer to obtain a first patterned layer penetrating the fifth thin film layer, and then the photoresist mask layer is removed to expose a window area in the third groove.

[0143] In step S110, refer to Fig.12 and Fig.15 , performing an etching process on the intersection of the first nanostrip and the second nanostrip in the window area to form a second etching cavity.

[0144] Specifically, in this embodiment, a wet etching process is performed on the intersection of the first nanostrip and the second nanostrip in the window area, so as to remove the first nanostrip and the second nanostrip in the window area. Fig.15As shown, a second etching cavity is formed at the exposed window area, and the second etching cavity is located in the first thin film layer and the second thin film layer. In the subsequent process, the first thin film layer and the second thin film layer with the second etching cavity are used as masks for etching the functional material layer, thereby realizing etching of the functional material layer.

[0145] In step S111, refer to Fig.12 and Fig.16 , dry-etching the functional material layer in the window area based on the second etching chamber to form a solid-state nanopore array in the functional material.

[0146] Specifically, the first thin film layer having the second etching cavity is used as a mask for etching the functional material layer, and the functional material layer is etched at the position of the second etching cavity, thereby forming a solid nanopore array in the window area of ​​the functional material layer.

[0147] In step S112, refer to Fig.12 and Fig.17 , performing an alignment process on the back side of the substrate, and etching the substrate and the mask layer using an etching process to reveal the solid-state nanopore array in the window area.

[0148] Specifically, the back side of the substrate is etched using an etching process to form the etching groove, and the etching groove reveals the solid-state nanopore array in the functional material layer. Specifically, as Fig.17 As shown, in this embodiment, an alkaline solution is selected to etch the back side of the substrate, specifically a KOH solution with a concentration of 30%. Of course, TMAH can also be selected to remove the silicon substrate and the mask layer.

[0149] In step S113, refer to Fig.12 and Fig.18 , removing the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanostrip, the second nanostrip and the first patterned layer to form the solid-state nanopore array device.

[0150] Specifically, after forming multiple nanoholes in the window area and completing the registration process, it is necessary to remove the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanostrip, the second nanostrip and the first patterned layer, and only retain the mask layer, the substrate and the functional material layer to form the solid-state nanohole array device.

[0151] In the embodiments of the present invention, the aperture and array size of the formed nanopores can be precisely controlled by adjusting the process parameters, with high repeatability. Different window areas can also be selectively designed according to actual needs to achieve customization of solid-state nanopore array devices with different numbers of nanopores. The preparation method is applicable to a variety of solid materials and is fully compatible with existing CMOS process technology, achieving large-scale integrated manufacturing of solid-state nanopore array devices, thereby significantly reducing preparation costs.

[0152] Example 3

[0153] This embodiment also provides a solid-state nanopore array device, which is obtained by the preparation method of the solid-state nanopore array device mentioned in the above content.

[0154] Example 4

[0155] This embodiment also provides an application of a solid-state nanopore array device in electrochemical signal analysis, high-throughput analysis and detection of biological molecules such as DNA and proteins. Specifically, a single-hole / double-hole solid-state nanopore array device is obtained by using the preparation method of the solid-state nanopore array device in the above-mentioned embodiment 2, wherein the diameter of the nanopore is about 40nm, and conductivity testing and biological molecule detection analysis are performed based on the obtained single-hole / double-hole solid-state nanopore array device, such as Fig.19 As shown, it is a schematic diagram of the structure of the single-hole / double-hole solid-state nanopore array device in the embodiment of the present invention when conducting conductivity testing and biomolecule detection analysis, wherein: Fig.19 a is a single-hole solid-state nanopore array device, Fig.19 b is a double-hole solid-state nanopore array device. Driven by ionic current, DNA molecules move from the cathode through the nanopores in the solid-state nanopore array device to the anode, thereby obtaining a blocking current signal.

[0156] The test solution was 1.8M LiCl solution, and the conductivity of the single-hole / double-hole solid-state nanopore array device was as follows: Fig. 20 As shown. Fig. 20 It can be seen that the conductivity of the single-hole solid-state nanopore array device is about 247nS, and the conductivity of the double-hole solid-state nanopore array device is about 458nS.

[0157] The single-hole / double-hole solid-state nanopore array device is used to detect and analyze DNA molecules, wherein the DNA molecule is phiX174 DNA molecule, and the concentration is about 3nM. Specifically, under a constant bias voltage of 60mV, after the signal is stabilized, the relationship curve between the current and time of the single-hole / double-hole solid-state nanopore array device within 100s is obtained, as shown in FIG. Fig.21 shown. Fig. 22The signal statistics corresponding to the single-hole / double-hole solid-state nanopore array device are shown. Through calculation, it can be seen that the capture rate per unit time of the single-hole solid-state nanopore array device is 0.25 / s, and the capture rate per unit time of the double-hole solid-state nanopore array device is 0.66 / s. Therefore, it can be seen that the double-hole solid-state nanopore array device has a higher capture rate and a higher detection flux.

[0158] In summary, the preparation method and application of the solid-state nanopore array and the solid-state nanopore array device of the present invention have the following beneficial effects: the preparation method of the solid-state nanopore array combines the deposition process coating and the dry etching process to form a first nano strip along the first direction in the first film layer and the second film layer, and forms a second nano strip along the second direction in the third film layer and the fourth film layer, and then selectively etches at the intersection of the first nano strip and the second nano strip, so as to form the required solid-state nanopore array pattern in the functional material layer. Compared with the existing FIB, EBL, TEM and CBD methods, the preparation method has the advantages of fast and efficient, large-area preparation, low cost, etc., and the aperture and array scale of the formed nanopores can be accurately controlled by adjusting the process parameters, and has high repeatability; the preparation method of the solid-state nanopore array device proposed based on the solid-state nanopore array can be applied to a variety of solid materials and is fully compatible with the existing CMOS process technology, realizing large-scale integrated manufacturing of solid-state nanopore array devices, thereby significantly reducing the preparation cost. In addition, the solid-state nanopore array device of the present invention can also realize high-throughput analysis and detection of electrochemical signals, as well as biomolecules such as DNA or protein. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0159] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a solid-state nanopore array, characterized in that: The method for preparing the solid-state nanopore array comprises the following steps: S1: providing a substrate, and forming a functional material layer on the front side of the substrate where nanopores need to be prepared; S2: performing a deposition process on the functional material layer to form a first thin film layer; S3: performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves; S4: performing a deposition process on the first thin film layer to form a first sacrificial layer, wherein the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer; S5: forming a second thin film layer on the first thin film layer, wherein the second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer, and the exposed first sacrificial layer serves as a first nano stripe; S6: performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves; S7: performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer; S8: forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so as to expose the second sacrificial layer as a second nano strip; S9: performing an etching process at the intersection of the first nanostrip and the second nanostrip to form a first etching cavity; S10: performing dry etching on the functional material layer based on the first etching chamber to form a solid nanopore array in the functional material layer.

2. The method for preparing a solid-state nanopore array according to claim 1, characterized in that: After forming the solid-state nanopore array in the functional material layer, the method further includes removing the first film layer, the second film layer, the third film layer, the fourth film layer, the first nanostrip and the second nanostrip.

3. The method for preparing a solid-state nanopore array according to claim 1, characterized in that: The angle θ between the first direction and the second direction is in the range of 0<θ<180°.

4. The method for preparing a solid-state nanopore array according to claim 1, characterized in that: The deposition process is one of physical vapor deposition, chemical vapor deposition or atomic layer deposition.

5. The method for preparing a solid-state nanopore array according to claim 1, characterized in that: The first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide, and the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide.

6. The method for preparing a solid-state nanopore array according to any one of claims 1 to 5, characterized in that: The material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound film, and the thickness d of the functional material layer is in the range of 0<d≤1μm.

7. The method for preparing a solid-state nanopore array according to claim 6, characterized in that: The first film layer and the second film layer are made of the same material, and the third film layer and the fourth film layer are made of the same material.

8. The method for preparing a solid-state nanopore array according to claim 6, characterized in that: The etching depth of the functional material layer subjected to dry etching is not less than the thickness of the functional material layer.

9. A method for preparing a solid-state nanopore array device, characterized in that: The method for preparing the solid-state nanopore array device comprises the following steps: Providing a substrate, forming a functional material layer on which nanopores are to be prepared on the front side of the substrate, and forming a mask layer on the back side of the substrate; Performing a deposition process on the functional material layer to form a first thin film layer; Performing a first dry etching on the first thin film layer along a first direction of the first thin film layer to form a plurality of first grooves; Performing a deposition process on the first thin film layer to form a first sacrificial layer, wherein the first sacrificial layer covers the bottom and sidewalls of the first groove and the top of the first thin film layer, and etching to remove the first sacrificial layer covering the bottom of the first groove and the top of the first thin film layer; forming a second thin film layer on the first thin film layer, wherein the second thin film layer covers the bottom of the first groove and has the same height as the first thin film layer, and the exposed first sacrificial layer serves as a first nano strip; Performing a deposition process on the first thin film layer and the second thin film layer to form a third thin film layer, and performing a second dry etching on the third thin film layer along a second direction of the third thin film layer to form a plurality of second grooves; Performing a deposition process on the third thin film layer to form a second sacrificial layer, wherein the second sacrificial layer covers the bottom and sidewalls of the second groove and the top of the third thin film layer, and etching to remove the second sacrificial layer covering the bottom of the second groove and the top of the third thin film layer; forming a fourth thin film layer on the third thin film layer, wherein the fourth thin film layer covers the bottom of the second groove and has the same height as the third thin film layer, so that the exposed second sacrificial layer serves as a second nano strip; Performing a deposition process on the third thin film layer and the fourth thin film layer to form a first patterned layer, wherein the first patterned layer has a plurality of third grooves, and the third grooves reveal window areas; Performing an etching process on the intersection of the first nanostrip and the second nanostrip in the window area to form a second etching cavity; Based on the second etching chamber, dry-etching the functional material layer at the window area forms a solid-state nanopore array; Performing an alignment process on the back side of the substrate, and etching the substrate and the mask layer using an etching process to expose the solid-state nanohole array in the window area; The first film layer, the second film layer, the third film layer, the fourth film layer, the first nanostrip, the second nanostrip and the first patterned layer are removed to form the solid-state nanopore array device.

10. The method for preparing a solid-state nanopore array device according to claim 9, characterized in that: The angle θ between the first direction and the second direction is in the range of 0<θ<180°.

11. The method for preparing a solid-state nanopore array device according to claim 9, characterized in that: The material forming the functional material layer includes at least one of metal, non-metal, metal compound and non-metal compound film, and the thickness d of the functional material layer is in the range of 0<d≤1μm.

12. The method for preparing a solid-state nanopore array device according to claim 9, characterized in that: The first sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide, and the second sacrificial layer includes at least one of silicon oxide, hafnium oxide, titanium nitride, magnesium oxide, zinc oxide, and aluminum oxide.

13. The method for preparing a solid-state nanopore array device according to claim 9, characterized in that: The first film layer and the second film layer are made of the same material, and the third film layer and the fourth film layer are made of the same material.

14. The method for preparing a solid-state nanopore array device according to claim 9, characterized in that: The etching depth of the functional material layer subjected to dry etching is not less than the thickness of the functional material layer.

15. A solid-state nanopore array device, characterized in that: The solid-state nanopore array device is obtained by the preparation method of the solid-state nanopore array device according to any one of claims 9 to 14.

16. Application of the solid-state nanopore array device according to claim 15 in electrochemical signal analysis, high-throughput analysis and detection of biological molecules such as DNA and protein.

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