High-speed current detection circuit and power supply circuit

Abstract

The invention provides a high-speed current detection circuit and a power supply circuit. The high-speed current detection circuit comprises a to-be-detected power switch tube, a current detection module, a switch module and a copying module. The current detection module is connected with the to-be-detected power switch tube and is used for detecting the to-be-detected power switch tube and generating detection current; the switch module is connected with the current detection module and used for controlling output detection current; and the copying module is connected with the current detection module and the switch module and is used for copying the detection current output by the switch module and feeding back the detection current to the current detection module, so that the jump amplitude of the detection current is reduced when the power switch tube to be detected is switched between the closed state and the on state. The power supply circuit comprises a high-speed current detection circuit. According to the current detection circuit, the copying module copies the detection current and feeds back the detection current to the current detection module, so that the jump amplitude of the circuit is reduced, the time required for the circuit to be stable is reduced, the detection efficiency of the circuit is improved, and the application range of the current detection circuit is expanded.

Description

Background Art

[0002] Current detection circuit plays a vital role in power supply system, and can be used for loop control, overcurrent protection, zero-crossing detection and other functions. Therefore, current detection circuit has become an indispensable part of most power supply circuit designs. There are many ways to detect current in power supply circuits, but directly detecting the voltage drop of the power switch tube in the on state is a low-cost and highly reliable detection solution.

[0003] In the related art, the current detection circuit includes an upper tube and a lower tube, wherein the lower tube is used as the power switch tube to be detected. When the power switch tube is turned on, it can be equivalent to a resistor R, and when it is turned on, the output voltage can be expressed as V= -IL*R. Therefore, as long as the V when the power switch tube is turned on can be sampled, the current value I can be obtained. The current detection circuit needs to detect the voltage difference from the output end to the ground end of the power switch tube, so it is necessary to convert the current of the power switch tube into a voltage signal. And the voltage signal output is sent to the subsequent control loop and other comparator circuits for overcurrent protection. After the power switch tube is turned off, the current flowing through the power switch tube is 0A. After the power switch tube is turned on, the current of the power switch tube needs to jump quickly to a relatively high current value. At the same time, the detection current generated by the current detection circuit also needs to jump quickly to a higher current value. Because this jump amplitude is large, the current detection circuit takes a relatively long time to achieve stability. In addition, the minimum on-time of the power switch tube must be longer than the time required for stabilization, otherwise the subsequent control loop will not be able to detect the effective current. The time required for stabilization is usually much higher than 100ns, thus limiting the minimum on-time of the power switch. For example, in the application of a high-frequency buck converter, if the minimum on-time of the power switch exceeds 100ns, the application range of the buck converter will be limited, thereby limiting the output voltage of the buck converter to a lower range. Summary of the invention

[0004] The present application provides a high-speed current detection circuit and a power supply circuit which are intended to reduce the circuit jump amplitude, shorten the stabilization time, and expand the application range.

[0005] In a first aspect, the present application provides a high-speed current detection circuit, comprising: The power switch tube M1 to be tested; A current detection module, connected to the power switch tube M1 to be tested, used to detect the power switch tube M1 to be tested and generate a detection current; A switch module, connected to the current detection module, and used to control the output of the detection current; The copy module is connected to the current detection module and the switch module, and is used to copy the detection current output by the switch module and feed it back to the current detection module, so that when the power switch tube M1 to be tested switches between the off state and the on state, the jump amplitude of the detection current is reduced.

[0006] In the above technical solution, a copy module is set to copy the detection current output by the switch module and feed it back to the current detection module, so that when the power switch tube to be tested switches between off and on, the jump amplitude of the current detection circuit is significantly reduced, thereby reducing the time required for the current detection circuit to reach stability. This not only improves the detection efficiency of the circuit, but also helps to expand the application scope of the current detection circuit.

[0007] Optionally, the high-speed current detection circuit includes a power supply terminal; the replication module includes a first MOS tube M11, a first resistor R12, a second MOS tube M12 and a third MOS tube M13; wherein, The gate of the first MOS tube M11 is connected to the output end of the switch module, the drain is connected to the power supply end, and the source is connected to the drain of the second MOS tube M12 through the first resistor R12; the gate of the second MOS tube M12 is short-circuited with its drain, and the source is grounded; the gate of the third MOS tube M13 is connected to the gate of the second MOS tube M12, the drain is connected to the current detection module, and the source is grounded.

[0008] Optionally, the current detection module further includes a detection unit and an error amplification unit; The detection unit includes a fourth MOS tube M2, a fifth MOS tube M3, a sixth MOS tube M4, a seventh MOS tube M5, an eighth MOS tube M6, and a ninth MOS tube M7; The drain of the fourth MOS tube M2 is connected to the source of the power switch tube M1 to be tested, the gate is connected to the power supply end, and the source is connected to the drain of the fifth MOS tube M3; the gate of the fifth MOS tube M3 is connected to the power supply end, and the source is connected to the source of the sixth MOS tube M4; the gate of the sixth MOS tube M4 is connected to the power supply end, and the drain is connected to the error amplification unit; the drain of the seventh MOS tube M5 is connected to the drain of the power switch tube M1 to be tested, the gate is connected to the gate of the power switch tube M1 to be tested, and the source is connected to the drain of the eighth MOS tube M6; the gate of the eighth MOS tube M6 is connected to the power supply end, and the source is connected to the source of the ninth MOS tube M7; the gate of the ninth MOS tube M7 is connected to the power supply end, and the drain is connected to the error amplification unit and the copy module.

[0009] Optionally, the error amplification unit includes an error amplifier Error Amp and a tenth MOS tube M8; wherein, The non-inverting input terminal of the error amplifier Error Amp is connected to the drain of the sixth MOS tube M4, the inverting input terminal of the error amplifier Error Amp is connected to the drain of the ninth MOS tube M7, and the output terminal of the error amplifier Error Amp is connected to the gate of the tenth MOS tube M8; the source of the tenth MOS tube M8 is connected to the drain of the ninth MOS tube M7 and the replica module, and the drain is connected to the switch module.

[0010] Optionally, the switch module includes an eleventh MOS transistor M9, a twelfth MOS transistor M10, a capacitor C1 and a first switch switch1; wherein, The drain of the eleventh MOS tube M9 is connected to the drain of the tenth MOS tube M8, the source is connected to the power supply end, the gate is short-circuited with its drain and connected to the gate of the twelfth MOS tube M10 through the first switch switch1; the source of the twelfth MOS tube M10 is connected to the power supply end, and the drain is connected to the gate of the first MOS tube; one end of the capacitor C1 is connected between the first switch switch1 and the gate of the twelfth MOS tube M10, and the other end is connected to the power supply end.

[0011] Optionally, the high-speed current detection circuit further includes a detection current output terminal; the current detection module further includes a current detection output unit, and the current detection output unit includes a first amplifier OP2, a second amplifier OP3, a third amplifier OP1 and a second resistor R1; wherein, The positive phase input terminal of the first amplifier OP2 is connected to the reference voltage, the negative phase input terminal of the first amplifier OP2 is connected to the negative phase input terminal of the second amplifier OP3, the output terminal of the first amplifier OP2 is short-circuited with its negative phase input terminal and connected to the drain of the twelfth MOS tube M10 through the second resistor; the positive phase input terminal of the second amplifier OP3 is connected to the negative phase input terminal of the third amplifier OP1, the negative phase input terminal of the second amplifier OP3 is connected to the output terminal of the first amplifier OP2, and the output terminal of the second amplifier OP3 is used to output the zero current clock detection signal ZC; the positive phase input terminal of the third amplifier OP1 is connected between the drain of the twelfth MOS tube M10 and the second resistor, the negative phase input terminal of the third amplifier OP1 is short-circuited with the output terminal, and the output terminal of the third amplifier OP1 is connected to the detection current output terminal.

[0012] Optionally, the copy module further includes a second switch switch2, one end of the second switch switch2 is connected to the drain of the third MOS tube M13, and the other end of the second switch switch2 is connected to the source of the tenth MOS tube M8 and the drain of the ninth MOS tube M7.

[0013] Optionally, the detection unit further includes an inverter LSGATE and a thirteenth MOS tube M15, wherein: The input end of the inverter LSGATE is connected to the gate of the power switch tube M1 to be tested; the gate of the thirteenth MOS tube M15 is connected to the output end of the inverter LSGATE, the drain is connected to the source of the seventh MOS tube M5, and the source is connected to the drain of the fourth MOS tube M2.

[0014] Optionally, it further comprises a first current source Ib1, one end of the first current source Ib1 is connected to the power supply end, and the other end is connected to the non-inverting input end of the error amplifier Error Amp; and / or The second current source Ib2 is also included. One end of the second current source Ib2 is connected to the drain of the twelfth MOS transistor M10, and the other end is grounded.

[0015] In a second aspect, the present application also provides a power supply circuit, including the high-speed current detection circuit described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure shows a structural block diagram of a high-speed current detection circuit provided by an embodiment of the present application; Figure 2 for Figure 1 A circuit diagram of a high-speed current detection circuit according to an embodiment of the present invention; Figure 3 for Figure 2 A specific circuit diagram showing the connection between the replica module in the high-speed current detection circuit of an embodiment and the first resistor R1 and the first amplifier OP2; Figure 4 A waveform diagram of a high-speed current detection circuit before a replication module is provided in an embodiment of the present application; Figure 5 A waveform diagram of a high-speed current detection circuit after a replication module is provided in an embodiment of the present application; Figure 6 Shown is a simulation schematic diagram of a high-speed current detection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The present application is further described in detail below through the accompanying drawings and embodiments. Through these descriptions, the characteristics and advantages of the present application will become clearer and more specific.

[0018] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.

[0019] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0020] The present application provides a high-speed current detection circuit and a power supply circuit to improve the current detection speed. The following is a detailed description of the embodiments in conjunction with specific drawings.

[0021] refer to Figure 1 As shown, a high-speed current detection circuit provided by the present application includes a power switch tube M1 to be tested, a current detection module 1, a switch module 2, and a copy module 3. The current detection module 1 is connected to the power switch tube M1 to be tested, and is used to detect the power switch tube M1 to be tested and generate a detection current. The switch module 2 is connected to the current detection module 1, and is used to control the output of the detection current. The copy module 3 is connected to the current detection module 1 and the switch module 2, and is used to copy the detection current output by the switch module 2, and feed it back to the current detection module 1, so that when the power switch tube M1 to be tested switches between the off state and the on state, the jump amplitude of the detection current is reduced.

[0022] The current detection circuit detects the current of the power switch tube M1 to be tested through the current detection module 1 to identify whether the relevant application device has abnormal phenomena such as overcurrent or overvoltage. In the related art, when the power switch tube M1 to be tested switches between the off state and the on state during the current detection circuit, a large voltage difference will be generated in the switch module 2, so that the jump amplitude of the detection current is large, thereby increasing the time required for the current detection circuit to reach a stable state. In this embodiment, in order to avoid the situation where the detection current in the current detection circuit has a high jump amplitude, the detection current Ic output by the switch module 2 is copied by setting the copy module 3 and fed back to the current detection module 1, so that when the power switch tube M1 to be tested switches between off and on, the jump amplitude of the current detection circuit is significantly reduced, thereby reducing the time required for the current detection circuit to reach stability. In this way, not only the detection efficiency of the circuit is improved, but also it helps to expand the application range of the current detection circuit.

[0023] like Figure 2 As shown, in a specific possible implementation scheme, the high-speed current detection circuit includes a power supply terminal VDRV; the current detection module 1 also includes a detection unit 10 and an error amplification unit 11; The detection unit 10 includes a fourth MOS tube M2, a fifth MOS tube M3, a sixth MOS tube M4, a seventh MOS tube M5, an eighth MOS tube M6, and a ninth MOS tube M7; The drain of the fourth MOS tube M2 is connected to the source of the power switch tube M1 to be tested, the gate is connected to the power supply terminal VDRV, and the source is connected to the drain of the fifth MOS tube M3; the gate of the fifth MOS tube M3 is connected to the power supply terminal VDRV, and the source is connected to the source of the sixth MOS tube M4; the gate of the sixth MOS tube M4 is connected to the power supply terminal VDRV, and the drain is connected to the error amplification unit 11; the drain of the seventh MOS tube M5 is connected to the drain of the power switch tube M1 to be tested, the gate is connected to the gate of the power switch tube M1 to be tested, and the source is connected to the drain of the eighth MOS tube M6; the gate of the eighth MOS tube M6 is connected to the power supply terminal VDRV, and the source is connected to the source of the ninth MOS tube M7; the gate of the ninth MOS tube M7 is connected to the power supply terminal VDRV, and the drain is connected to the error amplification unit 11 and the copy module 3.

[0024] In this embodiment, the fourth MOS tube M2, the fifth MOS tube M3, the sixth MOS tube M4, the seventh MOS tube M5, the eighth MOS tube M6 and the ninth MOS tube M7 are current detection MOS tubes, through which the current when the power switch tube M1 to be tested is turned on can be accurately detected.

[0025] In a specific implementation scheme, the error amplification unit 11 includes an error amplifier Error Amp and a tenth MOS tube M8. The positive input terminal of the error amplifier Error Amp is connected to the drain of the sixth MOS tube M4, the negative input terminal of the error amplifier Error Amp is connected to the drain of the ninth MOS tube M7, and the output terminal of the error amplifier Error Amp is connected to the gate of the tenth MOS tube M8; the source of the tenth MOS tube M8 is connected to the drain of the ninth MOS tube M7 and the replica module 3, and the drain is connected to the switch module 2. In this embodiment, the error amplification unit 11 amplifies the detection current through the error amplifier Error Amp and the tenth MOS tube M8, so as to improve the detection accuracy of the current detection circuit.

[0026] The high-speed current detection circuit also includes a first current source Ib1, which provides a first current Ib1 to the branch where the positive phase input terminal of the error amplifier Error Amp is located. One end of the first current source Ib1 is connected to the power supply terminal VDRV, and the other end is connected to the positive phase input terminal of the error amplifier Error Amp.

[0027] In the present application, the large gain characteristic of the error amplifier Error Amp is utilized. When the error amplifier Error Amp is working normally, the voltages of its positive input terminal PGNDSNS and negative input terminal SWSNS are forced to be the same, that is, U (PGNDSNS) = U (SWSNS), formula ①.

[0028] When the power switch tube M1 to be tested is turned on, it can be equivalent to a resistor R, and PGND is the reference ground. Then when the power switch tube M1 to be tested is turned on, the voltage at the SW point is Vsw= -IL*R, that is, the voltage value of the branch where the fourth MOS tube M2, the fifth MOS tube M3, and the sixth MOS tube M4 are located, where I is the current flowing through the power switch tube M1 to be tested. Let the total resistance of the fourth MOS tube M2, the fifth MOS tube M3, and the sixth MOS tube M4 be RSNS1; the total resistance of the seventh MOS tube M5, the eighth MOS tube M6, and the ninth MOS tube M7 be RSNS2. Since the current detection MOS tubes are set to be the same, RSNS1=RSNS2, formula ②.

[0029] In addition, a first current source Ib1 is also provided, so U(PGNDSNS)=IL*R+Ib1*RSNS1, formula ③. According to the above formulas ①, ②, and ③, Ia=Ib1+IL*R / RSNS2 is obtained, where Ia is the current flowing through the seventh MOS tube M5, the eighth MOS tube M6, and the ninth MOS tube M7, and is also the current output by the tenth MOS tube M8.

[0030] Further, in a specific implementation scheme, the switch module 2 includes an eleventh MOS tube M9, a twelfth MOS tube M10, a capacitor C1 and a first switch switch1. The drain of the eleventh MOS tube M9 is connected to the drain of the tenth MOS tube M8, the source is connected to the power supply terminal, the gate is short-circuited with its drain and connected to the gate of the twelfth MOS tube M10 through the first switch switch1; the source of the twelfth MOS tube M10 is connected to the power supply terminal, and the drain is connected to the gate of the first MOS tube; one end of the capacitor C1 is connected between the first switch switch1 and the gate of the twelfth MOS tube M10, and the other end is connected to the power supply terminal.

[0031] In this embodiment, combined with the scheme in the above embodiment, since the eleventh MOS tube M9 and the twelfth MOS tube M10 are current mirror structures, the current flowing through the twelfth MOS tube M10 is also Ia=Ib1+IL*R / RSNS2, formula ④. In the present application, a second current source Ib2 is also provided, one end of which is connected to the drain of the twelfth MOS tube M10, and the other end is grounded. Furthermore, the current output by the switch module 2, that is, the current output by the twelfth MOS tube M10 is Ic=Ia-Ib2, formula ⑤. In the present application, the first current source Ib1 is set to be the same as the second current source Ib2, that is, Ib1=Ib2, formula ⑥. According to formulas ④, ⑤, and ⑥, Ic=Ib1+IL*R / RSNS2-Ib2=IL*R / RSNS2 is obtained, formula ⑦. It can be seen from formula ⑦ that Ic is in direct proportion to IL.

[0032] Further, in a specific implementation scheme, the high-speed current detection circuit also includes a detection current output terminal CSA_OUT_BUF; the current detection module 1 also includes a current detection output unit 12, and the current detection output unit 12 includes a first amplifier OP2, a second amplifier OP3, a third amplifier OP1 and a second resistor R1; wherein the positive phase input terminal of the first amplifier OP2 is connected to the reference voltage VREF, the negative phase input terminal of the first amplifier OP2 is connected to the negative phase input terminal of the second amplifier OP3, and the output terminal of the first amplifier OP2 is short-circuited with its negative phase input terminal and connected to the drain of the twelfth MOS tube M10 through the second resistor. The positive phase input terminal of the second amplifier OP3 is connected to the negative phase input terminal of the third amplifier OP1, the negative phase input terminal of the second amplifier OP3 is connected to the output terminal of the first amplifier OP2, and the output terminal of the second amplifier OP3 is used to output a zero current clock detection signal ZC. The positive phase input terminal of the third amplifier OP1 is connected between the drain of the twelfth MOS tube M10 and the second resistor R1, the negative phase input terminal of the third amplifier OP1 is short-circuited with the output terminal, and the output terminal of the third amplifier OP1 is connected to the detection current output terminal CSA_OUT_BUF. In the present application, by setting the first amplifier OP2, the second amplifier OP3, the third amplifier OP1 and the second resistor R1, when Ic flows through the second resistor R1, CSA_OUT_BUF=VREF+Ic*R1 is obtained, formula ⑧; according to the above formulas ⑦ and ⑧, CSA_OUT_BUF=VREF+IL*R*R1 / RSNS2 is obtained, formula ⑨. In this way, the current value I of the power switch tube M1 to be tested, that is, the detection current, can be obtained by formula ⑨. According to formula ⑨, when the current value of the power switch tube M1 to be tested is switched from 0A to I, the jump amplitude of CSA_OUT_BUF also increases accordingly, so that the current Ia output by the tenth MOS tube M8 also increases accordingly. Therefore, before the copy module 3 is set, when the first switch Switch1 is turned on, the voltage difference between the VGS_M9 of the eleventh MOS tube M9 and the VGS_M10 of the twelfth MOS tube M10 is large, so the current detection circuit needs a relatively long time to achieve stability. After the copy module 3 is set in parallel with the switch module 2, the voltage difference between the VGS_M9 of the eleventh MOS tube M9 and the VGS_M10 of the twelfth MOS tube M10 becomes smaller, and even reaches the optimal state of almost zero voltage difference, so the time required for the current detection circuit to stabilize can be significantly reduced, and the current detection speed is improved.

[0033] Combination Figure 2 , Figure 3As shown, in a specific implementation scheme, the copy module 3 includes a first MOS tube M11, a first resistor R12, a second MOS tube M12 and a third MOS tube M13. The gate of the first MOS tube M11 is connected to the output terminal CSA_OUT of the switch module 2, the drain is connected to the power supply terminal VDRV, and the source is connected to the drain of the second MOS tube M12 through the first resistor R12; the gate of the second MOS tube M12 is short-circuited with its drain, and the source is grounded; the gate of the third MOS tube M13 is connected to the gate of the second MOS tube M12, the drain is connected to the current detection module 1, and the source is grounded.

[0034] In this embodiment, the detection current Ic output by the switch module 2 is replicated by setting the first MOS transistor M11, the first resistor R12, the second MOS transistor M12 and the third MOS transistor M13. Specifically, According to the first amplifier OP2 and the second resistor R1 and setting the output voltage of the first amplifier OP2 to 1V, Ic=(CSA_OUT-1V) / R1 can be obtained, formula ⑩; at the same time, the current Im flowing through the first MOS tube M11 and the second MOS tube M12=(CSA_OUT-VGS_M12-VGS_M11) / R12, formula ⑪, wherein VGS_M12 is the gate-source voltage of the second MOS tube M12, and VGS_M11 is the gate-source voltage of the first MOS tube M11.

[0035] Further, the twelfth MOS tube M12 in the present application is a conventional NMOS tube, and its gate-source voltage VGS_M12 is 800mV; the eleventh MOS tube M11 is a NativeNMOS tube, and its gate-source voltage VGS_M11 is 200mV. Therefore, VGS_M12+VGS_M11=1V, formula ⑫. According to the above formulas ⑩, ⑪ and ⑫, the current flowing through the twelfth MOS tube M12 is (CSA_OUT-1V) / R2; and R1=R12 is set, so that the current flowing through the second MOS tube M12 is Im=Ic.

[0036] Furthermore, the second MOS tube M12 and the third MOS tube M13 form a current mirror structure, so the current flowing through the third MOS tube M13 is also equal to Ic. In this way, the purpose of copying the current Ic is achieved. That is to say, the detection current Ic output by the switch module 2 is copied through the first MOS tube M11, the first resistor R12, the second MOS tube M12 and the third MOS tube M13, and then fed back to the current detection module 1.

[0037] Combination Figure 4 , Figure 5As shown, the simulation results show that after the copy module 3 feeds back the copied detection current Ic to the current detection module 1, compared with the traditional circuit, the jump amplitude of Ia in the circuit of the present application is significantly reduced, and stability can be achieved quickly. In addition, the voltage difference between VGS_M9 of the eleventh MOS tube M9 and VGS_M10 of the twelfth MOS tube M10 is also significantly reduced.

[0038] like Figure 6 As shown, waveform A represents the voltage variation of the output terminal CSA_OUT in the circuit of the present application over time, and waveform B represents the voltage variation of the output terminal CSA_OUT in the traditional circuit over time. According to waveforms A and B, the voltage rise time in the circuit of the present application is significantly less than the voltage rise time in the traditional circuit, thereby significantly reducing the minimum on-time of the power switch tube M1 to be tested, and the minimum on-time can be reduced to less than 100ns. In this way, for a high-frequency buck converter, if the operating frequency is 3MHz, one cycle is only 333ns. In this way, by reducing the minimum on-time of the power switch tube M1 to be tested, it is helpful to expand the application range of the current detection circuit (the range of VIN, VOUT).

[0039] In a specific embodiment, Figure 2 As shown, the copy module further includes a second switch switch2, one end of the second switch switch2 is connected to the drain of the third MOS tube M13, and the other end is connected to the source of the tenth MOS tube M8 and the drain of the ninth MOS tube M7. In this embodiment, by setting the second switch switch2, the switch control of the copy module is realized, and the control is simple, reliable and low in cost.

[0040] In a specific implementation scheme, the detection unit also includes an inverter INV and a thirteenth MOS tube M15, wherein the input end of the inverter INV is connected to the gate of the power switch tube M1 to be tested; the gate of the thirteenth MOS tube M15 is connected to the output end of the inverter LSGATE, the drain is connected to the source of the seventh MOS tube M5, and the source is connected to the drain of the fourth MOS tube M2.

[0041] The present application also provides a power supply circuit, comprising the high-speed current detection circuit described above.

[0042] The present application sets a copy module 3 to copy the detection current Ic output by the switch module 2 and feeds it back to the current detection module 1, so that when the power switch tube M1 to be tested switches between off and on, the jump amplitude of the current detection circuit is significantly reduced, thereby reducing the time required for the current detection circuit to reach stability. In this way, not only the detection efficiency of the circuit is improved, but also it helps to expand the application scope of the current detection circuit.

[0043] Those skilled in the art will appreciate that the present application may be implemented as a system, method or computer program product.

[0044] Therefore, the present disclosure may be specifically implemented in the following forms, namely: it may be completely hardware, it may be completely software (including firmware, resident software, microcode, etc.), or it may be a combination of hardware and software, generally referred to herein as a "circuit", "module" or "system". In addition, in some embodiments, the present application may also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium may contain computer-readable program code.

[0045] Any combination of one or more computer-readable media can be used. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0046] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present application. On this basis, a variety of replacements and improvements can be made to the present application, all of which fall within the scope of protection of the present application.

Claims

1. A high-speed current detection circuit, characterized in that: include: The power switch tube M1 to be tested; A current detection module, connected to the power switch tube M1 to be tested, used to detect the power switch tube M1 to be tested and generate a detection current; A switch module, connected to the current detection module, and used to control the output of the detection current; The copy module is connected to the current detection module and the switch module, and is used to copy the detection current output by the switch module and feed it back to the current detection module, so that when the power switch tube M1 to be tested switches between the off state and the on state, the jump amplitude of the detection current is reduced.

2. The high-speed current detection circuit according to claim 1, characterized in that: The high-speed current detection circuit includes a power supply terminal; the replication module includes a first MOS tube M11, a first resistor R12, a second MOS tube M12 and a third MOS tube M13; in, The gate of the first MOS tube M11 is connected to the output end of the switch module, the drain is connected to the power supply end, and the source is connected to the drain of the second MOS tube M12 through the first resistor R12; the gate of the second MOS tube M12 is short-circuited with its drain, and the source is grounded; the gate of the third MOS tube M13 is connected to the gate of the second MOS tube M12, the drain is connected to the current detection module, and the source is grounded.

3. The high-speed current detection circuit according to claim 2, characterized in that: The current detection module also includes a detection unit and an error amplification unit; The detection unit includes a fourth MOS tube M2, a fifth MOS tube M3, a sixth MOS tube M4, a seventh MOS tube M5, an eighth MOS tube M6, and a ninth MOS tube M7; The drain of the fourth MOS tube M2 is connected to the source of the power switch tube M1 to be tested, the gate is connected to the power supply end, and the source is connected to the drain of the fifth MOS tube M3; the gate of the fifth MOS tube M3 is connected to the power supply end, and the source is connected to the source of the sixth MOS tube M4; the gate of the sixth MOS tube M4 is connected to the power supply end, and the drain is connected to the error amplification unit; the drain of the seventh MOS tube M5 is connected to the drain of the power switch tube M1 to be tested, the gate is connected to the gate of the power switch tube M1 to be tested, and the source is connected to the drain of the eighth MOS tube M6; the gate of the eighth MOS tube M6 is connected to the power supply end, and the source is connected to the source of the ninth MOS tube M7; the gate of the ninth MOS tube M7 is connected to the power supply end, and the drain is connected to the error amplification unit and the copy module.

4. The high-speed current detection circuit according to claim 3, characterized in that: The error amplification unit includes an error amplifier Error Amp and a tenth MOS tube M8; wherein, The non-inverting input terminal of the error amplifier Error Amp is connected to the drain of the sixth MOS tube M4, the inverting input terminal of the error amplifier Error Amp is connected to the drain of the ninth MOS tube M7, and the output terminal of the error amplifier Error Amp is connected to the gate of the tenth MOS tube M8; the source of the tenth MOS tube M8 is connected to the drain of the ninth MOS tube M7 and the replica module, and the drain is connected to the switch module.

5. The high-speed current detection circuit according to claim 4, characterized in that: The switch module includes an eleventh MOS transistor M9, a twelfth MOS transistor M10, a capacitor C1 and a first switch switch1; wherein, The drain of the eleventh MOS tube M9 is connected to the drain of the tenth MOS tube M8, the source is connected to the power supply end, the gate is short-circuited with its drain and connected to the gate of the twelfth MOS tube M10 through the first switch switch1; the source of the twelfth MOS tube M10 is connected to the power supply end, and the drain is connected to the gate of the first MOS tube; one end of the capacitor C1 is connected between the first switch switch1 and the gate of the twelfth MOS tube M10, and the other end is connected to the power supply end.

6. The high-speed current detection circuit according to claim 5, characterized in that: The high-speed current detection circuit also includes a detection current output terminal; the current detection module also includes a current detection output unit, and the current detection output unit includes a first amplifier OP2, a second amplifier OP3, a third amplifier OP1 and a second resistor R1; wherein, The positive phase input terminal of the first amplifier OP2 is connected to the reference voltage, the negative phase input terminal of the first amplifier OP2 is connected to the negative phase input terminal of the second amplifier OP3, the output terminal of the first amplifier OP2 is short-circuited with its negative phase input terminal and connected to the drain of the twelfth MOS tube M10 through the second resistor; the positive phase input terminal of the second amplifier OP3 is connected to the negative phase input terminal of the third amplifier OP1, the negative phase input terminal of the second amplifier OP3 is connected to the output terminal of the first amplifier OP2, and the output terminal of the second amplifier OP3 is used to output the zero current clock detection signal ZC; the positive phase input terminal of the third amplifier OP1 is connected between the drain of the twelfth MOS tube M10 and the second resistor, the negative phase input terminal of the third amplifier OP1 is short-circuited with the output terminal, and the output terminal of the third amplifier OP1 is connected to the detection current output terminal.

7. The high-speed current detection circuit according to claim 4, characterized in that: The copy module further includes a second switch switch2, one end of which is connected to the drain of the third MOS tube M13, and the other end of which is connected to the source of the tenth MOS tube M8 and the drain of the ninth MOS tube M7.

8. The high-speed current detection circuit according to claim 3, characterized in that: The detection unit further includes an inverter LSGATE and a thirteenth MOS tube M15, wherein: The input end of the inverter LSGATE is connected to the gate of the power switch tube M1 to be tested; the gate of the thirteenth MOS tube M15 is connected to the output end of the inverter LSGATE, the drain is connected to the source of the seventh MOS tube M5, and the source is connected to the drain of the fourth MOS tube M2.

9. The high-speed current detection circuit according to claim 5, characterized in that: It also includes a first current source Ib1, one end of the first current source Ib1 is connected to the power supply end, and the other end is connected to the non-inverting input end of the error amplifier Error Amp; and / or The second current source Ib2 is also included. One end of the second current source Ib2 is connected to the drain of the twelfth MOS transistor M10, and the other end is grounded.

10. A power supply circuit, characterized in that: The invention comprises a high-speed current detection circuit as described in any one of claims 1 to 9.

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