FPGA-based chip automatic test design method and device

Abstract

The embodiment of the invention relates to the technical field of chip testing, and particularly discloses an automatic chip testing design method and device based on an FPGA (Field Programmable Gate Array). According to the embodiment of the invention, manual operation can be reduced, the test accuracy and reliability are improved, the test program can quickly adjust variables such as data format, data bit width, clock frequency and the like according to different test requirements through the programmable characteristic of the FPGA, the flexibility of the test system is enhanced, the stability can be well maintained, the test system is not easily influenced by external factors, and the test efficiency is improved. Key parameters such as a clock have high stability, and the device is small in size and can be conveniently placed in environments such as high and low temperature, humidity, aging and vibration for testing, so that the feasibility and efficiency of the environment test are greatly improved; by adding delay time information and test vector repetition point compression storage in a data format, the expenditure of memory resources and the expenditure of vector read-write time in a chip test process are greatly reduced; and the method also has rich expandability.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular relates to a chip automatic testing design method and device based on FPGA. Background Art

[0002] The chip test modes usually include scan, bist, analog and IO (input / output) test modes. Different test modes correspond to different test purposes. The current chip test platform is generally based on ATE (automatic test equipment). After configuring the test mode for the specific chip test IO pin, the test stimulus is applied to the chip IO, and the value given by the chip IO is read and compared with the correct value to give a conclusion on whether the chip is normal.

[0003] However, since ATE test equipment is relatively expensive, it is difficult for ordinary laboratories to have similar test equipment and environment, and it is difficult to make quick adjustments according to different chip types and test requirements. It lacks flexibility and is difficult to test under special environmental conditions, which limits the scope and depth of environmental testing. It is difficult to flexibly deploy between different locations or laboratories, affecting the flexibility and convenience of testing. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a chip automatic test design method and device based on FPGA, aiming to solve the problems raised in the background technology.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions: A chip automatic test design method based on FPGA, the method specifically comprises the following steps: When the asynchronous FIFO1 is not full, a FLASH data read request is initiated and a FLASH read operation is performed; The data returned by SPI control is control register data and test vector data, which are written into internal registers and asynchronous FIFO1; When asynchronous FIFO1 is not empty, the data in asynchronous FIFO1 is read out; Write the data read from asynchronous FIFO1 into the DDR control module; When asynchronous FIFO2 is not full, data is read from DDR control and written into asynchronous FIFO2; When the asynchronous FIFO2 is not empty, the data in the asynchronous FIFO2 is read out; The data read out from asynchronous FIFO2 is output according to the correspondence between the data bit and the GPIO signal.

[0006] As a further limitation of the technical solution of the embodiment of the present invention, when the asynchronous FIFO1 is not full, initiating a FLASH data read request and executing the FLASH read operation specifically include the following steps: When asynchronous FIFO1 is not full, a FLASH data read request is initiated; According to the FLASH data read request, execute the FLASH read operation; After all the data in FLASH are read, stop, reset the FPGA logic, and execute the FLASH read operation again.

[0007] As a further limitation of the technical solution of the embodiment of the present invention, the data returned by the SPI control is control register data and test vector data, and writing into the internal register and asynchronous FIFO1 specifically includes the following steps: The first N values ​​of the data returned by SPI control are control register data, and the following data are test vector data; Write control register data directly into internal registers; Write the test vector data directly into asynchronous FIFO1.

[0008] As a further limitation of the technical solution of the embodiment of the present invention, when the asynchronous FIFO1 is not empty, the data in the asynchronous FIFO1 is read out: after all the data of the first test vector are read, a delay of a period of time is configured through the control register to take effect, and then the data of the second test vector is read, and after all the data of the test vectors are read, a delay of a period of time is configured through the control register to take effect, and the whole cycle is read again.

[0009] As a further limitation of the technical solution of the embodiment of the present invention, the data stored in the FLASH includes control data and test data, wherein: the control data includes the length of each test vector, with N bits as 1 unit length; the time interval between test vectors, with the unit being the clk1 clock cycle; the time interval from when all test vectors run once to switching to the next cycle, with the unit being the clk1 clock cycle.

[0010] As a further limitation of the technical solution of the embodiment of the present invention, after the FPGA logic is reset, the state machine switches from the FLASH idle state to the FLASH four-line enabled state. In the FLASH four-line enabled state, the FPGA logic configures the FLASH from the standard SPI mode to the QUAD SPI mode to speed up the reading of SPI data; when the four-line enable configuration success signal is sampled and pulled high, indicating that the SPI interface is switched successfully, the state machine switches to the FLASH read data state to read all the data stored in the FLASH. After each successful data read, the read address is incremented, and the read data is placed in the control register or stored in the asynchronous FIFO1 according to the address. When all address data are read, the read data end signal is pulled high, the state machine switches to the FLASH read end state, and the FLASH state machine stops working.

[0011] As a further limitation of the technical solution of the embodiment of the present invention, when the asynchronous FIFO1 is not empty, it enters the DDR write address state, generates the corresponding AXI write address signal and write address, if the write address signal is successfully handshaked on the AXI bus, then enters the DDR write data state, the control logic generates the corresponding AXI write data signal and write data according to the control information, if the AXI bus write data signal handshake is successful, then enters the DDR write response state, detects the response channel of the write operation on the AXI bus, if it is detected that the write response handshake is successful, and the write address has not jumped to the end address, it indicates that there is subsequent data to be written to the DDR, the state machine continues to jump to the DDR write preparation state, if the write address has jumped to the end address at this time, then all the data has been written to the DDR, the state machine then jumps to the DDR write end state, and ends the process of writing data to the DDR.

[0012] As a further limitation of the technical solution of the embodiment of the present invention, when the asynchronous FIFO2 is not full, it enters the DDR read data state, generates the corresponding AXI read address signal and read address, if the read address signal is successfully handshaked on the AXI bus, then jumps to the DDR read wait state, waiting for the DDR control to return the data of the corresponding address, when the AXI bus read data signal handshake is successful, it indicates that the read data is returned successfully, then jumps to the DDR read data state, receives the returned data, and writes the received data into the asynchronous FIFO2 for receiving data, then jumps to the DDR read ready state again, the address is incremented according to the control logic, and the data in the next address is read.

[0013] As a further limitation of the technical solution of the embodiment of the present invention, when the asynchronous FIFO2 is not empty, data starts to be sent and enters the PAD sending state. If a repeated point is encountered, the PAD repeated sending state is entered, and the test points therein are repeatedly sent a certain number of times. At this time, the asynchronous FIFO2 is not read; in the PAD sending state, the data length of a single vector is used to determine whether the sending of all repeated points of a single vector is completed. If the sending is completed, the PAD sending switching state is entered; in the PAD sending state, the data length of all vectors is used to determine whether the sending of all test points is completed. If the sending is completed, the PAD sending end state is entered; if the sending of the next test vector is started in the PAD sending switching state, a delay is added, and the delay time is determined by the control register value in the storage space, and then the PAD sending preparation state is entered; in the PAD sending end state, if a new cycle is started to continue sending the test vector, a delay is added, and the delay time is determined by the control register in the storage space, and then the PAD sending preparation state is entered, and the sending is started from the first vector cycle, and data is read again at the first address of the DDR.

[0014] An FPGA-based chip automatic test design device is used to execute the FPGA-based chip automatic test design method as described above, the device includes a clock reset generation module, an SPI control module, a DDR control module and a main control module, wherein: A clock reset generation module is used to generate a clk1 clock and a corresponding reset signal, and to generate a clk2 clock and a reset signal; The SPI control module is used to receive the initialization and data reading commands sent by the main control module, convert them into SPI interface timing and send them to the FLASH device, receive the data returned by the FLASH device, and send them to the main control module; The DDR control module is used to receive the data read and write commands issued by the main control module, receive the data returned by the DDR device, and send it to the main control module, and output the clock clk_DDR of the AXI interface for use by the logic in the main control module; The main control module is used to provide FLASH and DDR control read and write control logic, perform data caching, data cross-clock transmission and final GPIO output control.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The embodiments of the present invention can reduce manual operations, improve the accuracy and reliability of the test, and through the programmable characteristics of FPGA, the test program can quickly adjust variables such as data format, data bit width, clock frequency, etc. according to different test requirements, thereby enhancing the flexibility of the test system, being able to maintain stability well and not being easily affected by external factors, so that key parameters such as the clock have high stability, and the device is small in size, which is convenient for placement in high and low temperature, humidity, aging, vibration and other environmental tests, greatly improving the feasibility and efficiency of environmental tests; by adding delay time information and test vector repeat point compression storage in the data format, the overhead of memory resources and the read and write time overhead of vectors during chip testing are greatly reduced; and the device also has rich scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention.

[0017] Figure 1 A schematic diagram showing the principle of the method provided by an embodiment of the present invention is shown.

[0018] Figure 2 A schematic diagram showing control data and test data in the method provided by an embodiment of the present invention is shown.

[0019] Figure 3 A schematic diagram showing the switching of the reset state in the method provided by an embodiment of the present invention is shown.

[0020] Figure 4 A schematic diagram of a DDR write address in a method provided by an embodiment of the present invention is shown.

[0021] Figure 5 A schematic diagram showing PAD state switching in the method provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0023] It is understandable that in the prior art, since ATE test machine experimental equipment is relatively expensive, it is difficult for ordinary laboratories to have similar test equipment and environment, and it is difficult to make rapid adjustments according to different chip types and test requirements. It lacks flexibility and is difficult to test under special environmental conditions. This limits the scope and depth of environmental testing and makes it difficult to flexibly deploy between different locations or laboratories, affecting the flexibility and convenience of testing.

[0024] To solve the above problems, in an embodiment of the present invention, when asynchronous FIFO1 is not full, a FLASH data read request is initiated and a FLASH read operation is performed; the data returned by the SPI control is the control register data and the test vector data, and is written into the internal register and the asynchronous FIFO1; when the asynchronous FIFO1 is not empty, the data in the asynchronous FIFO1 is read out; the data read out of the asynchronous FIFO1 is written into the DDR control module; when the asynchronous FIFO2 is not full, the data is read from the DDR control and written into the asynchronous FIFO2; when the asynchronous FIFO2 is not empty, the data in the asynchronous FIFO2 is read out; the data read out of the asynchronous FIFO2 is output according to the correspondence between the data bit and the GPIO signal. It can reduce manual operations and improve the accuracy and reliability of the test. Through the programmable characteristics of FPGA, the test program can quickly adjust variables such as data format, data bit width, clock frequency, etc. according to different test requirements, which enhances the flexibility of the test system. It can maintain stability well and is not easily affected by external factors, so that key parameters such as the clock have high stability. The device is small in size and is easy to place in high and low temperature, humidity, aging, vibration and other environmental tests, which greatly improves the feasibility and efficiency of environmental testing. By adding delay time information and test vector repeat point compression storage in the data format, the overhead of memory resources and the read and write time overhead of vectors during chip testing are greatly reduced. It also has rich scalability.

[0025] Figure 1 A schematic diagram showing the principle of the method provided by an embodiment of the present invention is shown.

[0026] Specifically, a chip automatic test design method based on FPGA, the method specifically includes the following steps: Step 1: When the asynchronous FIFO1 is not full, a FLASH data read request is initiated to perform a FLASH read operation.

[0027] In the embodiment of the present invention, when the asynchronous FIFO1 is not full, a FLASH data read request is initiated. At this time, according to the FLASH data read request, a FLASH read operation is performed until all the data in the FLASH are read and then stopped. After the FPGA logic is reset again, the FLASH read operation is performed again. Figure 2 A schematic diagram of control data and test data in the method provided by an embodiment of the present invention is shown, and the data stored in FLASH includes control data and test data: the control data includes the length of each test vector, with Nbit as 1 unit length; the time interval between test vectors, with the unit being the clk1 clock cycle; the time interval from when all test vectors run once to switching to the next cycle, with the unit being the clk1 clock cycle.

[0028] It is understandable that if Figure 3 A schematic diagram of the reset state switching in the method provided by an embodiment of the present invention is shown. After the FPGA logic is reset again, the state machine switches from the FLASH idle state to the FLASH four-line enabled state. In the FLASH four-line enabled state, the FPGA logic configures the FLASH from the standard SPI mode to the QUAD SPI mode to speed up the reading of SPI data. When the four-line enable configuration success signal is sampled to be pulled high, indicating that the SPI interface is switched successfully, the state machine switches to the FLASH read data state to read all the data stored in the FLASH. After each successful data read, the read address is incremented, and the read data is placed in the control register or stored in the asynchronous FIFO1 according to the address distinction. When all address data are read, the read data end signal is pulled high, the state machine switches to the FLASH read end state, and the FLASH state machine stops working.

[0029] Step 2: The data returned by the SPI control is the control register data and the test vector data, and is written into the internal register and the asynchronous FIFO1.

[0030] In the embodiment of the present invention, the first N values ​​of the data returned by the SPI control are control register data, and the following data are test vector data. The control register data is directly written into the internal register, and the test vector data is directly written into the asynchronous FIFO1.

[0031] Step 3: When the asynchronous FIFO1 is not empty, the data in the asynchronous FIFO1 is read out.

[0032] In the embodiment of the present invention, when the asynchronous FIFO1 is not empty, the data in the asynchronous FIFO1 is read out. After all the data of the first test vector is read, a delay is set to take effect for a period of time through the control register, and then the data of the second test vector is read. After all the data of the test vector is read, a delay is set to take effect for a period of time through the control register, and the whole cycle is read again. Specifically, Figure 4A schematic diagram of a DDR write address in a method provided by an embodiment of the present invention is shown. When asynchronous FIFO1 is not empty, the DDR write address state is entered, and a corresponding AXI write address signal and a write address are generated. If the write address signal is successfully handshaked on the AXI bus, the DDR write data state is then entered, and the control logic generates a corresponding AXI write data signal and write data according to the control information. If the AXI bus write data signal is successfully handshaked, the DDR write response state is then entered to detect the response channel of the write operation on the AXI bus. If it is detected that the write response handshake is successful and the write address has not jumped to the end address, it indicates that there is subsequent data to be written to the DDR, and the state machine continues to jump to the DDR write preparation state. If the write address has jumped to the end address at this time, all the data has been written to the DDR at this time, and the state machine then jumps to the DDR write end state to end the process of writing data to the DDR.

[0033] Step 4: Write the data read out from the asynchronous FIFO1 into the DDR control module.

[0034] Step 5: When the asynchronous FIFO2 is not full, read data from the DDR control and write it into the asynchronous FIFO2.

[0035] In an embodiment of the present invention, when the asynchronous FIFO2 is not full, it enters the DDR read data state, generates a corresponding AXI read address signal and a read address, and if the read address signal is successfully handshaked on the AXI bus, then jumps to the DDR read wait state, waiting for the DDR control to return the data of the corresponding address. When the AXI bus read data signal handshake is successful, it indicates that the read data is returned successfully, then jumps to the DDR read data state, receives the returned data, and writes the received data into the asynchronous FIFO2 for receiving data, then jumps to the DDR read ready state again, the address is incremented according to the control logic, and the data in the next address is read.

[0036] It is understandable that for the read side of DDR, the state machine is always in a loop, reading from address 0 to the maximum address used, and then starting from address 0 in the next loop.

[0037] Step 6: When the asynchronous FIFO2 is not empty, the data in the asynchronous FIFO2 is read out.

[0038] In the embodiment of the present invention, Figure 5The schematic diagram of PAD state switching in the method provided by an embodiment of the present invention is shown. When asynchronous FIFO2 is not empty, data starts to be sent and enters the PAD sending state. If a repeated point is encountered, the PAD repeated sending state is entered, and the test points therein are repeatedly sent a certain number of times. At this time, the asynchronous FIFO2 is not read; in the PAD sending state, the data length of a single vector is used to determine whether the sending of all repeated points of a single vector is completed. If the sending is completed, the PAD sending switching state is entered; in the PAD sending state, the data length of all vectors is used to determine whether the sending of all test points is completed. If the sending is completed, the PAD sending end state is entered; if the sending of the next test vector is started in the PAD sending switching state, a delay is added, and the delay time is determined by the control register value in the storage space, and then the PAD sending preparation state is entered; in the PAD sending end state, if a new cycle is started to continue sending the test vector, a delay is added, and the delay time is determined by the control register in the storage space, and then the PAD sending preparation state is entered, and the sending from the first vector cycle is started, and data is read again at the first address of the DDR.

[0039] Step 7: Output the data read out from asynchronous FIFO2 according to the corresponding relationship between the data bit and the GPIO signal.

[0040] Further, in another preferred embodiment of the present invention, a chip automatic test design device based on FPGA includes a clock reset generation module, an SPI control module, a DDR control module and a main control module, wherein: A clock reset generation module is used to generate a clk1 clock and a corresponding reset signal, and to generate a clk2 clock and a reset signal; The SPI control module is used to receive the initialization and data reading commands sent by the main control module, convert them into SPI interface timing and send them to the FLASH device, receive the data returned by the FLASH device, and send them to the main control module; The DDR control module is used to receive the data read and write commands issued by the main control module, receive the data returned by the DDR device, and send it to the main control module, and output the clock clk_DDR of the AXI interface for use by the logic in the main control module; The main control module is used to provide FLASH and DDR control read and write control logic, perform data caching, data cross-clock transmission and final GPIO output control.

[0041] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A chip automatic test design method based on FPGA, characterized in that: The method specifically comprises the following steps: When the asynchronous FIFO1 is not full, a FLASH data read request is initiated and a FLASH read operation is performed; The data returned by SPI control is control register data and test vector data, which are written into internal registers and asynchronous FIFO1; When asynchronous FIFO1 is not empty, the data in asynchronous FIFO1 is read out; Write the data read from asynchronous FIFO1 into the DDR control module; When asynchronous FIFO2 is not full, data is read from DDR control and written into asynchronous FIFO2; When the asynchronous FIFO2 is not empty, the data in the asynchronous FIFO2 is read out; The data read out from asynchronous FIFO2 is output according to the correspondence between the data bit and the GPIO signal.

2. The FPGA-based chip automatic test design method according to claim 1, characterized in that: When the asynchronous FIFO1 is not full, a FLASH data read request is initiated, and the FLASH read operation is performed, which specifically includes the following steps: When asynchronous FIFO1 is not full, a FLASH data read request is initiated; According to the FLASH data read request, execute the FLASH read operation; After all the data in FLASH are read, stop, reset the FPGA logic, and execute the FLASH read operation again.

3. The FPGA-based chip automatic test design method according to claim 1, characterized in that: The data returned by the SPI control is control register data and test vector data, and is written into the internal register and asynchronous FIFO1, specifically including the following steps: The first N values ​​of the data returned by SPI control are control register data, and the following data are test vector data; Write control register data directly into internal registers; Write the test vector data directly into asynchronous FIFO1.

4. The FPGA-based chip automatic test design method according to claim 1, characterized in that: When the asynchronous FIFO1 is not empty, the data in the asynchronous FIFO1 is read out: after all the data of the first test vector is read, a delay of a period of time is configured through the control register to take effect, and then the data of the second test vector is read. After all the data of the test vectors are read, a delay of a period of time is configured through the control register to take effect, and the whole cycle is read again.

5. The FPGA-based chip automatic test design method according to claim 2, characterized in that: The data stored in the FLASH includes control data and test data, wherein: the control data includes the length of each test vector, with N bits as 1 unit length; the time interval between test vectors, with the unit being the clk1 clock cycle; the time interval for all test vectors to run once and switch to the next cycle, with the unit being the clk1 clock cycle.

6. The FPGA-based chip automatic test design method according to claim 2, characterized in that: After the FPGA logic is reset, the state machine switches from the FLASH idle state to the FLASH four-line enabled state. In the FLASH four-line enabled state, the FPGA logic configures the FLASH from the standard SPI mode to the QUAD SPI mode to speed up the reading of SPI data; when the four-line enable configuration success signal is sampled and pulled high, it indicates that the SPI interface has been switched successfully, and the state machine switches to the FLASH read data state to read all the data stored in the FLASH. After each successful data read, the read address is incremented, and the read data is placed in the control register or stored in the asynchronous FIFO1 according to the address. When all address data are read, the read data end signal is pulled high, the state machine switches to the FLASH read end state, and the FLASH state machine stops working.

7. The FPGA-based chip automatic test design method according to claim 1, characterized in that: When the asynchronous FIFO1 is not empty, it enters the DDR write address state, generates the corresponding AXI write address signal and write address, if the write address signal is successfully handshaked on the AXI bus, then enters the DDR write data state, the control logic generates the corresponding AXI write data signal and write data according to the control information, if the AXI bus write data signal handshake is successful, then enters the DDR write response state, detects the response channel of the write operation on the AXI bus, if it is detected that the write response handshake is successful, and the write address has not jumped to the end address, it indicates that there is subsequent data to be written to the DDR, the state machine continues to jump to the DDR write preparation state, if the write address has jumped to the end address at this time, then all the data has been written to the DDR, the state machine then jumps to the DDR write end state, and ends the process of writing data to the DDR.

8. The FPGA-based chip automatic test design method according to claim 1, characterized in that: When the asynchronous FIFO2 is not full, it enters the DDR read data state, generates the corresponding AXI read address signal and read address, and if the read address signal is successfully handshaked on the AXI bus, then jumps to the DDR read wait state, waiting for the DDR control to return the data of the corresponding address. When the AXI bus read data signal handshake is successful, it indicates that the read data is returned successfully, then jumps to the DDR read data state, receives the returned data, and writes the received data into the asynchronous FIFO2 for receiving data, then jumps to the DDR read ready state again, the address is incremented according to the control logic, and the data in the next address is read.

9. The FPGA-based chip automatic test design method according to claim 1, characterized in that: When the asynchronous FIFO2 is not empty, it starts to send data and enters the PAD sending state. If a repeated point is encountered, it enters the PAD repeated sending state and repeats the sending of the test points therein for a certain number of times. At this time, the asynchronous FIFO2 is not read; in the PAD sending state, the data length of a single vector is used to determine whether the sending of all repeated points of a single vector is completed. If the sending is completed, the PAD sending switching state is entered; in the PAD sending state, the data length of all vectors is used to determine whether the sending of all test points is completed. If the sending is completed, the PAD sending end state is entered; if the sending of the next test vector is started in the PAD sending switching state, a delay is added, and the delay time is determined by the control register value in the storage space, and then the PAD sending preparation state is entered; in the PAD sending end state, if a new cycle is started to continue sending the test vector, a delay is added, and the delay time is determined by the control register in the storage space, and then the PAD sending preparation state is entered, and the sending is started from the first vector cycle, and data is read again at the first address of the DDR.

10. An FPGA-based chip automatic test design device, used to execute the FPGA-based chip automatic test design method as claimed in any one of claims 1 to 9, characterized in that: The device comprises a clock reset generation module, an SPI control module, a DDR control module and a main control module, wherein: A clock reset generation module is used to generate a clk1 clock and a corresponding reset signal, and to generate a clk2 clock and a reset signal; The SPI control module is used to receive the initialization and data reading commands sent by the main control module, convert them into SPI interface timing and send them to the FLASH device, receive the data returned by the FLASH device, and send them to the main control module; The DDR control module is used to receive the data read and write commands issued by the main control module, receive the data returned by the DDR device, and send it to the main control module, and output the clock clk_DDR of the AXI interface for use by the logic in the main control module; The main control module is used to provide FLASH and DDR control read and write control logic, perform data caching, data cross-clock transmission and final GPIO output control.

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