System and method for testing electrical connection between chip and external circuitry

Abstract

Systems and methods for testing electrical connections between a chip and external circuitry are discussed. In some embodiments, a chip may include an input / output (I / O) terminal and a test circuit coupled to the I / O terminal, where an oscillation of the test circuit varies in response to a change in impedance at the I / O terminal that is caused by a connection fault or degradation.

Description

Technical Field

[0001] The present disclosure relates generally to electronic circuits, and more particularly to systems and methods for testing electrical connections between a chip and external circuitry. Background Art

[0002] An integrated circuit (IC) is a group of electronic circuits fabricated on a piece of semiconductor material (e.g., silicon). With the advent of modern semiconductor manufacturing technology, increasingly miniaturized transistors and other IC components can now be integrated into a single electronic package, chip, or microchip. For example, a modern system on a chip (SoC) can include most (or all) of the components of an entire computer or data processing system.

[0003] In order to communicate with external devices, the chip may have numerous electrical connections. Examples of such connections are solder joints.

[0004] The inventors of the present invention have recognized that the increasing number of electrical connections required for operation of complex chips raises reliability issues since any such connection may fail due to manufacturing defects, shock, stress, fatigue, and the like. Summary of the invention

[0005] Various systems and methods for testing electrical connections between a chip and external circuitry are presented. In an illustrative, non-limiting embodiment, a chip may include an input / output (I / O) terminal and a test circuit coupled to the I / O terminal, wherein an oscillation frequency of the test circuit changes in response to an impedance change at the I / O terminal caused by a connection failure or degradation.

[0006] In some embodiments, the chip may include an RF transceiver coupled to an I / O terminal. The IC may be fabricated on a die encapsulated by a package, and the I / O terminal may be external to the package. The I / O terminal may be coupled to a device disposed external to the chip. The device may include an antenna. Additionally or alternatively, the device may include another chip.

[0007] The resonant frequency of the test circuit may be selected based at least in part on the impedance at the I / O terminal in the absence of a connection failure or degradation. For example, a connection failure or degradation may include a break or fracture of a solder joint.

[0008] The test circuit may include a relaxation oscillator. The relaxation oscillator may include a Schmitt trigger and a feedback resistor. The chip may include a counter coupled to an output of the Schmitt trigger, wherein the counter is configured to store a value indicating an oscillation frequency of the test circuit.

[0009] The chip may include a comparator coupled to the counter and to a register configured to store a threshold below which an increase in the oscillation frequency indicates a connection failure or degradation.

[0010] In the absence of connection failure or degradation, the relaxation oscillator does not oscillate when the antenna coupled to the I / O terminal presents a DC short circuit between the S pad and the G pad. In addition, in the absence of connection failure or degradation, the oscillation frequency is less than the operating frequency of the main application of the chip.

[0011] In another illustrative non-limiting embodiment, the test circuit can be a Schmitt trigger and a feedback resistor coupled across an input and an output of the Schmitt trigger, wherein the input of the Schmitt trigger is coupled to an electrical pad of the chip, and wherein the test circuit is configured to oscillate at a frequency indicative of the integrity of a connection between the chip and an external device coupled to the electrical pad.

[0012] The test circuit may have a resonant frequency selected based at least in part on an impedance at the I / O terminal in the absence of a failure or degradation of the solder joint at the electrical pad. In response to the connection being complete, the test circuit may not oscillate when the antenna coupled to the I / O terminal appears as a DC short between the S pad and the G pad.

[0013] In yet another illustrative, non-limiting embodiment, a method may include monitoring an oscillation frequency of a test circuit coupled to a connection between a chip and an antenna; and in response to a change in the oscillation frequency being greater than a threshold, identifying a failure or degradation of a solder joint at the connection.

[0014] The oscillation frequency may change in response to changes in parasitic capacitance, and an increase in the oscillation frequency may indicate a decrease in connection integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present invention is illustrated by way of example and is not limited by the accompanying drawings, in which like reference numerals indicate like elements. Elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale.

[0016] Figure 1 is a diagram of an example of a system for testing electrical connections between a chip and an external circuit or device according to some embodiments.

[0017] Figure 2A is a circuit diagram of an example of a first external circuit or device according to some embodiments.

[0018] Figure 2B is a circuit diagram of an example of a second external circuit or device according to some embodiments.

[0019] Figure 3 is a flow chart of an example of a method for testing electrical connections between a chip and an external circuit according to some embodiments. DETAILED DESCRIPTION

[0020] Systems and methods for testing electrical connections are described. In various embodiments, the test circuitry may be configured to monitor the integrity of a connection between a chip and an external circuit or device (eg, an antenna, another chip, etc.).

[0021] Typically, in addition to the on-chip shunt capacitor configured to provide electrostatic discharge (ESD) protection, the external circuit presents an additional shunt impedance to the output of the chip. In some embodiments, the test circuit may include an RC oscillator connected to the ESD protection circuit and the on-chip wiring of the chip. In the event of a connection failure, the electrical path toward the additional shunt impedance is at least partially disconnected, resulting in a change in the oscillation frequency of the RC oscillator.

[0022] The test circuit can be used in situations where the external circuit appears to be (i) a DC open circuit or (ii) a DC short circuit (to the chip).

[0023] For example, if the shunt impedance presented by the external circuit behaves as capacitive (as a DC open circuit), the test circuit can be configured to oscillate at the selected test frequency when the connection is adequate, complete, suitable, functional, or operational, such that a failure or degradation in the integrity of the connection will produce a greater oscillation frequency. Conversely, if the shunt impedance presented by the external circuit behaves as a DC short circuit, an oscillation frequency of 0 Hz will indicate that the connection is adequate, and a deviation from 0 Hz

[0024] In the case of a proper chip connection, the low frequency impedance at the chip pin is different than in the case of a connection failure. This allows relatively low frequency testing of pin connections that interface with high frequency loads (such as millimeter wave (mmWave) antennas or transmitters). In addition, the use of low frequency testing reduces complexity compared to high frequency test methods.

[0025] Therefore, in different applications, the systems and methods described herein can increase accuracy (reduce the probability of measurement errors), reduce the impact on high-frequency performance (because there are no components placed in the high-frequency signal path that would otherwise be necessary to implement conventional detection techniques), and reduce power consumption (low-frequency circuits generally consume less power than high-frequency circuits).

[0026] in this regard, Figure 1 2 is a diagram of an example of a system for testing electrical connections between a chip 100 and an external circuit or device 200A or 200B ( FIG. 2 ). As shown, the chip 100 includes a semiconductor die 101 encapsulated by an electronic package 102 .

[0027] For simplicity, the electronic package 102 includes a signal (S) pad, pin or terminal and two ground (G) pads, pins or terminals. However, in actual implementations, there may be dozens or hundreds of pads, pins or terminals.

[0028] In this example, the S pad is coupled to an integrated circuit (IC) 104 fabricated on semiconductor die 101 via a balun circuit 103 having a parasitic capacitance C coupled to a balun For example, if the primary application of chip 101 is a high frequency RF application (eg, automotive radar), IC 104 may include a transformer, matching network, etc. coupled to a radio frequency (RF) transceiver.

[0029] The semiconductor die 101 further includes an ESD protection circuit 105 having two diodes and a parasitic capacitor C ESD , as shown. Test circuit 106 is integrated into die 101 and coupled to a node between IC 104 and ESD protection circuit 105. In other applications, test circuit 106 may be external to die 101.

[0030] Test circuit 106 is coupled to the S pad via 103 and 104. Specifically, test circuit 106 includes a relaxation oscillator 107 coupled to counter 111. Relaxation oscillator 107 includes resistor 108 (which provides ESD protection along with 109, but is not otherwise required) at the input of Schmitt trigger 110. Feedback resistor R fb Coupled between the input and output of the Schmitt trigger 110, and as shown, a second ESD circuit 109 may also be used.

[0031] In operation, relaxation oscillator 107 is configured to operate at a test frequency (f test ) operation. In some cases, the relaxation oscillator 107 can be configured to operate in conjunction with the R fb The product of the total capacitance connected to the S pad gives a time constant that is one-to-one related to f test oscillation.

[0032] However, when there is a fault or after sufficient degradation in the connection, the oscillation frequency of the relaxation oscillator 107 increases, as indicated by a change in impedance or capacitance at the connection (eg, due to a crack in the solder joint at the S-pad, etc.).

[0033] Counter 111 increments a value indicating the number of times Schmitt trigger 110 changes its state within a selected time period after which it automatically resets, and thus stores a value indicative of the oscillation frequency of relaxation oscillator 107. Counter 111 is coupled to the inverting input of comparator 112.

[0034] Threshold register 113 is configured with a frequency threshold. When the oscillation frequency of relaxation oscillator 107 overcomes the frequency threshold, comparator 112 changes the state of error signal 114 (e.g., from "1" to "0"), thereby reporting a connection fault; which in turn can be handled by a safety circuit or process within chip 100.

[0035] Figure 2A is a circuit diagram of an example of an external circuit or device 200A. In this example, the external circuit or device 200A includes an antenna 201A, which is coupled to the S pad and the G pad of the package 102 via a 1 / 4 wave stub 202A; therefore, it behaves as a DC short circuit. When the solder ball breaks at the S pad, the S pad is no longer shorted to the G pad, resulting in a non-zero f test In the case of a solder ball break, when the value of the counter 111 exceeds the value of the threshold register 117, the comparator 212 reports a connection failure.

[0036] Figure 2B 2 is a circuit diagram of an example of an external circuit or device 200B. In this embodiment, the external circuit or device 200B includes an S pad coupled to the package 102 and a parasitic capacitor C ant antenna 201B; therefore, it behaves as a DC open circuit. In the case of a broken solder ball joint, the capacitive load changes, resulting in f test In the case of a solder ball break, when the value of the counter 111 exceeds the value of the threshold register 117, the comparator 212 reports a connection failure.

[0037] If there is a proper connection between the chip 100 and the antenna 200A, the S pad is shorted to the G pad, which is electrically connected to the ground (GND) on the chip 100. Therefore, the voltage across the ESD diode 105 does not change, causing the relaxation oscillator 107 to not oscillate (f test =0 Hz), so that the value of the counter 111 does not increase.

[0038] On the contrary, if the connection is faulty, the relaxation oscillator 107 is switched to the state of fb The first oscillation operation at a frequency determined by the total capacitance connected to its input causes the counter 111 to register a non-zero value. Thus, in the event of a solder ball break, when the value of the counter 111 exceeds the value of the threshold register 117, the comparator 112 reports a connection fault.

[0039] As the inventors of the present invention have determined, the difference introduced by a solder ball fracture fault is sufficient to make a reliable determination of a connection fault. Specifically, a typical setting can produce a difference of at least two times the capacitive loading of the relaxation oscillator 107. The oscillation frequency of the relaxation oscillator 107 is related one-to-one to its capacitive loading, so the difference in oscillation frequency also becomes at least two times larger, which makes it detectable without false positives or false negatives.

[0040] It is also worth noting that the amount of capacitance in a broken solder ball joint is less than the capacitance added by the off-chip external circuitry 200A / B. For example, if the solder ball is 350 μm in diameter, and we model the "broken solder ball" as a 5 μm air gap (i.e., crack), then the difference in capacitive loading is approximately 170 fF, which is much less than the minimum expected off-chip capacitance (>1 pF).

[0041] Figure 3 is a flow chart of an example of a method 300 for testing electrical connections between a chip and an external circuit. In various embodiments, the method 300 may be at least partially performed by the chip 100 when coupled to (or when expected to be coupled to) the external circuit 200A / B.

[0042] The method 300 starts at 301. At 302, the method 300 monitors the oscillation frequency of the test circuit 106 coupled to the S pad (e.g., via a solder joint) at the connection between the chip 100 and the external circuit 200A / B. For example, the counter 111 can store the number of times the Schmitt trigger 110 switches its output level within a certain time window, which indicates the oscillation frequency of the relaxation oscillator 107 that exists at that time.

[0043] At 303, method 300 determines whether the change in oscillation frequency is greater than a threshold value stored in register 117 (eg, within the same window duration) via operation of comparator 118. If not, at 303, control returns to 302 so that monitoring can continue while chip 100 is powered on.

[0044] Otherwise, at 304 , the output of comparator 118 indicates an error that indicates a fault, defect, error, or degradation of the solder joint at the connection between chip 100 and external circuit 200A / B. As shown, method 300 ends at 305 .

[0045] In some embodiments, method 300 may be performed on multiple pins, pads, or terminals on package 102 during operation of chip 100 and / or as part of a test procedure or event. Each time a fault is detected, method 300 may also identify which pin, pad, or terminal is defective based on which of the multiple test circuits indicates that the pin, pad, or terminal is defective. Alternatively, when a single test circuit is shared across multiple pins, pads, or terminals, the state of the multiplexer between the test circuit and the pin, pad, or terminal may indicate which pin, pad, or terminal is defective.

[0046] In many embodiments, the systems and methods described herein can be incorporated into a wide variety of electronic devices, including, for example: computer systems or information technology (IT) products, such as servers, desktops, laptops, storage, switches, routers, etc.; telecommunications hardware; consumer devices or appliances, such as mobile phones, tablets, wearable devices, Internet of Things (IoT) devices, televisions, cameras, audio systems, etc.; scientific instruments; industrial robots; medical or laboratory electronic equipment, such as imaging, diagnostic or therapeutic equipment, etc.; transportation vehicles, such as cars, buses, trucks, trains, boats, airplanes, etc.; military equipment, etc. More generally, these systems and methods can be incorporated into any device or system having one or more electronic components or assemblies.

[0047] For the sake of brevity, conventional techniques are not described in detail herein. In addition, the connecting lines shown in the various figures contained herein are intended to illustrate the relationship (e.g., logical relationship) or physical coupling (e.g., electrical coupling) between the various elements. However, it should be noted that alternative relationships and connections can be used in other embodiments. In addition, the circuit system described herein can be implemented with silicon or another semiconductor material, or alternatively, it can be implemented by its software code representation.

[0048] Although the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. It is not intended that any benefit, advantage, or solution to a problem described herein with respect to a specific embodiment be construed as a key, required, or essential feature or element of any or all claims.

[0049] Reference is made herein to "configuring" a device or a device being "configured to" perform some operation. It should be understood that this may include selecting predefined logic blocks and logically associating them. It may also include programming computer software-based logic that modifies the control device, wiring discrete hardware components, or a combination thereof. The device so configured is physically designed to perform the specified operation.

[0050] Unless otherwise specified, terms such as "first" and "second" are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the time ordering or other priority ordering of such elements. The term "coupled" or "operably coupled" is defined as connected, but not necessarily directly connected, nor necessarily mechanically connected. Unless otherwise specified, the term "one / an / a kind of" is defined as one (kind) or more (kinds). The term "comprise" (and any form of including, such as "comprises" and "comprising"), "have" (and any form of having, such as "has" and "having"), "include" (and any form of including, such as "includes" and "including") and "contain" (and any form of containing, such as "contains" and "containing") are open linking verbs. Therefore, a system, device or equipment that "includes", "has", "includes" or "contains" one or more elements has the one or more elements, but is not limited to having only the one or more elements. Similarly, a method or process that “comprises,” “has,” “includes,” or “contains” one or more operations possesses the one or more operations, but is not limited to possessing only the one or more operations.

Claims

1. A chip, characterized in that: include: Input / output I / O terminal; as well as A test circuit is coupled to the I / O terminal, wherein an oscillation frequency of the test circuit changes in response to an impedance change at the I / O terminal caused by a connection failure or degradation.

2. The chip according to claim 1, characterized in that: The resonant frequency of the test circuit is selected based at least in part on an impedance at the I / O terminal in the absence of the connection fault or degradation.

3. The chip according to claim 1, characterized in that: Additionally included is a counter coupled to an output of the Schmitt trigger, wherein the counter is configured to store a value indicative of an oscillation frequency of the test circuit.

4. The chip according to claim 3, characterized in that: Also included is a comparator coupled to the counter and to a register configured to store a threshold below which an increase in the oscillation frequency indicates a fault or degradation in the connection.

5. A test circuit, characterized in that: include: Schmitt trigger; as well as a feedback resistor coupled across an input and an output of the Schmitt trigger, wherein the input of the Schmitt trigger is coupled to an electrical pad of a chip, and wherein the test circuit is configured to oscillate at a frequency indicative of the integrity of a connection between the chip and an external device coupled to the electrical pad.

6. The test circuit according to claim 5, characterized in that: The test circuit has a resonant frequency selected based at least in part on an impedance at the I / O terminal in the absence of failure or degradation of a solder joint at the electrical pad.

7. The test circuit according to claim 5, characterized in that: In response to the connection being complete, the test circuit does not oscillate when the antenna coupled to the I / O terminal appears as a DC short between the S pad and the G pad.

8. A method, characterized in that include: monitoring an oscillation frequency of a test circuit coupled to a connection between the chip and the antenna; as well as In response to the change in the oscillation frequency being greater than a threshold, a failure or degradation of the solder joint at the connection is identified.

9. The method according to claim 8, characterized in that The oscillation frequency changes in response to changes in parasitic capacitance.

10. The method according to claim 8, characterized in that An increase in the oscillation frequency indicates a decrease in connection integrity.

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