Waveguide wafer, composite modulator and preparation method thereof

Abstract

The embodiment of the invention provides a waveguide wafer, a composite modulator and a preparation method of the composite modulator, and relates to the technical field of electro-optical modulators, and the waveguide wafer is characterized in that a SiO2 thermal oxide layer is arranged on the top surface of a silicon substrate; the first SiO2 cladding layer is arranged on the top surface of the SiO2 thermal oxide layer; the waveguide structure is arranged in the first SiO2 cladding; the metal electrode is arranged in the first SiO2 cladding and the SiO2 thermal oxide layer; the bonding interface is located on the top surface of the first SiO2 cladding above the waveguide structure, the SiO2 thickness between the bonding interface and the top surface of the waveguide structure is a preset thickness, the bonding interface is processed to have preset flatness and then is prevented from being over-etched in the process of etching the second SiO2 cladding through protection of the sacrificial layer, and the sacrificial layer is removed after etching of the second SiO2 cladding is completed; and after being etched, the second SiO2 claddings are all located in the areas, except the bonding interface, of the top surface of the first SiO2 claddings. According to the scheme, the bonding interface with controllable thickness and smooth surface can be obtained.

Description

Technical Field

[0001] The present invention relates to the technical field of electro-optical modulation devices, and in particular to a waveguide wafer, a composite modulator and a preparation method thereof. Background Art

[0002] Bonding technology can achieve a close combination of materials with different structures and functions, thereby splicing materials with different structures and functions into a whole, realizing a combination of different material properties, and producing beneficial effects. The Die to Wafer bonding method generally uses a single or batch method to bond small chips (die) with specific functions to a whole wafer (wafer). For silicon photonic chips, combining small chips with specific functions with waveguide structures to form a composite modulator has important application prospects. However, this composite modulator is very sensitive to the distance between the functional chip and the waveguide structure, that is, the distance between the bonding interface and the underlying waveguide structure has a greater impact on the optical performance of the waveguide structure. Therefore, it is necessary to strictly control the distance from the bonding interface to the waveguide structure.

[0003] In the prior art, when obtaining the target structure by bonding, the bonding layer thickness error is often large, thus affecting the efficiency of the composite modulator after bonding. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a waveguide wafer to solve the technical problem of large bonding layer thickness error in the prior art. The waveguide wafer includes:

[0005] Silicon substrate 14;

[0006] A SiO2 thermal oxide layer 13, disposed on the top surface of the silicon substrate 14;

[0007] A first SiO2 cladding layer 12 is disposed on the top surface of the SiO2 thermal oxide layer 13;

[0008] A waveguide structure 10 is arranged in the first SiO2 cladding layer 12;

[0009] A metal electrode 11 is disposed in the first SiO2 cladding layer 12 and the SiO2 thermal oxide layer 13;

[0010] A bonding interface 17, located on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10, wherein the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness, the bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to avoid being over-etched during etching of the second SiO2 cladding layer 16, and the sacrificial layer 15 is removed after etching of the second SiO2 cladding layer 16;

[0011] The second SiO 2 cladding layer 16 is located on the top surface of the first SiO 2 cladding layer 12 except for the bonding interface 17 .

[0012] The embodiment of the present invention further provides a composite modulator to solve the technical problem of large bonding layer thickness error in the prior art. The composite modulator includes:

[0013] Any of the above-mentioned waveguide wafers;

[0014] The optical modulation device 18 is bonded at the bonding interface 17 , and the optical modulation device 18 and the waveguide structure 10 below the bonding interface 17 form a composite waveguide 19 .

[0015] The embodiment of the present invention also provides a method for preparing the above-mentioned waveguide wafer to solve the technical problem of large bonding layer thickness error in the prior art. The preparation method comprises:

[0016] Preparing the SiO2 thermal oxide layer 13 on the top surface of the silicon substrate 14;

[0017] A first SiO2 cladding layer 12 is prepared on the top surface of the SiO2 thermal oxide layer 13, and the waveguide structure 10 is prepared in the first SiO2 cladding layer 12, and the metal electrode 11 is prepared in the first SiO2 cladding layer 12 and the SiO2 thermal oxide layer 13;

[0018] Processing the top surface of the first SiO2 cladding layer 12 so that the SiO2 thickness between the top surface of the first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 after the processing is a preset thickness and the top surface of the first SiO2 cladding layer 12 reaches the preset flatness;

[0019] Prepare the sacrificial layer 15 on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10;

[0020] Depositing the second SiO2 cladding layer 16 to cover the first SiO2 cladding layer 12 and the sacrificial layer 15, etching the second SiO2 cladding layer 16, and stopping the etching until the sacrificial layer 15 is completely exposed;

[0021] The sacrificial layer 15 is removed to obtain the bonding interface 17 .

[0022] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least: it is proposed that the bonding interface 17 of the waveguide wafer is located on the top surface of the first SiO2 cladding 12 above the waveguide structure 10, and the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness, and the bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to avoid being over-etched during the etching of the second SiO2 cladding 16, and the sacrificial layer 15 is removed after the etching of the second SiO2 cladding 16 is completed, so that the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 (i.e., the bonding interface layer thickness) is a preset thickness with controllable thickness , thereby reducing or avoiding the influence of the error of the bonding interface layer thickness on the efficiency of the composite modulator after bonding; in addition, when the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface of the waveguide wafer, after the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness and a preset flatness, the bonding interface 17 is protected by the sacrificial layer 15, and the sacrificial layer 15 is used as an etching stop layer to protect the bonding interface 17 from being over-etched during the etching of the second SiO2 cladding layer 16, and finally the sacrificial layer is removed by a wet etching process to obtain a bonding interface 17 with controllable thickness and flat surface, which is beneficial to improving the stability of the subsequent bonding process, as well as the stability and efficiency of the optical performance of the control device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 is a schematic diagram of a cross-sectional structure of etching the second SiO2 cladding layer 16 provided in an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of a cross-sectional structure after preparing an embedded metal electrode 11 provided in an embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of the cross-sectional structure of depositing the first SiO2 cladding layer 12 by using a cladding filling method provided by an embodiment of the present invention;

[0027] Figure 4 It is a schematic diagram of a cross-sectional structure of a first SiO2 cladding layer 12 after CMP is performed, provided by an embodiment of the present invention;

[0028] Figure 5It is a schematic diagram of a cross-sectional structure after a first SiO2 cladding layer 12 is grown by deposition, provided in an embodiment of the present invention;

[0029] Figure 6 It is a schematic diagram of a cross-sectional structure of preparing a sacrificial layer 15 provided in an embodiment of the present invention;

[0030] Figure 7 is a schematic diagram of a cross-sectional structure after depositing a second SiO2 cladding layer 16 provided in an embodiment of the present invention;

[0031] Figure 8 is a schematic diagram of a cross-sectional structure of removing a sacrificial layer 15 provided in an embodiment of the present invention;

[0032] Fig. 9 is a schematic cross-sectional structure diagram of an optical modulation device 18 bonded to a bonding interface 17 provided by an embodiment of the present invention;

[0033] Fig.10 is a schematic cross-sectional structure diagram of a method for preparing a first sacrificial layer 151 provided in an embodiment of the present invention;

[0034] Fig.11 It is a schematic diagram of a cross-sectional structure of preparing a second sacrificial layer 152 and then depositing a second SiO2 cladding layer 16 provided by an embodiment of the present invention;

[0035] Fig.12 It is a schematic diagram of a cross-sectional structure of etching the second SiO2 cladding layer 16 and the third SiO2 cladding layer 161 provided in an embodiment of the present invention;

[0036] Fig.13 is a schematic diagram of a cross-sectional structure of removing the first sacrificial layer 151 and the second sacrificial layer 152 provided by an embodiment of the present invention;

[0037] Fig.14 It is a schematic diagram of a cross-sectional structure of a modulator material bonded to a first bonding interface 171 and a second bonding interface 172 respectively, provided by an embodiment of the present invention;

[0038] Fig.15 It is a flow chart of a method for preparing a waveguide wafer provided by an embodiment of the present invention.

[0039] Reference numerals in the figures:

[0040] 10. Waveguide structure; 11. Metal electrode; 12. First SiO2 cladding; 13. SiO2 thermal oxide layer; 14. Silicon substrate; 15. Sacrificial layer; 16. Second SiO2 cladding; 17. Bonding interface; 18. Optical modulator; 19. Composite waveguide; 151. First sacrificial layer; 152. Second sacrificial layer; 161. Third SiO2 cladding; 171. First bonding interface; 172. Second bonding interface; 181. First modulator material; 182. Second modulator material. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0042] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0043] In an embodiment of the present invention, a waveguide wafer is provided, such as Figure 1 , Figure 8 As shown, the waveguide wafer includes:

[0044] Silicon substrate 14;

[0045] A SiO2 thermal oxide layer 13, disposed on the top surface of the silicon substrate 14;

[0046] A first SiO2 cladding layer 12 is disposed on the top surface of the SiO2 thermal oxide layer 13;

[0047] A waveguide structure 10 is arranged in the first SiO2 cladding layer 12;

[0048] A metal electrode 11 is disposed in the first SiO2 cladding layer 12 and the SiO2 thermal oxide layer 13;

[0049] Bonding interface 17 (eg Figure 8), the top surface of the first SiO2 cladding layer 12 located above the waveguide structure 10, wherein the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness, the bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to avoid being over-etched during etching of the second SiO2 cladding layer 16, and the sacrificial layer 15 is removed after etching of the second SiO2 cladding layer 16;

[0050] The second SiO 2 cladding layer 16 is located on the top surface of the first SiO 2 cladding layer 12 except for the bonding interface 17 .

[0051] Depend on Figure 1 , Figure 8 As shown, in the embodiment of the present invention, it is proposed that the bonding interface 17 of the waveguide wafer is located on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10, and the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness. The bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to avoid being over-etched during the etching of the second SiO2 cladding layer 16. The sacrificial layer 15 is removed after the second SiO2 cladding layer 16 is etched, so that the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 (i.e., the bonding interface thickness) is a preset thickness with controllable thickness, thereby reducing or avoiding the bonding interface layer. The thickness error affects the efficiency of the composite modulator after bonding; in addition, when the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface of the waveguide wafer, after the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness and a preset flatness, the bonding interface 17 is protected by the sacrificial layer 15, and the sacrificial layer 15 is used as an etching stop layer to protect the bonding interface 17 from being over-etched during the etching of the second SiO2 cladding layer 16. Finally, the sacrificial layer is removed by a wet etching process to obtain a bonding interface 17 with controllable thickness and a smooth surface, which is beneficial to improving the stability of the subsequent bonding process, as well as the stability and efficiency of the optical performance of the control device.

[0052] In specific implementation, in the current prior art, sacrificial layer technology is mostly used to release and obtain some specific structures. Its main function is to provide necessary structural support or serve as a temporary substrate at a certain stage of device manufacturing, and then be intentionally removed in subsequent steps to release or form the required structure, such as a microstructure bridge, a cantilever beam or a cavity, etc. However, the present application does not obtain some specific structures by releasing the sacrificial layer, but uses the sacrificial layer 15 as an etching stop layer to protect the bonding interface 17 from being over-etched during the etching of the second SiO2 cladding layer 16, thereby protecting the bonding interface 17 from controllable thickness and smooth surface. However, there is no technology in the prior art that uses a sacrificial layer to control and protect the thickness of the bonding interface of the silicon photonic chip.

[0053] For example, the waveguide wafer (or silicon photonic chip) of the present application is a special optical modulation structure in which the waveguide structure 10 and the metal electrode 11 are both located below the bonding interface 17. The preparation of the waveguide structure 10 and the metal electrode 11 will inevitably lead to the problem of uneven bonding interface 17, thereby increasing optical loss and reducing bonding reliability. The present application proposes to deposit a sacrificial layer 15 on the bonding interface 17 as an etching stop layer after adjusting the thickness of the cladding bonding interface 17 on the waveguide structure 10 to reach a preset thickness and a preset flatness, to protect the bonding interface 17 from being over-etched during the etching of the second SiO2 cladding 16, thereby protecting the bonding interface 17 with controllable thickness and flat surface. After removing the sacrificial layer 15 through a wet etching process, a bonding interface 17 with controllable thickness and flat surface can be obtained.

[0054] In a specific implementation, the thickness of the waveguide structure 10 can be 200-450 nm, and the material of the waveguide structure 10 can be silicon nitride, silicon, etc.; the material of the metal electrode 11 can be AlCu or Cu; the thickness of the metal electrode 11 can be 500-1500 nm; the thickness of the first SiO2 cladding 12 can be 0.6-1.6 μm; the thickness of the SiO2 thermal oxide layer 13 can be 2-8 μm; the thickness of the silicon substrate 14 can be 500-800 μm; the thickness of the second SiO2 cladding 16 can be 1-4 μm.

[0055] In a specific implementation, in order to ensure that the waveguide structure 10 and the modulator material bonded at the bonding interface 17 can form a composite waveguide, the preset thickness of SiO2 between the bonding interface 17 and the top surface of the waveguide structure 10 may be 50-150 nm.

[0056] In a specific implementation, the material of the sacrificial layer can be one of Al, AlCu, TiN or α-Si, preferably Al. The thickness of the sacrificial layer can be 100 nm.

[0057] In a specific implementation, in order to improve the structural diversity of the waveguide wafer, realize different composite waveguide spacings, and obtain composite optical waveguide modulators with different modulation efficiencies, it is proposed that the bonding interface 17 can be one place, located on the top surface of the first SiO2 cladding layer 12 above all the waveguide structures 10, such as Figure 8 In addition, the bonding interface 17 can be multiple locations, and the bonding interfaces 17 at different locations are located on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10, and the distance between the bonding interfaces 17 at different locations and the top surface of the waveguide structure 10 is different. Fig.13 As shown, at this time, the bonding interface 17 includes a first bonding interface 171 and a second bonding interface 172 . There may be one or more first bonding interfaces 171 , and there may be one or more second bonding interfaces 172 .

[0058] In a specific implementation, based on any of the above waveguide wafers, the present application also proposes a composite modulator, including:

[0059] Any of the above-mentioned waveguide wafers;

[0060] The optical modulator 18 is bonded at the bonding interface 17, and the optical modulator 18 and the waveguide structure 10 below the bonding interface 17 form a composite waveguide 19. When the bonding interface 17 is one place, the composite modulator formed is as follows: Fig. 9 As shown; when the bonding interface 17 is multiple, including a first bonding interface 171 and a second bonding interface 172, the first optical modulator 181 is bonded to the first bonding interface 171, and the second optical modulator 182 is bonded to the second bonding interface 172, the composite modulator formed is as shown Fig.14 shown.

[0061] In a specific implementation, in order to realize the preparation of the above waveguide wafer, the present application also provides a method for preparing any of the above waveguide wafers, such as Fig.15 As shown, including:

[0062] Step S1501: preparing the SiO2 thermal oxide layer 13 on the top surface of the silicon substrate 14;

[0063] Step S1502: Prepare a first SiO2 cladding layer 12 on the top surface of the SiO2 thermal oxide layer 13, prepare the waveguide structure 10 in the first SiO2 cladding layer 12, and prepare the metal electrode 11 in the first SiO2 cladding layer 12 and the SiO2 thermal oxide layer 13, as shown in FIG. Figure 2 As shown;

[0064] Step S1503: Processing the top surface of the first SiO2 cladding layer 12 so that the SiO2 thickness between the top surface of the first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 after the processing is a preset thickness and the top surface of the first SiO2 cladding layer 12 reaches the preset flatness (the preset flatness may be a flatness that meets bonding requirements);

[0065] Step S1504: preparing the sacrificial layer 15 on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10;

[0066] Step S1505: depositing the second SiO2 cladding layer 16 to cover the first SiO2 cladding layer 12 and the sacrificial layer 15, etching the second SiO2 cladding layer 16, and stopping the etching until the sacrificial layer 15 is completely exposed;

[0067] Step S1506 : removing the sacrificial layer 15 to obtain the bonding interface 17 .

[0068] In a specific implementation, in order to ensure that the bonding interface 17 with controllable thickness and smooth surface is obtained, after the embedded metal electrode 11 (such as Figure 2 After the bonding interface 17 is formed, the distance between the top surface of the first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 is controlled during the deposition of the first SiO2 cladding layer 12, so that the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness, and the first SiO2 cladding layer 12 is flattened to reach a preset flatness. In order to further ensure that the bonding interface 17 can accurately reach a preset thickness and a preset flatness, it is proposed to process the top surface of the first SiO2 cladding layer 12, so that the SiO2 thickness between the top surface of the first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 after the treatment is a preset thickness and the top surface of the first SiO2 cladding layer 12 reaches the preset flatness, including:

[0069] The first SiO2 cladding layer 12 is deposited by cladding filling method, such as Figure 3 As shown, the upper surface of the first SiO2 cladding layer 12 is 300 to 500 nm higher than the upper surface of the waveguide structure 10;

[0070] The first SiO2 cladding layer 12 is subjected to CMP flattening treatment, and the CMP is controlled to end on the top surface of the waveguide structure 10, such as Figure 4 As shown;

[0071] The first SiO2 cladding layer 12 is grown by deposition, so that the SiO2 thickness between the top surface of the grown first SiO2 cladding layer 12 and the top surface of the waveguide structure 10 is a preset thickness (for example, the upper surface of the first SiO2 cladding layer 12 is 50 to 150 nm higher than the upper surface of the waveguide structure 10, so as to obtain a bonding layer with controllable thickness) and the top surface of the first SiO2 cladding layer 12 reaches the preset flatness, so as to obtain a bonding interface 17 with a preset thickness and a preset flatness, such as Figure 5 shown.

[0072] In a specific implementation, after the bonding interface 17 is processed to reach a preset thickness and a preset flatness, a sacrificial layer can be prepared to protect the bonding interface 17. For example, taking the preparation of a sacrificial layer as an example, the sacrificial layer 15 is prepared on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10, including:

[0073] Prepare the sacrificial layer 15, the sacrificial layer 15 covers the first SiO2 cladding layer 12 above all the waveguide structures 10, such as Figure 6 shown.

[0074] In specific implementation, based on Figure 6 After the sacrificial layer 15 is prepared as shown, the second SiO2 cladding layer 16 can be deposited to cover the first SiO2 cladding layer 12 and the sacrificial layer 15. Figure 7 Then, the second SiO2 cladding layer 16 is etched by dry etching, and the etching is stopped when the sacrificial layer 15 is etched. The sacrificial layer 15 prevents over-etching. The sacrificial layer 15 is completely exposed and there is a certain amount of over-etching, such as Figure 1 Finally, the sacrificial layer 15 is removed by wet etching to obtain a bonding interface 17, as shown in FIG. Figure 8 At this time, the distance between the top of the waveguide structure 10 and the bonding interface 17 can be maintained at 50 to 150 nm, and then the optical modulation device 18 is bonded to the bonding interface 17, as shown in FIG. Fig. 9 As shown, after the optical modulation device 18 is bonded, it forms a composite waveguide 19 with the waveguide structure 10 below the bonding interface 17, thereby achieving better optical performance, such as reducing coupling loss and increasing optical bandwidth.

[0075] In a specific implementation, after the bonding interface 17 is processed to reach a preset thickness and a preset flatness, a sacrificial layer can be prepared to protect the bonding interface 17. For example, taking the preparation of multiple sacrificial layers as an example, the sacrificial layer 15 is prepared on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10, including:

[0076] A first sacrificial layer 151 is prepared on the top surface of the first SiO2 cladding layer 12 above a portion of the waveguide structure 10; for example, a 100 nm sacrificial layer (for example, TiN) is deposited on the first SiO2 cladding layer 12 and patterned to obtain a patterned first sacrificial layer 151; a third SiO2 cladding layer 161 is deposited and CMPed to make the distance between the upper surface of the first sacrificial layer 151 and the upper surface of the third SiO2 cladding layer 161 be 100 nm, as shown in FIG. Fig.10 As shown;

[0077] Prepare a third SiO2 cladding layer 161 to cover the first sacrificial layer 151 and the first SiO2 cladding layer 12; for example, deposit the third SiO2 cladding layer 161 and perform CMP so that the distance from the upper surface of the first sacrificial layer 151 to the upper surface of the third SiO2 cladding layer 161 is 100 nm, and the upper surface of the third SiO2 cladding layer 161 above the first sacrificial layer 151 is the first bonding interface 171, as shown in FIG. Fig.10 As shown;

[0078] A second sacrificial layer 152 is prepared on the top surface of the third SiO2 cladding layer 161 above the waveguide structure 10. The second sacrificial layer 152 and the first sacrificial layer 151 do not overlap in horizontal projection. For example, a sacrificial layer of 100 nm is continuously deposited on the flat surface of the third SiO2 cladding layer 161 and patterned to obtain a patterned second sacrificial layer 152, and then a second SiO2 cladding layer 16 is deposited. Fig.11 shown.

[0079] In specific implementation, based on Fig.11 After the second sacrificial layer 152 and the first sacrificial layer 151 are prepared, the second SiO2 cladding 16 can be deposited, and the second SiO2 cladding 16 and the third SiO2 cladding 161 are etched to expose the second sacrificial layer 152 and the first sacrificial layer 151. For example, the second SiO2 cladding 16 is deposited, and the second SiO2 cladding 16 is etched until the sacrificial layer 15 is etched and the etching is stopped. The sacrificial layer 15 is completely exposed (the sacrificial layer 15 includes the second sacrificial layer 152 and the first sacrificial layer 151), including:

[0080] Deposit the second SiO2 cladding layer 16 to cover the third SiO2 cladding layer 161 and the second sacrificial layer 152 (eg Fig.11 As shown in FIG. 1 ), the third SiO2 cladding layer 161 and the second SiO2 cladding layer 16 are etched (for example, dry etching is used) until the first sacrificial layer 151 and the second sacrificial layer 152 are etched and the etching is stopped. The first sacrificial layer 151 and the second sacrificial layer 152 prevent over-etching and protect the corresponding lower SiO2 cladding layer. The first sacrificial layer 151 and the second sacrificial layer 152 are completely exposed. Fig.12As shown, the first sacrificial layer 151 is removed to obtain a first bonding interface 171 (for example, the first sacrificial layer 151 is removed by wet etching), and the second sacrificial layer 152 is removed to obtain a second bonding interface 172 (for example, the second sacrificial layer 152 is removed by wet etching), as shown Fig.13 As shown, the SiO2 thickness (i.e., bonding layer thickness) between the top of the waveguide structure 10 and the first bonding interface 171 can be 100 nm, and the SiO2 thickness (i.e., bonding layer thickness) between the top of the waveguide structure 10 and the second bonding interface 172 can be 300 nm. By patterning the sacrificial layer and adjusting the sacrificial layer thickness and the cladding layer thickness, different bonding layer thicknesses can be controlled.

[0081] Finally, the first modulator material 181 and the second modulator material 182 are bonded to the first bonding interface 171 and the second bonding interface 172 respectively. The first modulator material 181 and the second modulator material 182 form different composite waveguide regions with the corresponding waveguide structure 10 respectively, so that different composite waveguide spacings can be achieved to obtain composite optical waveguide modulators with different modulation efficiencies, such as Fig.14 shown.

[0082] The embodiment of the present invention achieves the following technical effects: it is proposed that the bonding interface 17 of the waveguide wafer is located on the top surface of the first SiO2 cladding layer 12 above the waveguide structure 10, the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 is a preset thickness, the bonding interface 17 is processed to a preset flatness and protected by a sacrificial layer 15 to avoid being over-etched during the etching of the second SiO2 cladding layer 16, the sacrificial layer 15 is removed after the second SiO2 cladding layer 16 is etched, and the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 (i.e., the bonding interface layer thickness) is a preset thickness with controllable thickness, thereby reducing or avoiding the bonding interface 17. The error in layer thickness affects the efficiency of the composite modulator after bonding; in addition, when the waveguide structure 10 and the metal electrode 11 are simultaneously located below the bonding interface of the waveguide wafer, after the SiO2 thickness between the bonding interface 17 and the top surface of the waveguide structure 10 reaches a preset thickness and a preset flatness, the bonding interface 17 is protected by the sacrificial layer 15, and the sacrificial layer 15 is used as an etching stop layer to protect the bonding interface 17 from being over-etched during the etching of the second SiO2 cladding layer 16. Finally, the sacrificial layer is removed by a wet etching process to obtain a bonding interface 17 with controllable thickness and a smooth surface, which is beneficial to improving the stability of subsequent bonding processes, as well as the stability and efficiency of controlling the optical performance of the device.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A waveguide wafer, characterized in that: include: Silicon substrate (14); A SiO2 thermal oxide layer (13) is disposed on the top surface of the silicon substrate (14); A first SiO2 cladding layer (12) is arranged on the top surface of the SiO2 thermal oxide layer (13); A waveguide structure (10) is arranged in the first SiO2 cladding layer (12); A metal electrode (11) is arranged in the first SiO2 cladding layer (12) and the SiO2 thermal oxide layer (13); A bonding interface (17) located on the top surface of the first SiO2 cladding layer (12) above the waveguide structure (10), wherein the SiO2 thickness between the bonding interface (17) and the top surface of the waveguide structure (10) is a preset thickness, the bonding interface (17) is processed to a preset flatness and protected by a sacrificial layer (15) to avoid being over-etched during etching of the second SiO2 cladding layer (16), and the sacrificial layer (15) is removed after etching of the second SiO2 cladding layer (16); The second SiO2 cladding layer (16) is located on the top surface of the first SiO2 cladding layer (12) in an area other than the bonding interface (17).

2. The waveguide wafer according to claim 1, characterized in that The bonding interface (17) is located at one place on the top surface of the first SiO2 cladding layer (12) above all the waveguide structures (10).

3. The waveguide wafer according to claim 1, characterized in that There are multiple bonding interfaces (17), and the bonding interfaces (17) at different locations are located on the top surface of the first SiO2 cladding (12) above different waveguide structures (10). The SiO2 thickness between the bonding interfaces (17) at different locations and the top surface of the corresponding waveguide structure (10) is different.

4. The waveguide wafer according to any one of claims 1 to 3, characterized in that The material of the sacrificial layer is Al.

5. A composite modulator, characterized in that: include: The waveguide wafer according to any one of claims 1 to 4; An optical modulation device (18) is bonded at the bonding interface (17); the optical modulation device (18) and the waveguide structure (10) below the bonding interface (17) form a composite waveguide (19).

6. A method for preparing a waveguide wafer according to any one of claims 1 to 4, characterized in that: include: Preparing the SiO2 thermal oxide layer (13) on the top surface of the silicon substrate (14); A first SiO2 cladding layer (12) is prepared on the top surface of the SiO2 thermal oxide layer (13), the waveguide structure (10) is prepared in the first SiO2 cladding layer (12), and the metal electrode (11) is prepared in the first SiO2 cladding layer (12) and the SiO2 thermal oxide layer (13); Processing the top surface of the first SiO2 cladding layer (12) so that the SiO2 thickness between the top surface of the first SiO2 cladding layer (12) and the top surface of the waveguide structure (10) after the processing is a preset thickness and the top surface of the first SiO2 cladding layer (12) reaches the preset flatness; Preparing the sacrificial layer (15) on the top surface of the first SiO2 cladding layer (12) above the waveguide structure (10); Depositing the second SiO2 cladding layer (16) to cover the first SiO2 cladding layer (12) and the sacrificial layer (15), etching the second SiO2 cladding layer (16), and stopping the etching when the sacrificial layer (15) is reached, so that the sacrificial layer (15) is completely exposed; The sacrificial layer (15) is removed to obtain the bonding interface (17).

7. The preparation method according to claim 6, characterized in that: The sacrificial layer (15) is prepared on the top surface of the first SiO2 cladding layer (12) above the waveguide structure (10), comprising: The sacrificial layer (15) is prepared at one location, and the sacrificial layer (15) covers the first SiO2 cladding layer (12) above all the waveguide structures (10).

8. The preparation method according to claim 6, characterized in that: The sacrificial layer (15) is prepared on the top surface of the first SiO2 cladding layer (12) above the waveguide structure (10), comprising: Preparing a first sacrificial layer (151) on the top surface of the first SiO2 cladding layer (12) above a portion of the waveguide structure (10); Prepare a third SiO2 cladding layer (161) to cover the first sacrificial layer (151) and the first SiO2 cladding layer (12); A second sacrificial layer (152) is prepared on the top surface of the third SiO2 cladding layer (161) above the waveguide structure (10), and the second sacrificial layer (152) and the first sacrificial layer (151) do not overlap in horizontal projection.

9. The preparation method according to claim 8, characterized in that: The second SiO2 cladding layer (16) is deposited to cover the first SiO2 cladding layer (12) and the sacrificial layer (15), and the second SiO2 cladding layer (16) is etched until the sacrificial layer (15) is etched and then stopped, so that the sacrificial layer (15) is completely exposed, comprising: The second SiO2 cladding (16) is deposited to cover the third SiO2 cladding (161) and the second sacrificial layer (152), and the third SiO2 cladding (161) and the second SiO2 cladding (16) are etched. The etching is stopped when the first sacrificial layer (151) and the second sacrificial layer (152) are formed, and the first sacrificial layer (151) and the second sacrificial layer (152) are completely exposed. The first sacrificial layer (151) is removed to obtain a first bonding interface (171), and the second sacrificial layer (152) is removed to obtain a second bonding interface (172).

10. The preparation method according to any one of claims 6 to 9, characterized in that: The top surface of the first SiO2 cladding layer (12) is processed so that the SiO2 thickness between the top surface of the first SiO2 cladding layer (12) and the top surface of the waveguide structure (10) after the processing is a preset thickness and the top surface of the first SiO2 cladding layer (12) reaches the preset flatness, comprising: Depositing the first SiO2 cladding layer (12) by cladding filling method; Performing CMP treatment on the first SiO2 cladding layer (12), and controlling the end of CMP on the top surface of the waveguide structure (10); The first SiO2 cladding layer (12) is grown by deposition, so that the SiO2 thickness between the top surface of the first SiO2 cladding layer (12) and the top surface of the waveguide structure (10) after growth is a preset thickness and the top surface of the first SiO2 cladding layer (12) reaches the preset flatness.

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