Array substrate and display device

Abstract

The invention discloses an array substrate and a display device. The array substrate comprises a display area and a first frame area located on one side of the display area. In a plane perpendicular to the array substrate, the array substrate comprises a substrate and a plurality of heating wires located on one side of the substrate, and the plurality of heating wires are configured to transfer heat to the array substrate; the plurality of heating wires are arranged at intervals along a first direction and extend along a second direction, and the first direction is crossed with the second direction; each heating wire comprises a first line segment and a second line segment which are connected, the first line segment is located in the display area, the second line segment is located in the first frame area, and the resistance of the second line segment is smaller than that of the first line segment; the problem that an existing liquid crystal display is limited in application in a low-temperature use environment can be solved, and the liquid crystal display has high heating efficiency.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0002] Liquid Crystal Display (LCD) is a common type of display at present. LCD displays use two polarized materials with a liquid crystal solution between them. When an electric current passes through the liquid, the crystals are rearranged so that light cannot pass through them. Therefore, each crystal is like a shutter, which can allow light to pass through but also block light. Currently, liquid crystal displays (LCD) are developing towards the goal of being light, thin, short and small.

[0003] However, in low-temperature environments, the viscosity coefficient of liquid crystal is relatively large and it is easy to crystallize, which limits the application of liquid crystal displays in low-temperature environments. Summary of the invention

[0004] The embodiments of the present disclosure provide an array substrate and a display device, which can solve the problem that the existing liquid crystal display is limited in application in a low-temperature use environment and have a higher heating efficiency.

[0005] On the one hand, an embodiment of the present disclosure provides an array substrate, the array substrate comprising a display area and a first frame area located on one side of the display area; in a plane perpendicular to the array substrate, the array substrate comprises a substrate and a plurality of heating lines located on one side of the substrate, the plurality of heating lines being configured to transfer heat to the array substrate; the plurality of heating lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersecting the second direction;

[0006] Each of the heating lines includes a first line segment and a second line segment connected to each other. The first line segment is located in the display area, the second line segment is located in the first frame area, and a resistance of the second line segment is smaller than a resistance of the first line segment.

[0007] In an exemplary embodiment, the material of the second line segment is molybdenum or aluminum.

[0008] In an exemplary embodiment, the square resistance of the second line segment ranges from 0.15Ω / □ to 0.38Ω / □.

[0009] In an exemplary embodiment, the line width of the second line segment ranges from 4.0 micrometers to 4.5 micrometers.

[0010] In an exemplary embodiment, the first border area includes a first sub-area and a second sub-area arranged in sequence along a direction away from the display area; the second sub-area includes at least one binding pin area, the at least one binding pin area includes a plurality of binding pins, and the plurality of second line segments are all located in the first sub-area; the first ends of the plurality of second line segments are electrically connected to the plurality of first line segments in a one-to-one correspondence, and the second ends of the plurality of second line segments are electrically connected to the plurality of binding pins in a one-to-one correspondence.

[0011] In an exemplary embodiment, each of the binding pins includes a first pin line located on one side of the substrate, a connecting electrode located on a side of the first pin line away from the substrate, and at least one insulating layer located between the first pin line and the connecting electrode, wherein the at least one insulating layer includes at least one via hole, and the at least one via hole exposes a portion of the surface of the first pin line away from the substrate;

[0012] The second end of the first lead wire is electrically connected to the second end of the second line segment, and the connecting electrode is electrically connected to the first end of the first lead wire via the at least one via, and the surface of the connecting electrode away from the substrate is configured to be electrically connected to the flexible circuit board.

[0013] In an exemplary embodiment, the at least one insulating layer includes an inorganic insulating layer.

[0014] In an exemplary embodiment, the first sub-area includes at least one driver chip area, the at least one driver chip area includes a plurality of driver chip pins, and the driver chip area is configured to connect a driver chip.

[0015] In an exemplary embodiment, the first sub-area further includes two fan-out areas spaced apart from each other along the first direction, the at least one driver chip area is located between the two fan-out areas, and the plurality of second line segments are all located in the fan-out areas.

[0016] In an exemplary embodiment, the second line segment includes a first segment and a second segment that are stacked, and an orthographic projection of the first segment on the plane where the array substrate is located at least partially overlaps with an orthographic projection of the second segment on the plane where the array substrate is located.

[0017] In an exemplary embodiment, each of the binding pins includes a first pin line located at one side of the substrate, a second pin line located at a side of the first pin line away from the substrate, and a connecting electrode located at a side of the second pin line away from the substrate;

[0018] The first end of the connecting electrode is electrically connected to the first end of the first lead line, and the second end of the connecting electrode is electrically connected to the first end of the second lead line; the second end of the first lead line is electrically connected to the second end of the first section, and the second end of the second lead line is electrically connected to the second end of the second section, and the surface of the connecting electrode on one side away from the substrate is configured to be electrically connected to the flexible circuit board.

[0019] In an exemplary embodiment, the first section and the first lead line are in a same-layer structure, and the second section and the second lead line are in a same-layer structure.

[0020] On the other hand, an embodiment of the present disclosure provides a display device, which includes an array substrate, an opposing substrate and a liquid crystal layer as described in any of the above embodiments; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

[0021] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0023] Figure 1 A schematic diagram of an array substrate according to an embodiment of the present disclosure Figure 1 ;

[0024] Figure 2 for Figure 1 The cross section at the mark AA Figure 1 ;

[0025] Figure 3 for Figure 1 The cross section at the mark AA Figure 2 ;

[0026] Figure 4 for Figure 1 The cross section at the mark AA Figure 3 ;

[0027] Figure 5 A schematic diagram of an array substrate according to an embodiment of the present disclosure Figure 2 ;

[0028] Figure 6 FIG. 4 is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure.

[0029] Reference numerals:

[0030] AA-display area, BB-frame area, B1-first frame area, B2-second frame area, B11-first sub-area, B12-second sub-area, B111-fan-out area, B112-driver chip area, B121-binding pin area;

[0031] 10-substrate, 11-first insulating layer, 12-second insulating layer, 20-heating wire, 21-first wire segment, 22-second wire segment, 30-binding pin, 31-first pin wire, 32-second pin wire, 33-connecting electrode, 40-flexible circuit board, 50-driving chip;

[0032] 100 - array substrate, 200 - counter substrate, 300 - liquid crystal layer, 400 - black matrix, 500 - color filter layer. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0034] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0035] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure includes two and more than two.

[0036] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0037] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0038] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0039] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0040] In the present disclosure, "electrical connection" includes the situation where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0041] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0042] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0043] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0044] An embodiment of the present disclosure provides an array substrate, the array substrate comprising a display area and a first frame area located at one side of the display area; in a plane perpendicular to the array substrate, the array substrate comprises a substrate and a plurality of heating lines located at one side of the substrate, the plurality of heating lines being configured to transfer heat to the array substrate; the plurality of heating lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersecting the second direction;

[0045] Each of the heating lines includes a first line segment and a second line segment connected to each other. The first line segment is located in the display area, the second line segment is located in the first frame area, and a resistance of the second line segment is smaller than a resistance of the first line segment.

[0046] The array substrate provided in the embodiment of the present disclosure can heat the array substrate by setting a plurality of heating lines, thereby improving the problems of large viscosity coefficient of liquid crystal and easy crystallization in a low-temperature use environment, and by setting the resistance of the second line segment to be smaller than the resistance of the first line segment, the heat loss of the heating line in the first frame area can be reduced, thereby improving the heating efficiency of the heating line in the display area.

[0047] Figure 1 A schematic diagram of an array substrate according to an embodiment of the present disclosure Figure 1 .like Figure 1 As shown, the array substrate may include a display area AA and a frame area BB located around the display area AA. The frame area BB may include a first frame area B1 located on one side of the display area AA and a second frame area B2 located on the remaining sides of the display area AA. For example, the first frame area B1 may include a lower frame of the array substrate, and the second frame area B2 may include an upper frame, a left frame, and a right frame of the array substrate.

[0048] In an exemplary embodiment, the display area AA may include: a plurality of data lines (not shown in the figure) and a plurality of gate lines (not shown in the figure) disposed on a substrate. The plurality of gate lines may extend along a first direction X and be arranged in sequence along a second direction Y different from the first direction X. The plurality of data lines may extend along the second direction Y and be arranged in sequence along the first direction X. The first direction X and the second direction Y may intersect, for example, the first direction X may be perpendicular to the second direction Y. The plurality of data lines and the plurality of gate lines may be located in different film layers, for example, the plurality of data lines may be located on a side of the plurality of gate lines away from the substrate.

[0049] In an exemplary embodiment, a plurality of data lines and a plurality of gate lines may cross to form a plurality of sub-pixel regions. The region defined by the intersection of adjacent data lines and adjacent gate lines may be a sub-pixel region. A sub-pixel may be correspondingly arranged in the sub-pixel region. The sub-pixel region may include an opening region and a non-opening region surrounding the opening region. The non-opening region may be a region shielded by the black matrix of the opposing substrate of the array substrate, and the opening region may be a region not shielded by the black matrix of the opposing substrate. Adjacent gate lines and data lines may both be located in the non-opening region. The array substrate of the disclosed embodiment may be used to realize a display function, and the opening region of each sub-pixel region may be configured to display. The non-opening region surrounds the opening region and does not display. However, the disclosed embodiment is not limited to this. In some examples, the array substrate may be used to realize other functions.

[0050] In an exemplary embodiment, the display area AA may include: a plurality of pixel units disposed on a substrate. At least one pixel unit may include: three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in sequence along a first direction X). The three sub-pixels of the pixel unit may be, for example, a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged in sequence in the order of the blue sub-pixel, the red sub-pixel, and the green sub-pixel. At least one sub-pixel may include: a pixel electrode (not shown in the figure) and a common electrode (not shown in the figure), and the positive projections of the pixel electrode and the common electrode of the sub-pixel on the plane where the substrate is located may overlap. The common electrode of the plurality of sub-pixels of the display area AA may be an integral structure. The sub-pixel may also include a first transistor. The first transistor may be adjacent to the intersection of the data line and the gate line. The first transistor may include a first gate, a first pole, and a second pole. The first gate may be electrically connected to the gate line, the first pole of the first transistor may be electrically connected to the data line, and the second pole may be electrically connected to the pixel electrode of a sub-pixel. The first transistor may be configured to provide a data signal transmitted by the data line to the pixel electrode of the sub-pixel under the control of the gate line.

[0051] In an exemplary embodiment, the second border area B2 may include at least a gate driving circuit (eg, including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to a plurality of gate lines in the display area AA. The gate driving circuit may also include a second transistor.

[0052] In an exemplary embodiment, the second border area B2 may include a circuit area, a power line area, a crack dam area and a cutting area arranged in sequence along the direction of the display area AA. The circuit area may be connected to the display area AA, and the circuit area may include at least a gate drive circuit (for example, including a plurality of cascaded shift registers), and the plurality of shift registers may be electrically connected to a plurality of gate lines in the display area AA. The power line area is connected to the circuit area, and the power line area may include at least a low-level power line. The crack dam area may be connected to the power line area, and the crack dam area may include at least a plurality of cracks. The cutting area may be connected to the crack dam area, and the cutting area may include at least a cutting groove, and the cutting groove may be configured so that after all the film layers of the array substrate are prepared, the cutting equipment can cut along the cutting groove.

[0053] In an exemplary embodiment, if Figure 1 As shown, the first border area B1 may include a first sub-area B11 and a second sub-area B12 sequentially arranged in a direction away from the display area AA. The first sub-area B11 may include at least one fan-out area B111 and at least one driver chip area B112. Figure 1 As shown, the first sub-area B11 may include two fan-out areas B111 and a driver chip area B112. The two fan-out areas B111 may be spaced apart along the first direction X, and the driver chip area B112 may be located between the two fan-out areas B111. The orthographic projection of the fan-out area B111 on the plane where the array substrate is located may be a trapezoid, and the orthographic projection of the driver chip area B112 on the plane where the array substrate is located may be a rectangle. The driver chip area B112 may include a plurality of driver chip pins, and the driver chip area B112 is configured to be used for connecting a driver chip (Integrated Circuit, IC), and the driver chip may be electrically connected to the data line of the display area AA through the driver chip pins. The driver chip may be configured to generate a signal required for driving a sub-pixel, and provide the drive signal to the data line of the display area.

[0054] In an exemplary embodiment, if Figure 1As shown, the second sub-area B12 may include at least one binding pin area B121. For example, the second sub-area B12 may include two binding pin areas B121, and the two binding pin areas B121 are spaced apart along the first direction X. The fan-out area B111 and the binding pin area B121 may be arranged in groups in a one-to-one correspondence. The binding pin area B121 may include a plurality of binding pins, and the binding pins may be configured to be bound and connected to at least one corresponding circuit board (e.g., a flexible printed circuit (FPC)).

[0055] In an exemplary embodiment, if Figure 1 As shown, the array substrate may further include a conductive layer located on one side of the substrate 10, and the conductive layer may include a plurality of heating lines 20. The plurality of heating lines 20 are arranged at intervals along the first direction X and extend along the second direction Y. Each heating line 20 includes a first line segment 21 and a second line segment 22 connected to each other. The first line segment 21 may be located in the display area AA, and the second line segment 22 may be located in the first sub-area B11. The first end of the second line segment 22 may be electrically connected to the first line segment 21, and the second end of the second line segment 22 may be electrically connected to the binding pin. Figure 1 As shown, the plurality of first line segments 21 may be distributed along the first direction X at equal intervals.

[0056] In an exemplary embodiment, the first line segment 21 and the second line segment 22 may be located in the same conductive layer, or may be located in different conductive layers.

[0057] In an exemplary embodiment, the material of the second line segment 22 may be molybdenum (Mo) or aluminum (Al). At room temperature, the resistivity of molybdenum (Mo) is about 5.2 ohm·meter (Ω·m), and the resistivity of aluminum (Al) is about 2.83×10 -8 Ohm·meter (Ω·m). The calculation formula for sheet resistance is: Rs=ρ / t, where Rs represents the sheet resistance, ρ represents the resistivity of the material, and t represents the thickness of the film layer. It can be seen from the above calculation formula that the smaller the resistivity of the material, the smaller the sheet resistance. When t is set to 2800 angstroms, the sheet resistance of the second line segment 22 using aluminum (Al) is approximately 0.15Ω / □ (Ω / sq), and the sheet resistance of the second line segment 22 using molybdenum (Mo) is approximately 0.38Ω / □ (Ω / sq).

[0058] In an exemplary embodiment, the line width of the second line segment 22 may range from 4.0 microns to 4.5 microns. When the material and length of the second line segment 22 are constant, the larger the cross-sectional area of ​​the second line segment 22, the smaller the resistance of the second line segment 22. When the material of the second line segment 22 is aluminum (Al), when the line width of the second line segment 22 is 4.0 microns, the resistance of the second line segment 22 is approximately 364 ohms. When the material of the second line segment 22 is aluminum (Al), when the line width of the second line segment 22 is 4.5 microns, the resistance of the second line segment 22 is approximately 314.5 ohms. It can be seen that increasing the line width of the second line segment 22 can reduce its resistance.

[0059] In an exemplary embodiment, the second line segment 22 may include a first segment and a second segment arranged in a stacked manner. The first segment is closer to the substrate 10 than the second segment, and the orthographic projection of the first segment on the plane where the array substrate is located may overlap at least partially with the orthographic projection of the second segment on the plane where the array substrate is located. For example, the orthographic projection of the first segment on the plane where the array substrate is located may overlap with the orthographic projection of the second segment on the plane where the array substrate is located. The second end of the first segment and the second end of the second segment are both electrically connected to the binding pin, and the first end of the first segment and the first end of the second segment are both electrically connected to the first line segment 21. The second line segment 22 is arranged to include the first segment and the second segment arranged in a stacked manner, so as to form a parallel wiring form, reduce the resistance of the heating line in the first frame area, reduce the heating loss generated by the heating line in the first frame area, and improve the heating efficiency of the heating line. For example, when the materials of the first segment and the second segment are both aluminum (Al), the second line segment adopts the first segment and the second segment in parallel, and the resistance of the second line segment is about 210 ohms.

[0060] Figure 2 for Figure 1 The cross section at the mark AA Figure 1 In the embodiment of the present disclosure, the thickness direction of the array substrate is defined as a third direction and is marked as Z. In the embodiment of the present disclosure, the first direction X, the second direction Y and the third direction Z are perpendicular to each other.

[0061] like Figure 2 As shown, the binding pin 30 may include a first pin line 31, a second pin line 32 and a connecting electrode 33 located on one side of the substrate 10. The first pin line 31 is closer to the substrate 10 than the second pin line 32 and the connecting electrode 33, and the second pin line 32 is located between the first pin line 31 and the connecting electrode 33. For example, the first section and the first pin line 31 may be in the same layer structure, and the second section and the second pin line 32 may be in the same layer structure.

[0062] like Figure 2As shown, the binding pin 30 may also include a first insulating layer 11 located between the first pin line 31 and the second pin line 32, and a second insulating layer 12 located between the second pin line 32 and the connecting electrode 33. The second insulating layer 12 includes at least one first via K1 and at least one second via K2. The first insulating layer 11 and the second insulating layer 12 in the first via K1 are both etched away, exposing a portion of the surface of the first pin line 31 away from the substrate 10. The second insulating layer 12 in the second via K2 is etched away, exposing a portion of the surface of the second pin line 32 away from the substrate 10. The first end of the connecting electrode 33 is electrically connected to the first end of the first pin line 31 via the first via K1, and the second end of the connecting electrode 33 is electrically connected to the first end of the second pin line 32 via the second via K2. The second end of the first pin line 31 is configured to be electrically connected to the second end of the first section, and the second end of the second pin line 32 is configured to be electrically connected to the second end of the second section. The surface of the connecting electrode 33 away from the substrate 10 is configured to be electrically connected to the flexible circuit board.

[0063] In an exemplary embodiment, the first insulating layer 11 and the second insulating layer 12 may be made of inorganic materials. For example, silicon oxynitride (SiO x N y ) or silicon nitride (SiN x ) or silicon oxide (SiO x ) etc. The first insulating layer 11 and the second insulating layer 12 may be a single layer or a multi-layer or a composite layer structure.

[0064] In an exemplary embodiment, the material of the first lead wire 31 and the second lead wire 32 may be a metal material, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the material of the first lead wire 31 and the second lead wire 32 may be an alloy material of metal materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb) or molybdenum-nickel-titanium alloy (MoNiTi). The first lead wire 31 and the second lead wire 32 may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti or Mo / Nb / Cu or MoNiTi / Cu or MoNb / Cu / MoNiTi or MoNiTi / Cu / MoNiTi, etc.

[0065] In an exemplary embodiment, the material of the connection electrode 33 may be a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the connection electrode 33 may be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0066] In an exemplary embodiment, the substrate 10 may be a transparent substrate. For example, the substrate 10 may be a rigid substrate or a flexible substrate. For example, the material of the rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of the flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. However, the embodiments of the present disclosure are not limited thereto.

[0067] Figure 3 for Figure 1 The cross section at the mark AA Figure 2 .like Figure 3 As shown, the binding pin 30 may include a first pin line 31 and a connection electrode 33 located at one side of the substrate 10. The first pin line 31 is closer to the substrate 10 than the connection electrode 33.

[0068] like Figure 3 As shown, the binding pin 30 may further include a first insulating layer 11 and a second insulating layer 12 located between the first pin line 31 and the connecting electrode 33. The second insulating layer 12 includes at least one first via hole K1, and the first insulating layer 11 and the second insulating layer 12 in the first via hole K1 are both etched away, exposing a portion of the surface of the first pin line 31 away from the substrate 10. The connecting electrode 33 is electrically connected to the first end of the first pin line 31 via the first via hole K1. The second end of the first pin line 31 is configured to be electrically connected to the second end of the second line segment, and the surface of the connecting electrode 33 away from the substrate 10 is configured to be electrically connected to the flexible circuit board.

[0069] Figure 4 for Figure 1 The cross section at the mark AA Figure 3 .like Figure 4 As shown, the binding pin 30 may include a first pin line 31 and a connection electrode 33 located at one side of the substrate 10. The first pin line 31 is closer to the substrate 10 than the connection electrode 33.

[0070] like Figure 4As shown, the binding pin 30 may further include a first insulating layer 11 located between the substrate 10 and the first lead line 31, and a second insulating layer 12 located between the first lead line 31 and the connecting electrode 33. The second insulating layer 12 includes at least one first via K1, and the second insulating layer 12 in the first via K1 is etched away to expose a portion of the surface of the first lead line 31 away from the substrate 10. The connecting electrode 33 is electrically connected to the first end of the first lead line 31 via the first via K1. The second end of the first lead line 31 is configured to be electrically connected to the second end of the second line segment, and the surface of the connecting electrode 33 on the side away from the substrate 10 is configured to be electrically connected to the flexible circuit board.

[0071] Figure 5 A schematic diagram of an array substrate according to an embodiment of the present disclosure Figure 2 .like Figure 5 As shown, the array substrate may further include a flexible circuit board 40, which may be bound and connected to a plurality of binding pins. For example, the orthographic projection of the flexible circuit board 40 on the plane where the array substrate is located may include the orthographic projections of two binding pin areas B121 on the plane where the array substrate is located.

[0072] like Figure 5 As shown, the array substrate may further include a driver chip 50, the orthographic projection of the driver chip 50 on the plane where the array substrate is located may include the orthographic projection of the driver chip area B112 on the plane where the array substrate is located, and the driver chip 50 is bound and connected with a plurality of driver chip pins. The driver chip 50 may be electrically connected to the data line of the display area AA through the driver chip pins. The driver chip 50 may be configured to generate a signal required for driving the sub-pixel and provide the drive signal to the data line of the display area.

[0073] Figure 6 FIG. 1 is a partial cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure. Figure 6 As shown, the display device may further include an opposing substrate 200 and a liquid crystal layer 300 disposed between the array substrate 100 and the opposing substrate 200. The array substrate 100 may be the array substrate described in any of the above embodiments.

[0074] In an exemplary embodiment, if Figure 6 As shown, the counter substrate 200 may include a base substrate, and a black matrix 400 and a color filter layer 500 disposed on the base substrate. However, the embodiment of the present disclosure is not limited to this.

[0075] The embodiment of the present disclosure further provides a display device. The display device includes the array substrate described in any of the above embodiments. The display device can be: a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function. The embodiment of the present disclosure is not limited to this.

[0076] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. An array substrate, characterized in that: The array substrate includes a display area and a first frame area located on one side of the display area; in a plane perpendicular to the array substrate, the array substrate includes a substrate and a plurality of heating lines located on one side of the substrate, the plurality of heating lines are configured to transfer heat to the array substrate; the plurality of heating lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersecting the second direction; Each of the heating lines includes a first line segment and a second line segment connected to each other. The first line segment is located in the display area, the second line segment is located in the first frame area, and a resistance of the second line segment is smaller than a resistance of the first line segment.

2. The array substrate according to claim 1, characterized in that: The material of the second line segment is molybdenum or aluminum.

3. The array substrate according to claim 1, characterized in that: The square resistance of the second line segment ranges from 0.15Ω / □ to 0.38Ω / □.

4. The array substrate according to claim 1, wherein: The line width of the second line segment ranges from 4.0 micrometers to 4.5 micrometers.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The first border area includes a first sub-area and a second sub-area which are arranged in sequence along a direction away from the display area; the second sub-area includes at least one binding pin area, the at least one binding pin area includes a plurality of binding pins, and the plurality of second line segments are all located in the first sub-area; the first ends of the plurality of second line segments are electrically connected to the plurality of first line segments in a one-to-one correspondence, and the second ends of the plurality of second line segments are electrically connected to the plurality of binding pins in a one-to-one correspondence.

6. The array substrate according to claim 5, characterized in that: Each of the binding pins comprises a first pin line located at one side of the substrate, a connecting electrode located at a side of the first pin line away from the substrate, and at least one insulating layer located between the first pin line and the connecting electrode, wherein the at least one insulating layer comprises at least one via hole, and the at least one via hole exposes a portion of the surface of the first pin line away from the substrate; The second end of the first lead wire is electrically connected to the second end of the second line segment, and the connecting electrode is electrically connected to the first end of the first lead wire via the at least one via, and the surface of the connecting electrode away from the substrate is configured to be electrically connected to the flexible circuit board.

7. The array substrate according to claim 6, characterized in that: The at least one insulating layer includes an inorganic insulating layer.

8. The array substrate according to claim 5, characterized in that: The first sub-area includes at least one driver chip area, the at least one driver chip area includes a plurality of driver chip pins, and the driver chip area is configured to connect a driver chip.

9. The array substrate according to claim 8, characterized in that: The first sub-area further includes two fan-out areas spaced apart from each other along the first direction, the at least one driver chip area is located between the two fan-out areas, and the plurality of second line segments are all located in the fan-out areas.

10. The array substrate according to claim 5, characterized in that: The second line segment includes a first segment and a second segment which are stacked, and an orthographic projection of the first segment on the plane where the array substrate is located at least partially overlaps with an orthographic projection of the second segment on the plane where the array substrate is located.

11. The array substrate according to claim 10, characterized in that: Each of the binding pins comprises a first pin line located at one side of the substrate, a second pin line located at a side of the first pin line away from the substrate, and a connecting electrode located at a side of the second pin line away from the substrate; The first end of the connecting electrode is electrically connected to the first end of the first lead line, and the second end of the connecting electrode is electrically connected to the first end of the second lead line; the second end of the first lead line is electrically connected to the second end of the first section, and the second end of the second lead line is electrically connected to the second end of the second section, and the surface of the connecting electrode on one side away from the substrate is configured to be electrically connected to the flexible circuit board.

12. The array substrate according to claim 11, characterized in that: The first section and the first lead line are in the same layer structure, and the second section and the second lead line are in the same layer structure.

13. A display device, characterized in that: It comprises an array substrate, an opposing substrate and a liquid crystal layer as described in any one of claims 1 to 12; the array substrate and the opposing substrate are arranged opposite to each other, and the liquid crystal layer is located between the array substrate and the opposing substrate.

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