Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The array substrate comprises a substrate, a first conductive layer, a second conductive layer and a third conductive layer, the first conductive layer comprises a plurality of signal lines arranged at intervals in the first direction; the second conductive layer comprises a plurality of common electrodes; the third conductive layer comprises a plurality of pixel electrodes; wherein the second conductive layer further comprises a first gap, the first gap is located between at least two adjacent common electrodes in the first direction, and the orthographic projection of the signal line on the substrate and the orthographic projection of the first gap on the substrate are at least partially overlapped; the third conductive layer further comprises a shielding electrode, a fixed voltage signal is accessed into the shielding electrode, the orthographic projection of the shielding electrode on the substrate is at least partially overlapped with the orthographic projection of the signal line on the substrate, and the orthographic projection of the shielding electrode on the substrate is at least partially overlapped with the orthographic projection of the first gap on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the continuous development of display technology, liquid crystal display (LCD) panels with touch function are widely used in mobile phones, tablets, laptops, car displays and other fields. The touch function in the LCD panel can be realized by dividing the common electrode into blocks. After the division, the capacitance at different positions of the LCD panel can be detected to locate the touch position. However, the division of the common electrode into blocks will cause crosstalk problems.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, an array substrate is provided, comprising a substrate, a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer is located on one side of the substrate, and the first conductive layer comprises a plurality of signal lines spaced apart along a first direction; the second conductive layer is located on a side of the first conductive layer away from the substrate, and the second conductive layer comprises a plurality of common electrodes; the third conductive layer is located on a side of the second conductive layer away from the substrate, and the third conductive layer comprises a plurality of pixel electrodes; wherein the second conductive layer further comprises a first gap, the first gap is located between at least two common electrodes adjacent to each other in the first direction, and the orthographic projection of the signal line on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate; the third conductive layer further comprises a shielding electrode, the shielding electrode is connected to a fixed voltage signal, the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate.

[0005] According to some exemplary embodiments, the array substrate further includes at least one first insulating layer located between the second conductive layer and the third conductive layer, the at least one first insulating layer includes a first via hole, and the shielding electrode is electrically connected to the common electrode through the first via hole.

[0006] According to some exemplary embodiments, the multiple common electrodes include a first common electrode and a second common electrode, the first common electrode and the second common electrode are respectively located on both sides of the first gap in the first direction; the first common electrode includes a first electrode main body and a first protrusion, the second common electrode includes a second electrode main body and a first groove, the first protrusion protrudes from the first electrode main body in a direction toward the second common electrode, and the first groove is recessed from the second electrode main body in a direction away from the first common electrode; and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

[0007] According to some exemplary embodiments, an orthographic projection of the first protrusion on the substrate covers an orthographic projection of the first via on the substrate.

[0008] According to some exemplary embodiments, the plurality of pixel electrodes are arranged in an array along the first direction and the second direction to form a plurality of pixel electrode rows arranged at intervals in the second direction and a plurality of pixel electrode columns arranged at intervals in the first direction, and the first direction and the second direction intersect; the third conductive layer includes a second slit extending along the first direction, and the second slit is located between two adjacent pixel electrode rows; the third conductive layer includes a plurality of third slits, and the plurality of third slits are respectively located between two adjacent pixel electrode columns; and the orthographic projection of the first via on the substrate is located within the orthographic projection of the intersection area of ​​the second slit and the third slit on the substrate.

[0009] According to some exemplary embodiments, the first gap includes a first sub-gap and a second sub-gap, the first sub-gap being a portion of the first gap located in the intersection area, and the second sub-gap being a portion of the first gap located between two adjacent pixel electrodes in the first direction; and the orthographic projection of the shielding electrode on the first conductive layer at least partially overlaps with the first portion of the signal line, and the first portion of the signal line is located within the orthographic projection of the first sub-gap on the first conductive layer, and / or the orthographic projection of the shielding electrode on the first conductive layer covers the second portion of the signal line, and the second portion of the signal line is located within the orthographic projection of the second sub-gap on the first conductive layer.

[0010] According to some exemplary embodiments, the orthographic projections of the multiple signal lines on the substrate at least partially overlap with the orthographic projections of the multiple third gaps on the substrate, respectively; wherein the third conductive layer includes at least one first gap group, and the first gap group includes at least one third gap; and in the area where each third gap of the first gap group is located, the orthographic projection of the first gap on the substrate at least partially overlaps with the orthographic projection of the third gap in the first gap group on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the third gap in the first gap group on the substrate.

[0011] According to some exemplary embodiments, the third conductive layer includes at least one second slit group, the second slit group includes at least one third slit; and in the area where each third slit of the second slit group is located, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; and / or, the orthographic projection of the first slit on the substrate and the orthographic projection of the third slit in the second slit group on the substrate are arranged at intervals in the first direction, and the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the third slit in the second slit group on the substrate are arranged at intervals in the first direction.

[0012] According to some exemplary embodiments, the third conductive layer includes at least one third slit group, the third slit group includes at least one third slit; and in the area where each third slit of the third slit group is located, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; and / or, the orthographic projection of the first slit on the substrate and the orthographic projection of the third slit in the third slit group on the substrate are arranged at intervals in the first direction, and the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the third slit in the third slit group on the substrate at least partially overlap.

[0013] According to some exemplary embodiments, the third conductive layer includes a plurality of the shielding electrodes, and the plurality of the shielding electrodes and the plurality of the pixel electrode columns are alternately arranged in the first direction.

[0014] According to some exemplary embodiments, in the first direction, one shielding electrode is provided every at least one pixel electrode column; and / or, in the first direction, one first gap is provided every at least one pixel electrode column.

[0015] According to some exemplary embodiments, the plurality of pixel electrodes include a first pixel electrode and a second pixel electrode, the first pixel electrode and the second pixel electrode are respectively located in adjacent pixel electrode rows, the first pixel electrode extends along a third direction, the second pixel electrode extends along a fourth direction, the third direction intersects with the first direction and the second direction, respectively, and the fourth direction intersects with the first direction, the second direction and the third direction, respectively; a portion of the shielding electrode adjacent to the first pixel electrode extends along the third direction, and a portion of the shielding electrode adjacent to the second pixel electrode extends along the fourth direction; or, the pixel electrode includes a first electrode portion, a second electrode portion and a connecting portion, the first electrode portion extends along the third direction, the second electrode portion extends along the fourth direction, the third direction intersects with the fourth direction, and the connecting portion is used to connect the first electrode portion and the second electrode portion; a portion of the shielding electrode adjacent to the first electrode portion extends along the third direction, a portion of the shielding electrode adjacent to the second electrode portion extends along the fourth direction, and in the first direction, a portion of the shielding electrode adjacent to the connecting portion protrudes toward the same side as the connecting portion.

[0016] According to some exemplary embodiments, in the first direction, the shielding electrode is spaced equal to the distance between two adjacent pixel electrodes.

[0017] According to some exemplary embodiments, the pixel electrode includes a pixel electrode main body and a second protrusion, the shielding electrode includes a shielding electrode main body and a second groove, the second protrusion protrudes from the pixel electrode main body in a direction toward the shielding electrode, and the second groove is recessed from the shielding electrode main body in a direction away from the second protrusion; and the protruding directions of the second protrusions located in the same pixel electrode row are the same, and the protruding directions of the second protrusions located in two adjacent pixel electrode rows are opposite.

[0018] According to some exemplary embodiments, the common electrode is reused as a touch electrode; the first conductive layer also includes a plurality of touch lines spaced apart along the first direction, the touch lines being electrically connected to the common electrode; and the orthographic projection of the touch lines on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate, or the orthographic projection of the touch lines on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate.

[0019] According to some exemplary embodiments, the common electrode is reused as a touch electrode; the array substrate also includes a fourth conductive layer, the fourth conductive layer is located between the first conductive layer and the second conductive layer, the fourth conductive layer includes a plurality of touch traces spaced along the first direction, the touch traces are electrically connected to the common electrode; and the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; and / or, the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate; and / or, the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate.

[0020] According to some exemplary embodiments, the array substrate includes a first insulating layer and a second insulating layer, the first insulating layer is located between the second conductive layer and the third conductive layer, and the second insulating layer is located between the second conductive layer and the fourth conductive layer; the array substrate includes a first via hole and a second via hole, the first via hole passes through the first insulating layer, and the second via hole passes through the first insulating layer and the second insulating layer; and the shielding electrode is electrically connected to the common electrode through the first via hole, and the shielding electrode is electrically connected to the touch control trace through the second via hole.

[0021] In another aspect, a display panel is provided, comprising the array substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other objects and advantages of the present disclosure will be apparent from the following description of the present disclosure with reference to the accompanying drawings, and will help to have a comprehensive understanding of the present disclosure.

[0023] Figure 1 A partial structural diagram of an array substrate in the related art is schematically shown.

[0024] Figure 2 Schematically shows Figure 1 Magnified view of the P1 region.

[0025] Figure 3 The schematic diagram schematically shows the principle of crosstalk generation in the related art.

[0026] Figure 4 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0027] Figure 5 Schematically shows Figure 4 Magnified view of the P2 region.

[0028] Figure 6The schematic diagram schematically shows the principle of improving crosstalk in the embodiment of the present disclosure.

[0029] Figure 7 The diagram schematically shows a film layer stacking diagram of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 8 A partial structural diagram of a first common electrode and a second common electrode according to some embodiments of the present disclosure is schematically shown.

[0031] Fig. 9 A schematic diagram of the distribution area of ​​the first sub-slot and the second sub-slot according to some embodiments of the present disclosure is schematically shown.

[0032] Fig.10 A schematic diagram of the distribution area of ​​the third gap according to some embodiments of the present disclosure is schematically shown.

[0033] Fig.11 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0034] Fig.12 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0035] Fig.13 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0036] Fig.14 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0037] Fig.15 Schematically shows Fig.14 A magnified view of the P3 region.

[0038] Fig.16 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0039] Fig.17 Schematically shows Fig.16 Magnified view of the P4 region.

[0040] Fig.18 A partial structural diagram of an array substrate according to some embodiments of the present disclosure is schematically shown.

[0041] Fig.19 Schematically shows Fig.18 Magnified view of the P5 region.

[0042] Fig. 20Schematically shows the Fig.19 Cross-sectional view along the A-A' direction.

[0043] Fig.21 The diagram schematically shows a film layer stacking diagram of an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] In the following description, for the purpose of explanation, many specific details are set forth to provide a comprehensive understanding of various exemplary embodiments. However, it is apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, the specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0045] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In addition, the same reference numerals represent the same elements.

[0046] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on, directly connected to, or directly coupled to another element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there are no intermediate elements. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection.

[0047] It should be understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the exemplary embodiment, the first element may be named as the second element, and similarly, the second element may be named as the first element.

[0048] Figure 1 It is a schematic diagram of the local structure of an array substrate in the related art. Figure 2 yes Figure 1 Magnified view of the P1 region. Figure 3 It is a schematic diagram of the principle of crosstalk generation in the related art.

[0049] Reference Figures 1 to 3 In the related art, the array substrate includes a substrate, a first conductive layer 20, a second conductive layer 30 and a third conductive layer 40. The first conductive layer 20 includes a plurality of signal lines 201 (for example, data lines Data for transmitting data signals) spaced apart along a first direction X1, the second conductive layer 30 includes a plurality of common electrodes 301, and the third conductive layer 40 includes a plurality of pixel electrodes 401. The liquid crystal molecules can be driven to deflect by controlling the lateral electric field formed between the pixel electrodes 401 and the common electrodes 301 to achieve display effects of different grayscales. Among them, the second conductive layer 30 also includes a first slit S1, and the first slit S1 is located between at least two adjacent common electrodes 301 in the first direction X1. The orthographic projection of the signal line 201 on the substrate at least partially overlaps with the orthographic projection of the first slit S1 on the substrate, that is, the signal line 201 (such as the orthographic projection of the first slit S1) is located in the area where the first slit S1 is located between two adjacent common electrodes 301. Figure 2 shown).

[0050] It should be noted that in the field of flat panel displays, crosstalk refers to a display abnormality in which the display of a certain area of ​​the screen is affected by another area, causing image distortion. The causes of crosstalk include capacitive coupling. For example, Figure 3 As shown, due to the capacitive coupling between the signal line 201 and the pixel electrode 401 (for example, there is an electric field directed from the signal line 201 to the pixel electrode 401), when the voltage on the signal line 201 changes, it will affect the voltage of the pixel electrode 401, so that the actual voltage of the pixel electrode 401 is different from the set voltage, thereby causing brightness deviation (i.e., crosstalk). Therefore, in order to solve at least one aspect of the above technical problems, the embodiments of the present disclosure provide an array substrate and a display panel, which are conducive to improving the crosstalk problem between the signal line 201 and the pixel electrode 401.

[0051] In some embodiments, Figure 3 As shown, a color filter layer 2 is further provided on the side of the pixel electrode 401 away from the common electrode 301. The color filter layer 2 may include a first filter portion 21 and a second filter portion 22 to achieve color display. The first filter portion 21 is, for example, a blue light filter portion, and the second filter portion 22 is, for example, a red light filter portion. The color filter layer 2 may also include a green light filter portion.

[0052] Figure 4 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. Figure 5 yes Figure 4 Magnified view of the P2 region. Figure 6 It is a schematic diagram of the principle of improving crosstalk in an embodiment of the present disclosure. Figure 7 is a schematic diagram of film layer stacking of an array substrate according to some embodiments of the present disclosure. Figure 8 is a schematic diagram of a partial structure of the first common electrode 31 and the second common electrode 32 according to some embodiments of the present disclosure. Fig. 9 Schematic diagram of the distribution area of ​​the first sub-slit S11 and the second sub-slit S12 according to some embodiments of the present disclosure. Fig.10 is a schematic diagram of the distribution area of ​​the third gap S3 according to some embodiments of the present disclosure.

[0053] Reference Figures 4 to 10 The array substrate includes a substrate 10 (refer to Figure 7 ), a first conductive layer 20, a second conductive layer 30 and a third conductive layer 40. The first conductive layer 20 is located on one side of the substrate 10, and the first conductive layer 20 includes a plurality of signal lines 201 (for example, data lines Data for transmitting data signals) spaced apart along the first direction X1. The second conductive layer 30 is located on the side of the first conductive layer 20 away from the substrate 10, and the second conductive layer 30 includes a plurality of common electrodes 301. The third conductive layer 40 is located on the side of the second conductive layer 30 away from the substrate 10, and the third conductive layer 40 includes a plurality of pixel electrodes 401. The second conductive layer 30 also includes a first slit S1, and the first slit S1 is located between at least two adjacent common electrodes 301 in the first direction X1, and the orthographic projection of the signal line 201 on the substrate 10 at least partially overlaps with the orthographic projection of the first slit S1 on the substrate 10, that is, the area where the first slit S1 is located between two adjacent common electrodes 301 contains a signal line 201 (such as Figure 5 As shown). The third conductive layer 40 further includes a shielding electrode 402, that is, the shielding electrode 402 is arranged in the same layer as the pixel electrode 401. The shielding electrode 402 is connected to a fixed voltage signal (for example, a ground voltage GND), and the orthographic projection of the shielding electrode 402 on the substrate 10 at least partially overlaps with the orthographic projection of the signal line 201 on the substrate 10, and the orthographic projection of the shielding electrode 402 on the substrate 10 at least partially overlaps with the orthographic projection of the first slit S1 on the substrate 10, that is, the shielding electrode 402 is arranged above the signal line 201 in the area where the first slit S1 is located (specifically, on the side away from the substrate 10).

[0054] It should be noted that, in this embodiment, by dividing the second conductive layer 30 into a plurality of common electrode blocks, the common electrode 301 can be reused as a touch electrode to realize the touch function of multiple regions, thereby reducing the thickness of the panel and improving the integration of the display and touch functions. Specifically, in the display stage, the common electrode 301 receives a display voltage signal (such as a reference voltage VCOM); in the touch stage, the common electrode 301 is used as a touch electrode to receive a touch voltage signal, and the touch position is identified by detecting the change in capacitance between the common electrode 301 and GND when a finger or stylus touches and when there is no touch.

[0055] In some embodiments of the present disclosure, Figure 4 As shown, the first conductive layer 20 further includes a plurality of touch lines 202 spaced apart along the first direction X1, that is, the touch lines 202 can be arranged in the same layer as the signal lines 201. The touch lines 202 are electrically connected to the common electrodes 301, that is, the plurality of common electrodes 301 are electrically connected to the driving chip through the touch lines 202. The orthographic projection of the touch lines 202 on the substrate 10 at least partially overlaps with the orthographic projection of the pixel electrode 401 on the substrate 10, that is, the touch lines 202 can be arranged in the pixel opening area (that is, the area where the pixel electrode 401 is located).

[0056] In some embodiments of the present disclosure, Figure 4 As shown, the first conductive layer 20 further includes a source / drain 203, that is, the source / drain 203 is arranged in the same layer as the signal line 201. The pixel electrode 401 is electrically connected to the source / drain 203 through the connection hole 2031 (refer to Figure 7 ), thereby providing a driving voltage to the pixel electrode 401 through the source / drain 203.

[0057] It can be understood that, in this embodiment, by providing the shielding electrode 402 and connecting the shielding electrode 402 to a fixed voltage signal, the coupling electric field between the signal line 201 and the pixel electrode 401 can be interrupted. Figure 6 As shown, after adding the shielding electrode 402, an electric field from the signal line 201 to the shielding electrode 402 and an electric field from the pixel electrode 401 to the shielding electrode 402 can be formed respectively, so that the electric field formed between the pixel electrode 401 and the shielding electrode 402 will not be affected by the signal line 201, thereby improving the crosstalk problem between the signal line 201 and the pixel electrode 401, and the electric field formed between the pixel electrode 401 and the shielding electrode 402 can also enhance the lateral electric field formed between the pixel electrode 401 and the common electrode 301.

[0058] In some embodiments of the present disclosure, the array substrate further includes at least one first insulating layer 50 (see Figure 7 ), at least one first insulating layer 50 includes a first via hole 501 (refer to Figure 5 ), the shielding electrode 402 is electrically connected to the common electrode 301 through the first via hole 501. That is, the shielding electrode 402 is connected to the voltage of the common electrode 301, so there is no need to introduce an additional fixed voltage signal.

[0059] In some embodiments of the present disclosure, referring to Figure 4 , Figure 5 and Figure 8The plurality of common electrodes 301 include a first common electrode 31 and a second common electrode 32. The first common electrode 31 and the second common electrode 32 are respectively located on both sides of the first slit S1 in the first direction X1. Figure 5 In the embodiment, the first common electrode 31 is located on the left side of the first slit S1, and the second common electrode 32 is located on the right side of the first slit S1; Figure 8 In the embodiment, the first common electrode 31 is located on the right side of the first slit S1, and the second common electrode 32 is located on the left side of the first slit S1. The first common electrode 31 includes a first electrode main body 311 and a first protrusion 312, and the second common electrode 32 includes a second electrode main body 321 and a first groove 322. The first protrusion 312 protrudes from the first electrode main body 311 in a direction toward the second common electrode 32, and the first groove 322 is recessed from the second electrode main body 321 in a direction away from the first common electrode 31. The orthographic projection of the shielding electrode 402 on the substrate 10 at least partially overlaps with the orthographic projection of the first protrusion 312 on the substrate 10.

[0060] It can be understood that in this embodiment, by making the first common electrode 31 include the first protrusion 312 and the second common electrode 32 include the first groove 322 (i.e., the avoidance structure corresponding to the first protrusion 312), the shielding electrode 402 located above the signal line 201 in the area where the first gap S1 is located can be electrically connected to the first protrusion 312 through the first via 501, so that the shielding electrode 402 is connected to the common electrode 301 voltage. In some embodiments of the present disclosure, the orthographic projection of the first protrusion 312 on the substrate 10 covers the orthographic projection of the first via 501 on the substrate 10. That is, the first via 501 specifically refers to a via located in the area where the first protrusion 312 is located, connecting the first protrusion 312 and the shielding electrode 402.

[0061] It should be noted that, in the first direction X1, the width of the first slit S1 may be smaller than the width of the signal line 201, or may be greater than or equal to the width of the signal line 201. Figure 5 and Figure 8 In the figure, the case where the width of the first slit S1 is smaller than the width of the signal line 201 is taken as an example.

[0062] In some embodiments of the present disclosure, referring to Figure 4 , Figure 5 and Figure 8, a plurality of pixel electrodes 401 are arranged in an array along a first direction X1 and a second direction X2 to form a plurality of pixel electrode rows H1 arranged at intervals in the second direction X2 and a plurality of pixel electrode columns L1 arranged at intervals in the first direction X1. The first direction X1 and the second direction X2 intersect. The third conductive layer 40 includes a second slit S2 extending along the first direction X1, and the second slit S2 is located between two adjacent pixel electrode rows H1. The third conductive layer 40 includes a plurality of third slits S3, and the plurality of third slits S3 are respectively located between two adjacent pixel electrode columns L1. The orthographic projection of the first via 501 on the substrate 10 is located within the orthographic projection of the intersection region of the second slit S2 and the third slit S3 on the substrate 10. That is, the first via 501 can be located at the gap between four pixel electrodes 401 in two adjacent rows and two adjacent columns (i.e., at the vertex angle of the pixel electrode 401). The gap here is larger than the gap between two adjacent pixel electrodes 401. Therefore, a first via 501 with a larger size or a plurality of first vias 501 can be formed to realize the electrical connection between the shielding electrode 402 and the common electrode 301. In other embodiments, the first via 501 can also be provided at the gap between two adjacent pixel electrodes 401 in the first direction X1 (i.e., at the edge of the pixel electrode 401). The embodiments of the present disclosure are not limited thereto.

[0063] It should be noted that Figure 4 only one common electrode 301 corresponding to two rows and three columns of pixel electrodes 401 (i.e., 6 pixel electrodes 401) is taken as an example for illustration. Further, one common electrode 301 can correspond to n rows and m columns of pixel electrodes 401 (i.e., n*m pixel electrodes 401), where n and m are positive integers. When n is greater than or equal to 2, within the region between two adjacent common electrodes 301 in the first direction X1, one shielding electrode 402 or a plurality of shielding electrodes 402 arranged at intervals along the pixel electrode column L1 direction can be provided. That is, a column of pixel electrodes 401 within the region of one common electrode 301 can correspond to one shielding electrode 402 with a longer extension distance (for example, the extension distance is yl), or can correspond to a plurality of shielding electrodes 402 with shorter extension distances (for example, the extension distances are y2, y2 < y1).

[0064] Refer to Figure 7In some embodiments of the present disclosure, the array substrate further includes a light shielding metal layer 11, a buffer layer 12, an active layer 13, a gate insulating layer 14, a fifth conductive layer 15, an interlayer insulating layer 16, a planarization layer 17, and an alignment layer 18. The light shielding metal layer 11 is located between the substrate 10 and the first conductive layer 20, and is used to shield the channel region of the active layer 13. The buffer layer 12 is located between the light shielding metal layer 11 and the first conductive layer 20. The active layer 13 is located between the buffer layer 12 and the first conductive layer 20, and the active layer 13 includes a first pole contact region, a second pole contact region, and a channel region located between the first pole contact region and the second pole contact region. The active layer 13 also includes a first shallowly doped region located between the channel region and the first pole contact region and a second shallowly doped region located between the channel region and the second pole contact region. The material of the active layer 13 may be polysilicon. The gate insulating layer 14 is located between the active layer 13 and the first conductive layer 20. The fifth conductive layer 15 is located between the gate insulating layer 14 and the first conductive layer 20, and the fifth conductive layer 15 includes a first gate 151 and a second gate 152, that is, the array substrate includes two thin film transistors connected in series, the thin film transistor close to the left side (for example, the first thin film transistor) includes the first gate 151, and the thin film transistor close to the right side (for example, the second thin film transistor) includes the second gate 152. The first electrode contact area of ​​the first thin film transistor is electrically connected to the signal line 201 through a via hole, the second electrode contact area of ​​the first thin film transistor is connected to the first electrode contact area of ​​the second thin film transistor, and the second electrode contact area of ​​the second thin film transistor is electrically connected to the source / drain 203 through a via hole.

[0065] In some embodiments, the second electrode contact region of the second thin film transistor is, for example, a drain contact region. By providing a second shallowly doped region between the channel region and the drain contact region, the electric field strength between the drain and the source can be reduced to avoid the drain induced barrier lowering (DIBL) effect. The first electrode contact region of the second thin film transistor is, for example, a source contact region. By providing a first shallowly doped region between the channel region and the source contact region, the influence of interface traps can be reduced, thereby improving the reliability and stability of the device.

[0066] Continue to refer to Figure 7 The interlayer insulating layer 16 is located between the fifth conductive layer 15 and the first conductive layer 20. The planarization layer 17 is located between the first conductive layer 20 and the second conductive layer 30. The alignment layer 18 is located on the side of the third conductive layer 40 away from the substrate 10. The alignment layer 18 can be a polyimide film (PI film for short) for guiding the liquid crystal molecules to be arranged in a specific direction, thereby achieving an orderly rotation and orientation effect of the liquid crystal material.

[0067] Reference Figure 4 and Fig. 9 In some embodiments of the present disclosure, the first slit S1 includes a first sub-slit S11 and a second sub-slit S12, the first sub-slit S11 being the portion of the first slit S1 located in the intersection area of ​​the second slit S2 and the third slit S3 (i.e., at the top corner of the pixel electrode 401), and the second sub-slit S12 being the portion of the first slit S1 located between two adjacent pixel electrodes 401 in the first direction X1 (i.e., at the edge of the pixel electrode 401). The orthographic projection of the shielding electrode 402 on the first conductive layer 20 at least partially overlaps with the first part of the signal line 201, and the first part of the signal line 201 is located within the orthographic projection of the first sub-slit S11 on the first conductive layer 20, that is, in the area where the first sub-slit S11 is located, the shielding electrode 402 at least covers a portion of the signal line 201; and / or, the orthographic projection of the shielding electrode 402 on the first conductive layer 20 covers the second part of the signal line 201, and the second part of the signal line 201 is located within the orthographic projection of the second sub-slit S12 on the first conductive layer 20, that is, in the area where the second sub-slit S12 is located, the shielding electrode 402 covers the entire signal line 201.

[0068] It is understandable that, since the signal line 201 located in the area where the first sub-slit S11 is located does not affect the light emission, the shielding electrode 402 may only cover part of the signal line 201 in the area where the first sub-slit S11 is located, or may cover all of the signal line 201. However, the signal line 201 located in the area where the second sub-slit S12 is located will generate crosstalk with the pixel electrode 401, so in the area where the second sub-slit S12 is located, the shielding electrode 402 needs to cover all of the signal line 201, thereby reducing the capacitive coupling between the signal line 201 and the pixel electrode 401 and reducing the risk of crosstalk.

[0069] Reference Figure 4 and Fig.10 In some embodiments of the present disclosure, the orthographic projections of the plurality of signal lines 201 on the substrate 10 overlap at least partially with the orthographic projections of the plurality of third slits S3 on the substrate 10, that is, the signal line 201 is located in the region between two adjacent pixel electrode columns L1 in the first direction X1. The third conductive layer 40 includes at least one first slit group G1 (such as Fig.10As shown in the figure, the first slit group G1 includes at least one third slit S3. In the region where each third slit S3 of the first slit group G1 is located, the orthographic projection of the first slit S1 on the substrate 10 at least partially overlaps with the orthographic projection of the third slit S3 in the first slit group G1 on the substrate 10, and the orthographic projection of the shielding electrode 402 on the substrate 10 at least partially overlaps with the orthographic projection of the third slit S3 in the first slit group G1 on the substrate 10, that is, the third slits S3 that overlap with the orthographic projection of the first slit S1 on the third conductive layer 40 constitute the first slit group G1, and the orthographic projection of the third slit S3 in the first slit group G1 on the substrate 10 at least partially overlaps with the orthographic projection of the shielding electrode 402 on the substrate 10.

[0070] Continue to refer to Figure 4 and Fig.10 In some embodiments of the present disclosure, the third conductive layer 40 includes at least one second slit group G2, and the second slit group G2 includes at least one third slit S3. In the region where each third slit S3 of the second slit group G2 is located, the orthographic projection of the common electrode 301 on the substrate 10 overlaps with the orthographic projection of the signal line 201 on the substrate 10 at least partially, that is, the third slits S3 that overlap with the orthographic projection of the signal line 201 on the third conductive layer 40 located in the region where the common electrode 301 is located constitute the second slit group G2; and / or, the orthographic projection of the first slit S1 on the substrate 10 and the orthographic projection of the third slit S3 in the second slit group G2 on the substrate 10 are arranged alternately in the first direction X1, and the orthographic projection of the shielding electrode 402 on the substrate 10 and the orthographic projection of the third slit S3 in the second slit group G2 on the substrate 10 are arranged alternately in the first direction X1, that is, the shielding electrode 402 is not provided in the region where the third slit S3 in the second slit group G2 is located.

[0071] Continue to refer to Figure 4 In some embodiments of the present disclosure, the plurality of pixel electrodes 401 include a first pixel electrode 41 and a second pixel electrode 42, the first pixel electrode 41 and the second pixel electrode 42 are respectively located in adjacent pixel electrode rows H1, the first pixel electrode 41 extends along a third direction X3, the second pixel electrode 42 extends along a fourth direction X4, the third direction X3 intersects with the first direction X1 and the second direction X2, respectively, and the fourth direction X4 intersects with the first direction X1, the second direction X2 and the third direction X3, respectively; a portion of the shielding electrode 402 adjacent to the first pixel electrode 41 extends along the third direction X3, and a portion of the shielding electrode 402 adjacent to the second pixel electrode 42 extends along the fourth direction X4.

[0072] Fig.11 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0073] Reference Fig.11In some embodiments of the present disclosure, the third conductive layer 40 includes at least one third slit group G3, and the third slit group G3 includes at least one third slit S3. In the region where each third slit S3 of the third slit group G3 is located, the orthographic projection of the common electrode 301 on the substrate 10 at least partially overlaps with the orthographic projection of the signal line 201 on the substrate 10, that is, the third slit S3 that overlaps with the orthographic projection of the signal line 201 on the third conductive layer 40 located in the region where the common electrode 301 is located constitutes the third slit group G3; and / or, the orthographic projection of the first slit S1 on the substrate 10 and the orthographic projection of the third slit S3 in the third slit group G3 on the substrate 10 are arranged alternately in the first direction X1, and the orthographic projection of the shielding electrode 402 on the substrate 10 and the orthographic projection of the third slit S3 in the third slit group G3 on the substrate 10 at least partially overlap, that is, the shielding electrode 402 is provided in the region where the third slit S3 in the third slit group G3 is located.

[0074] It should be noted that, in conjunction with the reference Figure 4 and Fig.11 , three pixel electrodes 401 arranged in sequence along the first direction X1 correspond to three sub-pixels, for example, red sub-pixels, green sub-pixels and blue sub-pixels. The red sub-pixels, green sub-pixels and blue sub-pixels are combined into one pixel, and the upper and lower pixels share one common electrode 301, but the embodiments of the present disclosure are not limited thereto. Figure 4 In the embodiment, the shielding electrode 402 is only disposed between adjacent pixels in the first direction X1, specifically, between the red sub-pixel and the blue sub-pixel. Fig.11 , the number of shielding electrodes 402 is reduced, the transmittance is higher, and the risk of short circuit or open circuit of shielding electrode 402 is reduced. Fig.11 In the embodiment, the shielding electrode 402 is disposed between adjacent sub-pixels in the first direction X1. Figure 4 , it can be avoided that the shielding electrode 402 is only set between the red sub-pixel and the blue sub-pixel, and the different luminous brightness between the sub-pixels due to the different sizes of the conductive parts of the red sub-pixel and the blue sub-pixel regions and the conductive parts of the green sub-pixel region can be avoided.

[0075] It should be noted that Fig.11 In the figure, the third slit group G3 includes two third slits S3 as an example. In other embodiments, the third slit group G3 may also include only one third slit S3, that is, the third slit group G3 only includes the third slit S3 located between the adjacent red sub-pixel and the green sub-pixel in the first direction X1 or between the adjacent green sub-pixel and the blue sub-pixel in the first direction X1. Compared with Figure 4 The structure has better brightness uniformity; compared with Fig.11 The structure has a higher transmittance.

[0076] It should be noted that the shielding electrode 402 located between two adjacent common electrodes 301 in the first direction X1 is electrically connected to the first protrusion 312 of the first common electrode 31 through the first via hole 501 (eg, Figure 5 The shielding electrode 402 located in the area where the common electrode 301 is located is directly electrically connected to the first electrode main body 311 or the second electrode main body 321 through the via hole on the first insulating layer 50 (as shown in FIG. Fig.11 shown).

[0077] In some embodiments of the present disclosure, in the first direction X1, a shielding electrode 402 is provided every at least one pixel electrode column L1. Fig.11 As shown, the third conductive layer 40 includes a plurality of shielding electrodes 402 , which are alternately arranged with a plurality of pixel electrode columns L1 in the first direction X1 , that is, a shielding electrode 402 is disposed at every other pixel electrode column L1 , but the embodiments of the present disclosure are not limited thereto.

[0078] Fig.12 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0079] Combined with reference Fig.11 and Fig.12 In some embodiments of the present disclosure, in the first direction X1, a first gap S1 is provided every at least one pixel electrode column L1. Fig.11 As shown, a first gap S1 is provided every three pixel electrode columns L1; Fig.12 As shown, a first gap S1 is provided every other pixel electrode column L1. Fig.11 The six sub-pixels in the embodiment share a common electrode 301. Fig.12 The two sub-pixels in the embodiment share a common electrode 301.

[0080] Understandably, Fig.11 The common electrode block of the second conductive layer 30 is compared with Fig.12 Therefore, fewer touch wirings 202 can be provided. Fig.12 A first gap S1 is further provided between every two adjacent sub-pixels in the first direction X1, so that the surrounding environment of each sub-pixel is completely identical and completely symmetrical, further improving the brightness uniformity between the sub-pixels and reducing the crosstalk between different sub-pixels and the differences in other electrical or optical characteristics.

[0081] Fig.13 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0082] Reference Fig.13 , the pixel electrode 401 includes a first electrode portion 4011, a second electrode portion 4012 and a connecting portion 4013, the first electrode portion 4011 extends along a third direction X3, the second electrode portion 4012 extends along a fourth direction X4, the third direction X3 intersects with the fourth direction X4, and the connecting portion 4013 is used to connect the first electrode portion 4011 and the second electrode portion 4012. The portion of the shielding electrode 402 adjacent to the first electrode portion 4011 extends along the third direction X3, and the portion of the shielding electrode 402 adjacent to the second electrode portion 4012 extends along the fourth direction X4. In the first direction X1, the portion of the shielding electrode 402 adjacent to the connecting portion 4013 protrudes toward the same side as the connecting portion 4013, exemplarily, as Fig.13 As shown, the portion of the shielding electrode 402 adjacent to the connecting portion 4013 protrudes toward the left side (i.e., the opposite direction of the first direction X1) together with the connecting portion 4013. In other embodiments, the portion of the shielding electrode 402 adjacent to the connecting portion 4013 may also protrude toward the right side (i.e., the first direction X1) together with the connecting portion 4013.

[0083] It should be noted that the third direction X3 and the fourth direction X4 have a preset angle, and the preset angle is configured to enable the first electrode portion 4011 and the common electrode 301 to form a first domain electric field, and the second electrode portion 4012 and the common electrode 301 to form a second domain electric field, and the directions of the first domain electric field and the second domain electric field are different. In the embodiment of the present disclosure, the preset angle can be determined according to actual needs and is not limited here.

[0084] It can be understood that in the embodiment of the present disclosure, by providing the connecting portion 4013 between the first electrode portion 4011 and the second electrode portion 4012 , the pixel electrode 401 can be bent better, thereby preventing the electrical performance of the bent portion of the pixel electrode 401 from being affected.

[0085] In some embodiments of the present disclosure, in the first direction X1, the distances between the shielding electrode 402 and two adjacent pixel electrodes 401 are equal. Fig.13 As shown, the spacing d1 between the shielding electrode 402 and the pixel electrode 401 on the left (i.e., the pixel electrode 401 adjacent in the opposite direction of the first direction X1) is equal to the spacing d2 between the shielding electrode 402 and the pixel electrode 401 on the right (i.e., the pixel electrode 401 adjacent in the first direction X1).

[0086] Fig.14 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. Fig.15 yes Fig.14 A magnified view of the P3 region.

[0087] Reference Fig.14 and Fig.15 In some embodiments of the present disclosure, the pixel electrode 401 includes a pixel electrode main body 431 and a second protrusion 432, the shielding electrode 402 includes a shielding electrode main body 4021 and a second groove 4022 (i.e., a avoidance structure corresponding to the second protrusion 432), the second protrusion 432 protrudes from the pixel electrode main body 431 in a direction toward the shielding electrode 402, and the second groove 4022 is recessed from the shielding electrode main body 4021 in a direction away from the second protrusion 432. The protruding directions of the second protrusions 432 in the same pixel electrode row H1 are the same, and the protruding directions of the second protrusions 432 in two adjacent pixel electrode rows H1 are opposite, but the embodiments of the present disclosure are not limited thereto.

[0088] It should be noted that in the related art, the uneven brightness phenomenon caused by pressing or sliding on the LCD panel is called Trace Mura, which is manifested as a dark mark left at the pressing position. The principle of its generation is mainly due to the deformation of liquid crystal molecules when they are pressed or slid under high grayscale voltage, resulting in uneven arrangement of liquid crystal molecules, thereby forming uneven brightness marks on the LCD panel. In this embodiment, by making the pixel electrode 401 include the second protrusion 432, the size of the lateral electric field weakening area between the common electrode 301 is effectively reduced, so that the lateral electric field can enhance the orientation ability of the liquid crystal molecules, and the electric field distribution in the pixel opening area can be made more orderly, which is conducive to improving Trace Mura and improving the display effect of the LCD panel.

[0089] In some embodiments, in the first direction X1, the spacing between the second protrusion 432 and the shielding electrode 402 is greater than or equal to 2 microns and less than or equal to 3 microns, which can avoid short circuit between the second protrusion 432 and the shielding electrode 402. In some embodiments, in the first direction X1, the width of the portion of the shielding electrode 402 provided with the second groove 4022 is greater than or equal to 2 microns and less than or equal to 3 microns, which can avoid the shielding electrode 402 from being broken. In this embodiment, the portion of the shielding electrode 402 without the second groove 4022 can be electrically connected to the common electrode 301 through the first via 501, thereby achieving capacitive coupling between the shielding signal line 201 and the pixel electrode 401 while avoiding the second protrusion 432 of the pixel electrode 401.

[0090] Fig.16 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. Fig.17 yes Fig.16 Magnified view of the P4 region.

[0091] Reference Fig.16 and Fig.17In some embodiments of the present disclosure, the common electrode 301 is reused as a touch electrode. The first conductive layer 20 also includes a plurality of touch lines 202 spaced apart along the first direction X1, that is, the touch lines 202 can be arranged in the same layer as the signal lines 201. The touch lines 202 are electrically connected to the common electrodes 301, that is, the plurality of common electrodes 301 are electrically connected to the driving chip through the touch lines 202, respectively. The orthographic projection of the touch lines 202 on the substrate 10 at least partially overlaps with the orthographic projection of the shielding electrode 402 on the substrate 10, that is, the touch lines 202 can be arranged in the area between two adjacent pixel electrodes 401 in the first direction X1.

[0092] Fig.18 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. Fig.19 yes Fig.18 Magnified view of the P5 region. Fig. 20 is along Fig.19 Cross-sectional view along the A-A' direction. Fig.21 is a schematic diagram of film layer stacking of an array substrate according to some embodiments of the present disclosure.

[0093] Reference Figures 18 to 21 In some embodiments of the present disclosure, the common electrode 301 is reused as a touch electrode. The array substrate further includes a fourth conductive layer 60, which is located between the first conductive layer 20 and the second conductive layer 30. The fourth conductive layer 60 includes a plurality of touch traces 202 spaced apart along the first direction X1, and the touch traces 202 are electrically connected to the common electrode 301. The orthographic projection of the touch trace 202 on the substrate 10 at least partially overlaps with the orthographic projection of the signal line 201 on the substrate 10; and / or, the orthographic projection of the touch trace 202 on the substrate 10 at least partially overlaps with the orthographic projection of the shielding electrode 402 on the substrate 10; and / or, the orthographic projection of the touch trace 202 on the substrate 10 at least partially overlaps with the orthographic projection of the first slit S1 on the substrate 10.

[0094] It is understandable that in this embodiment, the touch line 202 and the signal line 201 are arranged in different layers, and an additional mask is required to separately make the pattern of the touch line 202. By making the orthographic projection of the touch line 202 on the substrate 10 overlap with the orthographic projection of the signal line 201 on the substrate 10 at least partially, the aperture ratio of the pixel can be improved.

[0095] In some embodiments, in the first direction X1, the width of the touch line 202 is smaller than the width of the signal line 201, so the touch line 202 cannot completely block the signal line 201. In this embodiment, by setting the shielding electrode 402 above the touch line 202 (i.e., on the side away from the signal line 201), the capacitive coupling between the signal line 201 and the pixel electrode 401 can be better shielded to reduce the risk of crosstalk. In other embodiments, the width of the touch line 202 can also be made greater than the width of the signal line 201, so as to completely block the signal line 201 and shield the capacitive coupling between the signal line 201 and the pixel electrode 401, but the aperture ratio of the pixel will be reduced. In this embodiment, the shielding electrode 402 can be made of a transparent material to avoid affecting the aperture ratio of the pixel.

[0096] In some embodiments of the present disclosure, referring to Fig. 20 and Fig.21 , the array substrate includes a first insulating layer 50 and a second insulating layer 70, the first insulating layer 50 is located between the second conductive layer 30 and the third conductive layer 40, and the second insulating layer 70 is located between the second conductive layer 30 and the fourth conductive layer 60. The array substrate includes a first via hole 501 and a second via hole 701, the first via hole 501 penetrates the first insulating layer 50, and the second via hole 701 penetrates the first insulating layer 50 and the second insulating layer 70. The shielding electrode 402 is electrically connected to the common electrode 301 through the first via hole 501, and the shielding electrode 402 is electrically connected to the touch wiring 202 through the second via hole 701. That is, the touch wiring 202 is electrically connected to the shielding electrode 402, and then electrically connected to the common electrode 301 through the shielding electrode 402. In this embodiment, the first via hole 501 and the second via hole 701 can be formed by the same etching process, so that the process takt can be saved.

[0097] The present disclosure also provides a display panel, including the array substrate as described above. For a detailed structure of the array substrate, please refer to Figures 4 to 21 And related instructions will not be repeated here.

[0098] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, characterized in that: The array substrate comprises: substrate; A first conductive layer, located at one side of the substrate, the first conductive layer comprising a plurality of signal lines spaced apart along a first direction; a second conductive layer, located on a side of the first conductive layer away from the substrate, the second conductive layer comprising a plurality of common electrodes; and A third conductive layer, located on a side of the second conductive layer away from the substrate, the third conductive layer comprising a plurality of pixel electrodes; Wherein, the second conductive layer further comprises a first slit, the first slit is located between at least two common electrodes adjacent to each other in the first direction, and the orthographic projection of the signal line on the substrate at least partially overlaps with the orthographic projection of the first slit on the substrate; The third conductive layer also includes a shielding electrode, which is connected to a fixed voltage signal, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes: at least one first insulating layer located between the second conductive layer and the third conductive layer, the at least one first insulating layer includes a first via hole, and the shielding electrode is electrically connected to the common electrode through the first via hole.

3. The array substrate according to claim 2, characterized in that: The plurality of common electrodes include a first common electrode and a second common electrode, and the first common electrode and the second common electrode are respectively located at two sides of the first slit in the first direction; The first common electrode includes a first electrode body and a first protrusion, and the second common electrode includes a second electrode body and a first groove, wherein the first protrusion protrudes from the first electrode body in a direction toward the second common electrode, and the first groove is recessed from the second electrode body in a direction away from the first common electrode; as well as An orthographic projection of the shielding electrode on the substrate at least partially overlaps with an orthographic projection of the first protrusion on the substrate.

4. The array substrate according to claim 3, characterized in that: An orthographic projection of the first protrusion on the substrate covers an orthographic projection of the first via on the substrate.

5. The array substrate according to claim 4, characterized in that: The plurality of pixel electrodes are arranged in an array along the first direction and the second direction to form a plurality of pixel electrode rows arranged at intervals in the second direction and a plurality of pixel electrode columns arranged at intervals in the first direction, and the first direction and the second direction intersect; The third conductive layer comprises a second slit extending along the first direction, and the second slit is located between two adjacent pixel electrode rows; The third conductive layer comprises a plurality of third slits, and the plurality of third slits are respectively located between two adjacent pixel electrode columns; as well as The orthographic projection of the first via hole on the substrate is located within the orthographic projection of an intersection area of ​​the second slit and the third slit on the substrate.

6. The array substrate according to claim 5, characterized in that: The first slit includes a first sub-slit and a second sub-slit, the first sub-slit is a portion of the first slit located in the intersection area, and the second sub-slit is a portion of the first slit located between two adjacent pixel electrodes in the first direction; as well as The orthographic projection of the shielding electrode on the first conductive layer at least partially overlaps with the first portion of the signal line, and the first portion of the signal line is located within the orthographic projection of the first sub-slot on the first conductive layer, and / or the orthographic projection of the shielding electrode on the first conductive layer covers the second portion of the signal line, and the second portion of the signal line is located within the orthographic projection of the second sub-slot on the first conductive layer.

7. The array substrate according to claim 5, characterized in that: The orthographic projections of the plurality of signal lines on the substrate at least partially overlap with the orthographic projections of the plurality of third slits on the substrate respectively; The third conductive layer includes at least one first slit group, and the first slit group includes at least one third slit; and In the area where each third slit of the first slit group is located, the orthographic projection of the first slit on the substrate at least partially overlaps with the orthographic projection of the third slit in the first slit group on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the third slit in the first slit group on the substrate.

8. The array substrate according to claim 7, characterized in that: The third conductive layer includes at least one second slit group, and the second slit group includes at least one third slit; as well as In the region where each third slit of the second slit group is located, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; And / or, the orthographic projection of the first slit on the substrate and the orthographic projection of the third slit in the second slit group on the substrate are arranged at intervals in the first direction, and the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the third slit in the second slit group on the substrate are arranged at intervals in the first direction.

9. The array substrate according to claim 7, characterized in that: The third conductive layer includes at least one third slit group, and the third slit group includes at least one third slit; and In the region where each third slit of the third slit group is located, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; And / or, the orthographic projection of the first slit on the substrate and the orthographic projection of the third slit in the third slit group on the substrate are arranged at intervals in the first direction, and the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the third slit in the third slit group on the substrate at least partially overlap.

10. The array substrate according to claim 5, characterized in that: The third conductive layer includes a plurality of shielding electrodes, and the plurality of shielding electrodes and a plurality of pixel electrode columns are alternately arranged in the first direction.

11. The array substrate according to claim 5, characterized in that: In the first direction, one shielding electrode is disposed every at least one pixel electrode column; and / or In the first direction, one first gap is arranged every at least one pixel electrode column.

12. The array substrate according to claim 5, characterized in that: The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode, the first pixel electrode and the second pixel electrode are respectively located in adjacent pixel electrode rows, the first pixel electrode extends along a third direction, the second pixel electrode extends along a fourth direction, the third direction intersects the first direction and the second direction respectively, and the fourth direction intersects the first direction, the second direction and the third direction respectively; A portion of the shielding electrode adjacent to the first pixel electrode extends along the third direction, and a portion of the shielding electrode adjacent to the second pixel electrode extends along the fourth direction; or The pixel electrode includes a first electrode portion, a second electrode portion and a connecting portion, the first electrode portion extends along a third direction, the second electrode portion extends along a fourth direction, the third direction intersects with the fourth direction, and the connecting portion is used to connect the first electrode portion and the second electrode portion; a portion of the shielding electrode adjacent to the first electrode portion extends along the third direction, a portion of the shielding electrode adjacent to the second electrode portion extends along the fourth direction, and in the first direction, a portion of the shielding electrode adjacent to the connecting portion protrudes toward the same side as the connecting portion.

13. The array substrate according to claim 12, characterized in that: In the first direction, the shielding electrode is spaced equal to the distance between two adjacent pixel electrodes.

14. The array substrate according to claim 5, characterized in that: The pixel electrode comprises a pixel electrode main body and a second protrusion, the shielding electrode comprises a shielding electrode main body and a second groove, the second protrusion protrudes from the pixel electrode main body in a direction toward the shielding electrode, and the second groove is recessed from the shielding electrode main body in a direction away from the second protrusion; as well as The second protrusions in the same pixel electrode row have the same protruding direction, and the second protrusions in two adjacent pixel electrode rows have opposite protruding directions.

15. The array substrate according to claim 1, characterized in that: The common electrodes are reused as touch electrodes; the first conductive layer further comprises a plurality of touch wirings spaced apart along the first direction, the touch wirings being electrically connected to the common electrodes; and The orthographic projection of the touch line on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate, or the orthographic projection of the touch line on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate.

16. The array substrate according to claim 1, characterized in that: The common electrode is reused as a touch electrode; the array substrate further includes a fourth conductive layer, the fourth conductive layer is located between the first conductive layer and the second conductive layer, the fourth conductive layer includes a plurality of touch traces arranged at intervals along the first direction, and the touch traces are electrically connected to the common electrode; and The orthographic projection of the touch control trace on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; And / or, the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate; And / or, an orthographic projection of the touch trace on the substrate at least partially overlaps with an orthographic projection of the first gap on the substrate.

17. The array substrate according to claim 16, characterized in that: The array substrate comprises a first insulating layer and a second insulating layer, the first insulating layer is located between the second conductive layer and the third conductive layer, and the second insulating layer is located between the second conductive layer and the fourth conductive layer; The array substrate comprises a first via hole and a second via hole, the first via hole passes through the first insulating layer, and the second via hole passes through the first insulating layer and the second insulating layer; as well as The shielding electrode is electrically connected to the common electrode through the first via hole, and the shielding electrode is electrically connected to the touch control trace through the second via hole.

18. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1-17.

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