Novel integrated circuit exposure method

Abstract

The invention discloses a novel integrated circuit exposure method, which belongs to the technical field of integrated circuit exposure, and comprises the following steps: confirming carved number information including position, shape and size; according to the confirmed information, setting the WEE exposure mode, the position of the engraved number, the size of the engraved number and the energy for shielding the engraved number in the photoetching machine; wEE exposure is carried out on the number carving area; and performing normal whole-surface exposure on the wafer. According to the method, a mode of WEE shielding number etching of a photoetching machine is adopted, the requirement for number etching shielding of any position and any shape can be met, the size can be controlled, effective chips cannot be affected, a photomask does not need to be additionally manufactured, two exposure processes are reduced, the cost is saved, and the productivity is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit exposure, and in particular relates to a novel integrated circuit exposure method. Background Art

[0002] In the chip manufacturing process, the chip fab needs to mark the chip ID at a specific location on the wafer as an identification mark in the subsequent packaging and testing process, so that the machine in the subsequent process can read and identify it through OCR technology. However, due to the characteristics of chip bump packaging, if special treatment is not taken, a bump pattern will grow where the chip ID is located, making the chip ID unreadable and causing chip identification failure. Therefore, special measures must be taken for the engraved area during the photolithography process to avoid the growth of bumps to ensure the readability of the engraved area.

[0003] Currently, wafer factories usually place the engraved mark in the inactive die area of ​​the wafer, and the industry's bump packaging mostly uses negative photoresist. To cover the engraved mark, the conventional practice is to design a blank mask and perform a secondary exposure on the engraved mark area so that there is no window in the area, so that no bump grows, and the engraved mark can be recognized by the machine. The specific steps are as follows:

[0004] First, normal exposure is performed on the entire wafer;

[0005] Next, use a blank mask to perform a second exposure on the area where the engraved mark is located.

[0006] However, this traditional method has many disadvantages: on the one hand, it is difficult to accurately calculate the position of the engraved area and use complex coordinate conversion to ensure that the blank mask used for secondary exposure can accurately cover the engraved area without affecting the valid chips nearby; on the other hand, the special production of specific masks will increase production costs; in addition, if there are valid chips near the engraved area, this method will easily block some of the valid chips, making it impossible for them to grow bumps, which will ultimately damage the yield. Summary of the invention

[0007] In view of the above situation, in order to overcome the defects of the prior art, the method of the present invention can accurately, efficiently and cost-effectively solve the many problems faced by the chip engraving area during the photolithography process, ensure the readability of the chip ID, and improve the overall efficiency of chip manufacturing.

[0008] In order to achieve the above object, the following technical solution is adopted: The present invention provides a novel integrated circuit exposure method, comprising the following steps:

[0009] Confirm the engraving information, including position, shape, and size;

[0010] According to the confirmed information, the WEE exposure mode, the position of the mark, the size of the mark and the energy of masking the mark are set in the lithography machine;

[0011] Perform WEE exposure on the engraved area;

[0012] The wafer is exposed on the entire surface normally.

[0013] Furthermore, the normal markings in the marking information are in the four directions of up, down, left, and right of the wafer, and are centered at four angles, and are in the shape of a straight line;

[0014] In addition to the gas areas in the horizontal and vertical directions, there are marks at special positions in the shape of an arc.

[0015] Furthermore, the marking information is provided by the wafer factory. If the wafer factory does not provide the marking information, it can be confirmed by measuring with a tool microscope.

[0016] Furthermore, if the shape of the engraved mark is a straight line, the exposure mode of the photolithography machine is set to be linear;

[0017] If the shape is an arc, the exposure mode of the photolithography machine is set to an arc.

[0018] Furthermore, the size of the mark in the lithography machine includes length and width, and both the length and width diffuse to the four sides with the center area of ​​the mark as the zero point. When actually setting the size, the error caused by the light spot affecting the lithography machine is added.

[0019] Furthermore, the energy for masking the markings in the photolithography machine is set according to the thickness of the photoresist, and the exposure of the photoresist is ensured.

[0020] The beneficial effects of the present invention are as follows: the present invention adopts the method of masking the markings by the lithography machine WEE, which can meet the requirements of masking the markings of any shape and position, and the size can be controlled without affecting the effective chip. There is no need to make additional masks, reducing the second exposure process, saving costs and improving production capacity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 The present invention is a flow chart of a novel integrated circuit exposure method.

[0022] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0024] Unless otherwise defined, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein may be applied to the present invention. The preferred implementation methods and materials described herein are for demonstration purposes only and are not intended to limit the content of this application.

[0025] The experimental methods in the following examples are conventional methods unless otherwise specified, and the experimental materials used in the following examples are purchased from commercial channels unless otherwise specified.

[0026] Example

[0027] Combined with Figure 1 , an embodiment of the present invention: a novel integrated circuit exposure method

[0028] In the process of integrated circuit manufacturing, chip fabs need to mark chip IDs at specific locations on the wafers in order to facilitate accurate identification of chips in subsequent packaging and testing processes. Accurate knowledge of marking information is the basis for the accurate implementation of the entire exposure method, which covers key elements such as position, shape, and size.

[0029] As for the acquisition of engraving information, usually, the engraving information is provided by the wafer factory. This is because the wafer factory has already clearly defined the location of the chip ID and other related settings during the chip design and early planning stages. It will record and transmit this information according to the established production process and process requirements so that subsequent processes such as photolithography can accurately know the engraving related information.

[0030] However, in actual production scenarios, there are also cases where the wafer factory does not provide the marking information. At this time, it is necessary to use a tool microscope for measurement and confirmation. The tool microscope has high-precision observation and measurement functions, and can observe the surface of the wafer in detail. Through its measurement function, it can accurately determine the specific position coordinates of the mark on the wafer, and clearly distinguish the shape of the mark (such as a straight line or an arc, etc.), and can also accurately measure its size, thereby making up for the loss caused by the wafer factory’s failure to provide information and ensuring that subsequent operations can be carried out smoothly.

[0031] Judging from the distribution of the marks on the wafer, the normal marks in the mark information are in the four directions of the wafer, up, down, left, right, and center at four angles, and are in the shape of a straight line. This is a relatively common and regular distribution form. In previous lithography practices, this kind of regularly distributed marks still face many challenges when performing exposure processing and other operations if traditional methods are used. For example, when traditional secondary exposure uses a blank mask to cover the marks, in order to accurately correspond to these straight-line shapes and marks in a specific direction, complex coordinate conversion and other operations are required, which is easy to cause deviations, thereby affecting the effective chip or causing the marks to be unable to be accurately recognized by the machine.

[0032] Except for the gas areas in the horizontal and vertical directions, the marks in special positions are arc-shaped. Compared with straight-line marks, arc-shaped marks are more difficult to handle during the photolithography process. It is difficult for traditional methods to adapt to their irregular shapes for precise masking. It is often easy to have incomplete masking or excessive masking that affects the surrounding effective chips. In addition, the production of corresponding masks also faces higher costs and precision challenges.

[0033] According to the confirmed information, set the WEE exposure method, the position of the mark, the size of the mark and the energy of the masking mark in the lithography machine.

[0034] After obtaining accurate engraving information, a series of key parameters must be set in the lithography machine based on this information.

[0035] If the shape of the mark is a straight line, the exposure mode of the lithography machine is set to linear. This is because the characteristics of the straight-line-shaped marks conform to the law of linear exposure. Through the linear exposure method, the corresponding processing can be evenly performed along the direction of the marks, ensuring that while shielding the marks, the adverse effects on the surrounding effective chips can be avoided to the greatest extent. In traditional exposure methods, for straight-line marks, it may be more likely to be shielded by performing secondary exposure through a fixed-shape mask, but there are problems such as high mask production cost and difficult positioning. The linear exposure method of the present invention utilizes the functional characteristics of the lithography machine itself, which can be more flexible and accurate.

[0036] If the shape is an arc, the exposure mode of the photolithography machine is set to an arc. Due to the curved shape characteristics of the arc marking, a matching arc exposure mode is required to fit its contour to achieve precise masking operations. In the past, it was difficult to achieve precise coverage of arc markings using traditional exposure methods. Either part of the marking area would be missed, causing subsequent bump growth to affect the marking reading, or the effective chip area would be mistakenly covered, causing the chip yield to drop. The arc exposure setting of the present invention can effectively overcome these problems.

[0037] The size of the mark in the photolithography machine includes length and width, and both length and width spread out to the four sides with the center area of ​​the mark as the zero point. When actually setting the size, it is necessary to add the error caused by the light spot affecting the photolithography machine. This is because in the actual operation of the photolithography machine, the characteristics of the light spot will have a certain impact on the exposure range. If this error factor is not considered, the set mark size may be inconsistent with the actual exposure effect. Either the shielding is incomplete, so that the mark area may still grow a bump to affect the reading, or it will exceed the expected range and affect the surrounding effective chip area that should not be affected. In traditional exposure technology, the control of the mark size is often not accurate enough, especially in considering these complex influencing factors. The present invention can better achieve accurate control of the mark size by accurately considering the light spot error.

[0038] In addition, the energy for shielding the marks in the photolithography machine is set according to the thickness of the photoresist, and the exposure of the photoresist is ensured. Photoresist plays a key role in the photolithography process, and different thicknesses have different requirements for exposure energy. If the energy is set too low, the photoresist cannot be exposed, and effective shielding of the marks cannot be achieved, and bump growth may cover the marks later; if the energy is set too high, it may have adverse effects such as overexposure on the surrounding photoresists. In terms of energy setting, the previous exposure methods often lack a mechanism for accurate matching based on the thickness of the photoresist, and are prone to a series of problems caused by unreasonable energy. The present invention can better ensure the accurate processing of the mark area and the stability of the entire photolithography process by reasonably setting the energy for shielding the marks based on the thickness of the photoresist.

[0039] After completing the accurate setting of the relevant parameters of the above-mentioned lithography machine, the engraved area is subjected to WEE exposure. The WEE exposure method plays a core role in the present invention. It can accurately process the engraved area according to the various parameters set previously to meet the requirements of engraved masking of any shape and position. Unlike the traditional method of secondary exposure using a blank mask, it does not require additional production of a mask, avoiding the increase in cost and mask accuracy caused by the production of the mask, and through its precise exposure control, it can ensure that it will not affect the effective chip, so that the engraved area can be effectively shielded, laying the foundation for the accurate reading of the subsequent chip ID.

[0040] After completing the WEE exposure of the engraved area, the wafer is then exposed to the entire surface normally. This step is a routine operation in the integrated circuit lithography process, and is intended to expose the other parts of the wafer except the engraved area according to normal lithography requirements so that it can form corresponding circuit graphics and other structures. In the traditional exposure process, the previous secondary exposure and other operations may cause some interference or influence on the normal whole-surface exposure, such as the mask blocking causing abnormal exposure of some areas. The present invention first uses WEE exposure to accurately process the engraved area, and then performs normal whole-surface exposure, which can ensure that the exposure process of the entire wafer is smoother and more accurate, thereby ensuring the overall quality and efficiency of chip manufacturing.

[0041] In summary, the novel integrated circuit exposure method demonstrated in this embodiment, through the above steps and corresponding detailed settings and operations, can accurately, efficiently and cost-effectively solve the many problems faced by the chip engraving area in the photolithography process, ensure the readability of the chip ID, and improve the overall efficiency of chip manufacturing.

[0042] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0043] The present invention and its implementation methods are described above, which is not restrictive. The drawings are only one of the implementation methods of the present invention, and the actual application is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design methods and embodiments similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. A novel integrated circuit exposure method, characterized in that: The following steps are involved: Confirm the engraving information, including position, shape, and size; According to the confirmed information, the WEE exposure mode, the position of the mark, the size of the mark and the energy of masking the mark are set in the lithography machine; Perform WEE exposure on the engraved area; The wafer is exposed on the entire surface normally.

2. The novel integrated circuit exposure method according to claim 1, characterized in that: The normal markings in the marking information are in the four directions of up, down, left, and right of the wafer, with four angles as the center, and are in the shape of a straight line; In addition to the gas areas in the horizontal and vertical directions, there are marks at special positions in the shape of an arc.

3. The novel integrated circuit exposure method according to claim 2, characterized in that: The marking information is provided by the wafer factory. If the wafer factory does not provide the marking information, it can be confirmed by measuring with a tool microscope.

4. The novel integrated circuit exposure method according to claim 3, characterized in that: If the shape of the engraved mark is a straight line, the exposure mode of the photolithography machine is set to linear; If the shape is an arc, the exposure mode of the photolithography machine is set to an arc.

5. The novel integrated circuit exposure method according to claim 4, characterized in that: The size of the mark in the lithography machine includes length and width, and both the length and width spread out to the four sides with the center area of ​​the mark as the zero point. When actually setting the size, the error caused by the light spot affecting the lithography machine is added.

6. The novel integrated circuit exposure method according to claim 5, characterized in that: The energy for masking the markings in the photolithography machine is set according to the thickness of the photoresist, and the exposure of the photoresist is ensured.

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