A contact hole photolithography process condition design method and a semiconductor structure

Abstract

The application provides a contact hole photolithography process condition design method and a semiconductor structure, and the method comprises the following steps: obtaining the front film parameters of a substrate to be coated with an anti-reflection layer, simulating and selecting target film thicknesses of the anti-reflection layer and a photoresist and target exposure anchor points; changing illumination condition parameters to verify a photolithography process, and selecting the target exposure anchor point with the minimum contact hole edge roughness obtained by photolithography as the selected exposure anchor point, and the corresponding illumination condition parameters are the contact hole photolithography process conditions. The illumination condition parameters of the photolithography are iteratively optimized, and the edge roughness of the photolithography contact hole is obviously improved. Meanwhile, the target exposure anchor point is selected through the process window design condition screening before iteration and optimization, so that the improved contact hole meets the process window design condition, and the photolithography process is suitable for high-precision requirements. In addition, the optimal photolithography process conditions of the contact hole corresponding to different processes are obtained in advance, so that the photolithography condition changes caused by process changes can be quickly responded.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a method for designing contact hole photolithography process conditions and a semiconductor structure. Background Technology

[0002] In the back-end processes of advanced process nodes, excessive roughness of the photoresist line edges, line width, and VIA (contact via) edges can cause short circuit defects in metal interconnects. Furthermore, excessive line edge roughness transmitted to the final pattern through etching can prevent subsequent copper material from filling in, thereby reducing the resistance, capacitance, and other performance parameters of the back-end interconnects.

[0003] As process nodes shrink, the requirements for edge roughness in vias (VIAs) become increasingly stringent, making improvements crucial. Current methods for optimizing VIA edge roughness include increasing the concentration of photoacid generators (PAGs), moderately increasing post-exposure baking temperature or time, and chemical trimming (spraying the photolithographic pattern surface with a chemical liquid before development). However, increasing PAG concentration makes the exposure dose more sensitive, leading to a decrease in energy latitude (EL), thus reducing the process window. Increasing post-exposure baking temperature or time is only suitable for photoresists with high deprotection energy during baking, and not for photoresists requiring shorter baking times or lower temperatures, thus limiting its applicability. Chemical trimming is costly and also has limited applications.

[0004] Therefore, there is an urgent need for a structure or method that can reduce the roughness of contact hole edges in the later stages of advanced processes, meet process window conditions, and has a wide range of applications.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a contact hole photolithography process condition design method and semiconductor structure to solve the problem that it is difficult to improve the contact hole edge roughness in the back-end process of advanced processes in the prior art while meeting process window conditions and having a wide range of applications.

[0007] To achieve the above objectives, the present invention provides a method for designing contact hole photolithography process conditions, the method comprising:

[0008] A substrate to be coated with an antireflective layer is provided, the substrate including a substrate and n thin films deposited on the substrate, where n is an integer greater than or equal to 1; the parameters of the front thin film of the substrate to be coated with the antireflective layer are measured and obtained, the parameters of the front thin film include the film thickness and corresponding extinction coefficient of each of the m thin films from the topmost thin film of the substrate, where m is an integer greater than or equal to 1 and less than or equal to n.

[0009] Photolithography simulation is performed using the obtained front thin film parameters to obtain the relationship curve between the simulated film thickness and extinction coefficient of the anti-reflection layer to be coated, and then the target film thickness of the anti-reflection layer to be coated is selected.

[0010] Photolithography simulation is performed based on the parameters of the previous thin film and the target film thickness and extinction coefficient of the anti-reflection layer to be coated, and the simulated film thickness and reflectivity relationship curve of the photoresist set on the anti-reflection layer to be coated is obtained, and then the target film thickness of the photoresist is selected.

[0011] Based on the parameters of the front thin film, the target film thickness and extinction coefficient of the antireflective layer to be coated, and the target film thickness of the photoresist, candidate exposure anchor points are selected, and photolithography simulation is performed by fixing the photolithography parameters to be optimized and the illumination mode parameters to obtain at least one target exposure anchor point.

[0012] On the substrate, by changing the illumination condition parameters, the photolithography process conditions obtained in the aforementioned steps are verified. The target exposure anchor point with the smallest edge roughness of the contact hole obtained by photolithography is selected as the selected exposure anchor point, and the corresponding illumination condition parameters of the selected exposure anchor point are obtained, thereby determining the contact hole photolithography process conditions. The illumination condition parameters include: numerical aperture, relative radius of the outer ring pupil, and relative radius of the inner ring pupil. The photolithography process conditions obtained in the aforementioned steps include: the target film thickness of the antireflective layer to be coated, the target film thickness of the photoresist, the illumination mode parameters, and the at least one target exposure anchor point.

[0013] Optionally, n is greater than or equal to 4, and m is greater than or equal to 4.

[0014] Optionally, the step of selecting the target film thickness of the antireflective layer to be coated further includes:

[0015] Obtain the second minimum point of the simulated film thickness versus extinction coefficient curve of the antireflective layer to be coated;

[0016] The simulated film thickness of the anti-reflective layer to be coated is selected from the second minimum point as the target film thickness of the anti-reflective coating.

[0017] Optionally, the step of obtaining the target film thickness of the photoresist includes at least:

[0018] The parameters of the front thin film and the target film thickness and corresponding extinction coefficient of the anti-reflection coating are input into the photolithography simulation software for simulation to obtain the simulated film thickness and reflectivity relationship curve with photoresist set on the anti-reflection layer to be coated, and at least one minimum point in the curve with an absolute slope value close to 0 is selected.

[0019] Select at least one minimum point where the absolute value of the slope is close to 0 as the simulated film thickness of the photoresist as the target film thickness of the photoresist.

[0020] Optionally, the illumination parameters include the illumination mode of the exposure light source and the polarization state of the exposure light source.

[0021] Optionally, the step of obtaining at least one target exposure anchor point further includes:

[0022] A series of feature images are selected as candidate exposure anchor points;

[0023] Photolithography simulation is performed with fixed lithography parameters and illumination parameters to be optimized, and one or more of the following parameters corresponding to the candidate exposure anchor point are obtained as preset screening parameters: key linewidth, linewidth uniformity parameter, mask error enhancement factor, energy margin or focus depth.

[0024] At least one candidate exposure anchor point among the candidate exposure anchor points whose preset screening parameters satisfy the lithography process window design conditions is selected as the target exposure anchor point.

[0025] Optionally, the series of feature patterns includes: a preset periodic dense pattern, a preset periodic semi-dense pattern, a preset periodic semi-dense pattern with exposure auxiliary patterns added based on preset rules, and / or an isolated pattern in a sparse area.

[0026] Optionally, the step of changing the illumination condition parameters on the substrate further includes:

[0027] Select a set of lighting condition parameters as an initial parameter set, and iterate by changing one or more of the lighting condition parameters based on the initial parameter set.

[0028] When the change in the roughness of the contact hole edge obtained by photolithography is less than the preset change value, the illumination condition parameters obtained at this time are used as the new initial parameter set.

[0029] After iterating a preset number of times, the illumination condition parameters with the minimum contact hole edge roughness are used as the contact hole photolithography process conditions.

[0030] Optionally, the design method further includes:

[0031] Determine whether the edge roughness of the contact hole obtained by photolithography under the illumination condition parameters corresponding to the selected exposure anchor point is higher than the reference threshold.

[0032] If the edge roughness is higher than the reference threshold, the illumination condition parameters are adjusted and the photolithography process is re-verified to obtain a new selected exposure anchor point; if the edge roughness is not higher than the reference threshold, the iteration ends and the illumination condition parameters corresponding to the obtained contact hole edge roughness are output.

[0033] The present invention also provides a semiconductor structure, wherein the semiconductor structure is provided with contact hole photolithography process conditions by using any of the contact hole photolithography process condition design methods described above to obtain the photolithography process conditions for setting contact holes on the semiconductor structure, wherein the semiconductor structure includes a substrate and n thin films deposited on the substrate, where n is an integer greater than or equal to 1.

[0034] As described above, the contact hole photolithography process condition design method and semiconductor structure of the present invention have the following beneficial effects:

[0035] This invention improves the edge roughness of contact holes obtained by photolithography by iteratively optimizing the illumination condition parameters of photolithography, and the improvement effect is significant.

[0036] Before iterative optimization, this invention filters target exposure anchor points by process window design conditions, so that the contact holes with improved edge roughness meet the process window design conditions, and is applicable to photolithography processes of 28nm and below technology nodes.

[0037] This invention, through a contact hole photolithography process condition design method, can rapidly adapt to changes in photolithography conditions caused by photolithography processes corresponding to Tri-layer and Bi-layer structures, ensuring that the edge roughness of the contact hole and the photolithography process window conditions are maintained even when the process is changed. Attached Figure Description

[0038] Figure 1 The flowchart shown is a step 1 of the contact hole photolithography process condition design method in Embodiment 1 of the present invention.

[0039] Figure 2 This is a schematic diagram of the substrate structure in step 1 of the contact hole photolithography process condition design method of Embodiment 1 of the present invention.

[0040] Figure 3 The diagram shown is a schematic representation of a preset periodic dense pattern in step 4 of the contact hole photolithography process condition design method of Embodiment 1 of the present invention.

[0041] Figure 4 The diagram shows a preset periodic semi-dense pattern in step 4 of the contact hole photolithography process condition design method of Embodiment 1 of the present invention.

[0042] Figure 5The diagram shown is a schematic of a preset periodic semi-dense pattern for adding exposure auxiliary patterns based on preset rules in step 4 of the contact hole photolithography process condition design method of Embodiment 1 of the present invention.

[0043] Figure 6 The diagram shows a schematic of an isolated pattern in a sparse region in step 4 of the contact hole photolithography process condition design method of Embodiment 1 of the present invention.

[0044] Figure 7 The diagram shows the structure of the substrate in the contact hole photolithography process condition design method of Embodiment 2 of the present invention.

[0045] Figure 8 This is a table showing the corresponding parameter records for each selected exposure anchor point during the iteration process in an example of the contact hole photolithography process condition design method of Embodiment 2 of the present invention.

[0046] Figure 9 The diagram shows the structure of the Tri-layer in the contact hole photolithography process condition design method of Embodiment 3 of the present invention.

[0047] Figure 10 The diagram shows the structure of the Bi-layer in the contact hole photolithography process condition design method of Embodiment 3 of the present invention.

[0048] Explanation of icon numbers

[0049] 10. Substrate; 11. Substrate; 12. Thin film; 13. NDC; 14. TEOS2; 15. BD2; 16. BD1; 17. TEOS1;

[0050] 18. TiN; 19. SOC;

[0051] 21. Light resist; 22. Anti-reflective layer. Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0054] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0055] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] In the back-end processes of semiconductor manufacturing, especially at advanced process nodes, excessively high line-edge roughness, linewidth roughness, and VIA (via) edge roughness can lead to a series of serious defects. Excessive edge roughness can cause short circuits between metal interconnects, affecting the normal operation of the entire circuit. Furthermore, if excessive line-edge roughness is carried over to the final pattern during etching, subsequent copper filling may fail, directly impacting critical parameters such as resistance and capacitance of the interconnects, thus reducing the overall circuit performance. As process nodes continue to shrink, the requirements for VIA edge roughness become increasingly stringent; therefore, improving its edge roughness is crucial.

[0058] Currently, several methods for optimizing VIA edge roughness have been proposed in the industry. For example, roughness can be improved by increasing the concentration of PAG (Photo-Acid Generator) in the photoresist. However, a drawback of this method is that increasing the PAG concentration makes the exposure dose more sensitive, leading to a decrease in energy latitude (EL), which reduces the process window and decreases the process's tolerance. Another method is to moderately increase the baking temperature or time after exposure. This method is suitable for photoresists with high deprotection energy during post-exposure baking. However, this method is not suitable for photoresists that require shorter baking times and lower temperatures, thus its applicability is relatively limited. Yet another method is to perform a chemical liquid spraying treatment on the photolithographic pattern surface before development, a method known as chemical trimming. Although this method can effectively improve roughness in some cases, it is costly and has limited applicability.

[0059] The present invention provides the following solution for improving the edge roughness of contact holes to meet the requirements of smaller size manufacturing processes.

[0060] Example 1:

[0061] like Figure 1 As shown, this embodiment provides a method for designing contact hole photolithography process conditions. The method for designing contact hole photolithography process conditions of the present invention will be described in detail below. It should be noted that the above order does not strictly represent the order of the contact hole photolithography process condition design method protected by the present invention, and those skilled in the art can make changes according to the actual design steps.

[0062] First, proceed with step 1, as follows: Figure 2 As shown, a substrate 10 to be coated with an antireflective layer is provided. The substrate 10 includes a substrate 11 and n thin films 12 deposited on the substrate 11, where n is an integer greater than or equal to 1. The parameters of the front film stack of the substrate 10 to be coated with the antireflective layer are measured and obtained. The front film stack parameters include the film thickness and corresponding extinction coefficient of each of the m thin films 12 from the topmost film 12 of the substrate 10, where m is an integer greater than or equal to 1 and less than or equal to n.

[0063] This invention obtains the front-layer thin film parameters of the substrate 10, including film thickness and extinction coefficient, and performs photolithography simulation on the existing substrate 10. This allows for iterative optimization and adjustment of parameters within the photolithography simulation, enabling the acquisition of optimized contact hole photolithography process conditions without actual experiments. This significantly reduces the cost of optimizing photolithography parameters and allows for extensive exploration of various possibilities, improving the accuracy of the optimization results. Furthermore, when dealing with different substrates 10, the photolithography simulation model of the substrate 10 can be directly replaced, and a specified iterative program can be executed to quickly address the required contact hole photolithography process conditions for different substrates 10, ensuring that corresponding contact hole edge improvements can be achieved for different substrate 10 structures.

[0064] In one embodiment, n is greater than or equal to 4, and m is greater than or equal to 4.

[0065] Preferably, m equals 4.

[0066] By setting the parameters of the front thin film, including the film thickness and extinction coefficient of each of the four thin films 12 starting from the top thin film 12, the present invention can obtain the best optimized iterative results for the contact hole photolithography process conditions, and further improve the improvement effect on the contact hole edge.

[0067] In one embodiment, the substrate 11 is a silicon substrate 11.

[0068] In one embodiment, the antireflective layer to be applied is a spin-on carbon (SOC) layer.

[0069] Then, in step 2, photolithography simulation is performed using the obtained front thin film parameters to obtain the relationship curve between the simulated film thickness and extinction coefficient of the anti-reflection layer to be coated, and then the target film thickness of the anti-reflection layer to be coated is selected.

[0070] Specifically, by selecting a simulated film thickness of the antireflective layer that corresponds to a minimum extinction coefficient, the antireflective layer can improve the transmittance of the exposed light during photolithography, avoid intensity attenuation of the exposed light when passing through the antireflective layer, reduce the scattering loss of the exposed light on the surface of the antireflective layer, reduce the main broadcast effect, improve the accuracy of the photolithography pattern, and also help improve the edge of the contact hole.

[0071] In one embodiment, the step of selecting the target film thickness of the antireflective layer to be coated further includes:

[0072] Obtain the second minimum point of the simulated film thickness versus extinction coefficient curve of the antireflective layer to be coated;

[0073] The simulated film thickness of the anti-reflective layer to be coated is selected from the second minimum point as the target film thickness of the anti-reflective coating.

[0074] This invention obtains the second minimum point of the relationship curve between the simulated film thickness and the extinction coefficient of the antireflection layer, thus avoiding the problem that the extinction coefficient obtained is not representative due to poor surface flatness when the film thickness is too small, thereby making the target film thickness obtained by photolithography simulation closer to the real situation.

[0075] Next, in step 3, photolithography simulation is performed based on the parameters of the previous thin film and the target film thickness and extinction coefficient of the anti-reflection layer to be coated, to obtain the simulated film thickness and reflectivity relationship curve (rocking curve) of the photoresist 21 set on the anti-reflection layer to be coated, and then the target film thickness of the photoresist 21 is selected.

[0076] In one embodiment, the step of obtaining the target film thickness of the photoresist 21 includes at least:

[0077] The parameters of the front thin film and the target film thickness and corresponding extinction coefficient of the anti-reflection coating are input into the photolithography simulation software for simulation to obtain the simulation film thickness and reflectivity relationship curve of the photoresist 21 set on the anti-reflection layer to be coated, and at least one minimum point in the curve where the absolute value of the slope is close to 0 is selected.

[0078] Select at least one minimum point where the absolute value of the slope is close to 0 as the simulated film thickness of the photoresist 21 as the target film thickness of the photoresist 21.

[0079] Specifically, there are multiple minimum points where the absolute value of the slope of the simulated film thickness and reflectivity curve of photoresist 21 is close to 0, and at least one of these valley points can be selected according to actual needs.

[0080] Specifically, the absolute value of the curve slope being close to 0 can be defined according to the actual measurement tools and accuracy requirements. This article does not impose any restrictions on this.

[0081] This invention selects the minimum point where the absolute value of the slope of the reflectance relationship curve is close to 0 in the photolithography simulation. This ensures that the reflectance of the photoresist 21 of this film thickness is stable during the photolithography process, and at the same time achieves the relative minimization of the reflectance of the photoresist 21. Thus, they work together to improve the accuracy and uniformity of photolithography, and also help improve the edge of the contact hole.

[0082] Then, proceed to step 4, based on the parameters of the front thin film, the target film thickness and extinction coefficient of the antireflective layer to be coated, and the target film thickness of the photoresist 21, select candidate exposure anchor points, fix the lithography parameters to be optimized and the illumination mode parameters, perform lithography simulation, and obtain at least one target exposure anchor point.

[0083] This invention selects candidate exposure anchor points that meet the requirements as target exposure anchor points according to preset standards, thereby ensuring that all target exposure anchor points used for optimizing and iterating the contact hole photolithography process conditions meet the preset standards.

[0084] In one embodiment, the illumination parameters include the illumination mode of the exposure light source and the polarization state of the exposure light source.

[0085] In one embodiment, the illumination mode of the exposure light source is ring illumination, and the polarization state of the exposure light source is TE polarization.

[0086] Specifically, the lighting parameters can also be selected in appropriate combinations as the lighting parameters for the target exposure anchor point, depending on the requirements.

[0087] In one embodiment, the step of obtaining at least one target exposure anchor point further includes:

[0088] A series of feature images are selected as candidate exposure anchor points;

[0089] Photolithography simulation is performed with fixed lithography parameters and illumination parameters to be optimized. One or more of the following parameters corresponding to the candidate exposure anchor point are obtained as preset screening parameters: key linewidth, linewidth uniformity parameter, mask error enhancement factor, energy margin (EL), or depth of field (DOF).

[0090] At least one candidate exposure anchor point among the candidate exposure anchor points whose preset screening parameters satisfy the lithography process window design conditions is selected as the target exposure anchor point.

[0091] In one embodiment, key linewidth, linewidth uniformity parameters, and mask error enhancement factors are obtained by measuring the simulated two-dimensional graphic of the contact hole.

[0092] This invention uses one or more of the following parameters as preset screening parameters: key linewidth, linewidth uniformity parameter, mask error enhancement factor, energy margin (EL), or depth of focus (DOF) corresponding to the candidate exposure anchor point. This allows the selection of candidate exposure anchor points that meet the process window conditions as target exposure anchor points, ensuring that all target exposure anchor points meet the process window conditions.

[0093] Preferably, the key linewidth, linewidth uniformity parameter, mask error enhancement factor, energy margin (EL), or depth of focus (DOF) are all used as preset screening parameters to ensure that the process window conditions are met; however, some parameters can be selectively used as preset screening parameters to improve iteration efficiency. Those skilled in the art can make appropriate adjustments according to their needs, all of which are within the protection scope of this invention.

[0094] In one embodiment, the series of feature graphics includes: such as Figure 3 The preset periodic dense pattern shown is as follows: Figure 4 The preset periodic semi-dense pattern shown is as follows: Figure 5 The example shown is a preset periodic semi-dense pattern with sub-resolution assist feature (SRAF) added based on preset rules, and / or as shown in the image. Figure 6 The figure shown is an isolated graphic within the sparse region.

[0095] This invention selects a series of feature patterns of different densities to ensure that the final contact hole photolithography process conditions are applicable to the preparation of contact holes with various pattern densities, thereby improving the effect on the edges of each contact hole in the overall product.

[0096] Finally, in step 5, the photolithography process conditions obtained in the preceding steps are verified on the substrate 10 by changing the illumination condition parameters. The target exposure anchor point with the smallest edge roughness of the contact hole obtained by photolithography is selected as the selected exposure anchor point, and the corresponding illumination condition parameters of the selected exposure anchor point are obtained, thereby determining the contact hole photolithography process conditions. The illumination condition parameters include: numerical aperture (NA), relative radius of the outer ring pupil (σ). out ) and the relative radius of the inner pupil (σ) in The photolithography process conditions obtained in the aforementioned steps include: the target film thickness of the antireflective layer to be coated, the target film thickness of the photoresist 21, the illumination mode parameters, and the at least one target exposure anchor point.

[0097] This invention determines the optimal anti-reflection layer and photoresist 21 film thickness, illumination parameters, and target exposure anchor point that meets the process window conditions through photolithography simulation. Then, iterative optimization of the illumination condition parameters is performed to obtain the selected exposure anchor point with the smallest contact hole edge. At the same time, this design method can determine the optimal photolithography process conditions for contact hole preparation for different processes such as Tri-layer or Bi-layer in advance. It can quickly adapt to photolithography conditions when the process changes, so that contact holes prepared under different processes can achieve a small edge roughness.

[0098] Specifically, the design method for contact hole photolithography process conditions of the present invention can be applied to various technology nodes. Among them, since technology nodes of 28nm and below have higher requirements for the pattern accuracy of contact holes and require more minimization of contact hole edges, technology nodes of 28nm and below need to use the solution of the present invention to improve the edge roughness of contact holes.

[0099] In one embodiment, the design of the present invention is used in an immersion lithography process. Specifically, it can also be applied to other suitable lithography processes (such as non-immersion lithography processes) as needed, all of which are within the scope of protection of the present invention.

[0100] In one embodiment, the step of changing the illumination condition parameters on the substrate 11 further includes:

[0101] Select a set of lighting condition parameters as an initial parameter set, and iterate by changing one of the lighting condition parameters based on the initial parameter set.

[0102] When the change in the roughness of the contact hole edge obtained by photolithography is less than the preset change value, the lighting condition parameters obtained at this time are used as the new initial parameter set, and the lighting condition parameters that have not been iterated are selected for iteration.

[0103] After iterating a preset number of times, the illumination condition parameters with the minimum contact hole edge roughness are used as the contact hole photolithography process conditions.

[0104] Specifically, the preset change value can be set to an appropriate value based on experience, proving that the contact hole edge roughness obtained by the lighting condition parameters based on the initial parameter set has approached the minimum value and is almost unchanged, and the iteration under the lighting condition parameters can be stopped.

[0105] In one embodiment, the preset number of iterations is 3-5. Specifically, those skilled in the art can design other iteration numbers according to requirements. In practice, 3-5 iterations are generally sufficient to obtain the case where the contact hole edge roughness is minimized under the given lighting conditions.

[0106] In one embodiment, such as Figure 1 As shown, the design method further includes:

[0107] Step 6: Determine whether the edge roughness of the contact hole obtained by photolithography under the illumination condition parameters corresponding to the selected exposure anchor point is higher than the reference threshold;

[0108] If the edge roughness is higher than the reference threshold, the illumination condition parameters are adjusted and the photolithography process verification in step 5 is repeated to obtain a new selected exposure anchor point; if the edge roughness is not higher than the reference threshold, the iteration ends and the illumination condition parameters corresponding to the obtained contact hole edge roughness are output.

[0109] Specifically, those skilled in the art can select other suitable reference thresholds as needed to meet the requirements of the specific technical node for the roughness of the contact hole edge, all of which are within the protection scope of this invention.

[0110] In one embodiment, the above steps can all be input into the lithography program and simulation software to achieve automated iterative calculations and improve iterative optimization efficiency.

[0111] Example 2:

[0112] This embodiment provides a method for designing contact hole photolithography process conditions. The design method is basically the same as other features in Embodiment 1, except that:

[0113] In this embodiment, the design method is applied to the photolithography process of the following substrate 10 structure:

[0114] like Figure 7 As shown, the substrate 10 consists of NDC (Nitride Doped Carbon) 13, TEOS2 (Tetraethyl orthosilicate) 14, BD2 (Blocking Layer) 15, BD1 (16), TEOS1 (17), TiN18, and SOC19 (Spin-On Carbon).

[0115] In this embodiment, the thickness of NDC13 is 250 Å, the thickness of TEOS2 (14) is 150 Å, the thickness of BD2 (15) is 150 Å, the thickness of BD1 (16) is 150 Å, the thickness of TEOS1 (17) is 200 Å, and the thickness of TiN18 is 210 Å.

[0116] In this embodiment, as Figure 8 The table shown is a partial data table of various illumination condition parameters and their corresponding energy margin (EL), depth of focus (DOF), and aperture edge roughness (CER) during a parameter iteration of the substrate 10. When changing the illumination condition parameters on the substrate 11: select a set of illumination condition parameters as the initial parameter set, and simultaneously change two or more of the illumination condition parameters based on the initial parameter set for iteration.

[0117] When the change in the roughness of the contact hole edge obtained by photolithography is less than the preset change value (the edge roughness can be judged to be almost unchanged based on experience or actual program measurement), the illumination condition parameters obtained at this time are used as the new initial parameter set.

[0118] After iterating a preset number of times, the illumination condition parameters with the minimum contact hole edge roughness are used as the contact hole photolithography process conditions.

[0119] This invention performs large-step iterations by simultaneously changing two or more lighting condition parameters. Although some lighting condition parameters with smaller contact hole edge roughness may be missed, the above-mentioned iterative method can be used to first confirm a rough range of lighting condition parameters. Then, when changing a single lighting condition parameter for further small-step iterations, it can be ensured that the lighting condition parameters are within a relatively optimal range, thereby improving the efficiency of iterative optimization and reducing the number of optimizations.

[0120] In this embodiment, the linewidth / spacing of the target exposure anchor point obtained in step 4 is 108 μm / 72 μm. Using ring illumination, the numerical aperture (NA) corresponding to the selected exposure anchor point is 1.35, and the relative radius of the outer ring pupil (σ) is... out The relative radius of the inner ring pupil is σ = 0.7. in With a value of 0.5, the circle edge roughness (CER) obtained by iterating multiple lighting condition parameters simultaneously can be reduced from the initial 4.46 to 2.44. It can be seen that after 5 iterations, the circle edge roughness is halved, and the improvement effect is obvious.

[0121] Example 3:

[0122] This embodiment provides a method for designing contact hole photolithography process conditions. The design method is basically the same as other features in Embodiment 1, except that:

[0123] In this embodiment, the design method is applied in a photolithography process where the structure on the substrate 11 is a Tri-layer structure.

[0124] In one embodiment, such as Figure 9 As shown, the Tri-layer structure consists of photoresist (PR, also known as photoresist 21), anti-reflection layer 22, and spin-coated carbon layer (SOC19) from top to bottom.

[0125] This invention applies a contact hole photolithography process condition design method to a Tri-layer photolithography structure, which can not only reduce the reflection of exposure light and improve pattern clarity and reduce the edge roughness of the contact hole, but also improve etching selectivity. Compared with the Bi-layer photolithography structure, it is suitable for more advanced process nodes (such as 28nm and below). However, the spin coating process of SOC19 is more complicated and has an additional spin coating process, resulting in higher costs.

[0126] Example 4:

[0127] This embodiment provides a method for designing contact hole photolithography process conditions. The design method is basically the same as other features in Embodiment 1, except that:

[0128] In this embodiment, the design method is applied to a photolithography process where the structure on the substrate 11 is a Bi-layer.

[0129] In one embodiment, such as Figure 10 As shown, the Bi-layer structure consists of photoresist (photoresist 21) and anti-reflection layer 22 from top to bottom.

[0130] This invention applies a contact hole photolithography process condition design method to a Bi-layer photolithography structure, mainly to reduce the reflection of exposure light to improve pattern clarity. Compared with a Tri-layer photolithography structure, it is suitable for cost-sensitive applications, with a simpler process and relatively lower cost.

[0131] Example 5:

[0132] The present invention provides a semiconductor structure, wherein the contact hole photolithography process conditions for setting contact holes on the semiconductor structure are obtained by any one of the contact hole photolithography process condition design methods described in Examples 1-4. The semiconductor structure includes a substrate 11 and n thin films 12 deposited on the substrate 11, where n is an integer greater than or equal to 1.

[0133] Preferably, n is greater than or equal to 4.

[0134] This invention optimizes the iterative effect of contact hole edge roughness obtainable by setting the number of thin film layers to 12 in the semiconductor structure.

[0135] In summary, the contact hole photolithography process condition design method and semiconductor structure of the present invention can significantly improve the edge roughness of the contact holes obtained by photolithography through iterative optimization of the illumination condition parameters. Furthermore, before iterative optimization, target exposure anchor points are selected through process window design conditions, ensuring that the contact holes with improved edge roughness meet the process window design conditions, making them suitable for photolithography processes at technology nodes of 28nm and below. Additionally, the contact hole photolithography process condition design method can rapidly adapt to changes in photolithography conditions caused by processes corresponding to Tri-layer and Bi-layer structures, ensuring that the edge roughness of the contact holes and the photolithography process window conditions are maintained even when the process is changed.

[0136] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0137] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for designing photolithography process conditions for contact holes, characterized in that, The design method includes: A substrate to be coated with an antireflective layer is provided, the substrate including a substrate and n thin films deposited on the substrate, where n is an integer greater than or equal to 1; the parameters of the front thin film of the substrate to be coated with the antireflective layer are measured and obtained, the parameters of the front thin film include the film thickness and corresponding extinction coefficient of each of the m thin films from the topmost thin film of the substrate, where m is an integer greater than or equal to 1 and less than or equal to n. Photolithography simulation is performed using the obtained front thin film parameters to obtain the relationship curve between the simulated film thickness and extinction coefficient of the anti-reflection layer to be coated, and then the target film thickness of the anti-reflection layer to be coated is selected. Photolithography simulation is performed based on the parameters of the previous thin film and the target film thickness and extinction coefficient of the anti-reflection layer to be coated, and the simulated film thickness and reflectivity relationship curve of the photoresist set on the anti-reflection layer to be coated is obtained, and then the target film thickness of the photoresist is selected. Based on the parameters of the front thin film, the target film thickness and extinction coefficient of the antireflective layer to be coated, and the target film thickness of the photoresist, candidate exposure anchor points are selected, and photolithography simulation is performed by fixing the photolithography parameters to be optimized and the illumination mode parameters to obtain at least one target exposure anchor point. On the substrate, by changing the illumination condition parameters, the photolithography process conditions obtained in the aforementioned steps are verified. The target exposure anchor point with the smallest edge roughness of the contact hole obtained by photolithography is selected as the selected exposure anchor point, and the corresponding illumination condition parameters of the selected exposure anchor point are obtained, thereby determining the contact hole photolithography process conditions. The illumination condition parameters include: numerical aperture, relative radius of the outer ring pupil, and relative radius of the inner ring pupil. The photolithography process conditions obtained in the aforementioned steps include: the target film thickness of the antireflective layer to be coated, the target film thickness of the photoresist, the illumination mode parameters, and the at least one target exposure anchor point.

2. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, n is greater than or equal to 4 m is greater than or equal to 4.

3. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, The step of selecting the target film thickness of the antireflective layer to be coated further includes: Obtain the second minimum point of the simulated film thickness versus extinction coefficient curve of the antireflective layer to be coated; The simulated film thickness of the anti-reflective layer to be coated, corresponding to the second minimum point, is selected as the target film thickness of the anti-reflective layer.

4. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, The step of obtaining the target film thickness of the photoresist includes at least the following: The parameters of the front thin film and the target film thickness and corresponding extinction coefficient of the anti-reflection layer are input into the photolithography simulation software for simulation to obtain the simulated film thickness and reflectivity relationship curve with photoresist set on the anti-reflection layer to be coated, and at least one minimum point in the curve with an absolute slope value close to 0 is selected. Select at least one minimum point where the absolute value of the slope is close to 0 as the simulated film thickness of the photoresist as the target film thickness of the photoresist.

5. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, The lighting parameters include the illumination mode of the exposure light source and the polarization state of the exposure light source.

6. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, The step of obtaining at least one target exposure anchor point further includes: A series of feature images are selected as candidate exposure anchor points; Photolithography simulation is performed with fixed lithography parameters and illumination parameters to be optimized, and one or more of the following parameters corresponding to the candidate exposure anchor point are obtained as preset screening parameters: key linewidth, linewidth uniformity parameter, mask error enhancement factor, energy margin or focus depth. At least one candidate exposure anchor point among the candidate exposure anchor points whose preset screening parameters satisfy the lithography process window design conditions is selected as the target exposure anchor point.

7. The method for designing contact hole photolithography process conditions according to claim 6, characterized in that, The series of feature patterns includes: a preset periodic dense pattern, a preset periodic semi-dense pattern, a preset periodic semi-dense pattern with added exposure auxiliary patterns based on preset rules, and / or an isolated pattern in a sparse area.

8. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, The step of changing the illumination condition parameters on the substrate further includes: Select a set of lighting condition parameters as an initial parameter set, and iterate by changing one or more of the lighting condition parameters based on the initial parameter set. When the change in the roughness of the contact hole edge obtained by photolithography is less than the preset change value, the illumination condition parameters obtained at this time are used as the new initial parameter set. After iterating a preset number of times, the illumination condition parameters with the minimum contact hole edge roughness are used as the contact hole photolithography process conditions.

9. The method for designing contact hole photolithography process conditions according to claim 1, characterized in that, The design method further includes: Determine whether the edge roughness of the contact hole obtained by photolithography under the illumination condition parameters corresponding to the selected exposure anchor point is higher than the reference threshold. If the edge roughness is higher than the reference threshold, the illumination condition parameters are adjusted and the photolithography process is re-verified to obtain a new selected exposure anchor point; if the edge roughness is not higher than the reference threshold, the iteration ends and the illumination condition parameters corresponding to the obtained contact hole edge roughness are output.

10. A semiconductor structure, characterized in that, The semiconductor structure is provided with contact hole photolithography process conditions by designing contact hole photolithography process conditions according to any one of claims 1-9. The semiconductor structure includes a substrate and n thin films deposited on the substrate, where n is an integer greater than or equal to 1.

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