Program control method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a program control method and device, electronic equipment and a storage medium, the method is applied to a control system, the control system comprises a control end and a program scheduler, and the method comprises the steps that the control end reads a clock signal of a to-be-tested design, when the clock signal reaches a clock cycle edge, operation of the to-be-tested design is suspended, and the program scheduler is started; a control signal is sent to the program scheduler; under the condition that the program scheduler receives the control signal sent by the control end, the subprograms are scheduled in sequence according to the execution sequence of the subprograms in the test program; under the condition that each subprogram in the test program runs to a preset position, sending a wake-up signal to a control end; and under the condition that the control end receives the wake-up signal, the to-be-tested design is driven to continuously run to the edge of the next clock period. In the embodiment of the invention, the hardware clock can be controlled and the parallel operation can be completed through the software programming language, so that the program control efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a program control method, device, electronic equipment and storage medium. Background Art

[0002] In the process of verifying the design under test, hardware programming languages ​​are generally used. In recent years, there has been a demand for using software programming languages ​​to verify chips. However, software programming languages ​​cannot well control the parallel operations and clocks required by the hardware. Among the existing tools, cocotb can well meet the control requirements by controlling coroutines based on callbacks. However, the implementation requirements are relatively high and the operating efficiency is also low. Therefore, the efficiency of controlling hardware clocks and completing parallel operations in software programming languages ​​is reduced. Summary of the invention

[0003] The embodiments of the present invention provide a program control method, device, electronic device and storage medium, which can solve the problems in the related art that the software programming language cannot well control the parallel operations and clocks required by the hardware, and the control implementation requirements are relatively high and the operating efficiency is also low.

[0004] In order to solve the above problems, an embodiment of the present invention discloses a program control method, which is applied to a control system. The control system includes a control terminal and a program scheduler. The method includes: The control end reads the clock signal of the design to be tested, and when the clock signal reaches a clock cycle edge, suspends the operation of the design to be tested, and sends a control signal to the program scheduler; The program scheduler schedules the subprograms in the test program in order according to the execution order of the subprograms in the test program when receiving the control signal sent by the control end; and sends a wake-up signal to the control end when all the subprograms in the test program run to a preset position; When receiving the wake-up signal, the control end drives the design under test to continue running until the next clock cycle edge.

[0005] Optionally, the method further comprises: When the clock signal reaches a clock cycle edge, obtaining a first operation result of the design to be tested; When at least one subprogram runs to a preset position, obtaining a second running result corresponding to the at least one subprogram; Matching the first operation result with the second operation result; When the first operation result matches the second operation result, determining that the design to be tested operates correctly; When the first operation result does not match the second operation result, it is determined that the design under test has an operation error.

[0006] Optionally, when receiving the wake-up signal, the control end drives the design under test to continue running until the next clock cycle edge, including: When receiving the wake-up signal, the control end calls the driving interface to send a driving signal to the design under test, so as to drive the design under test to continue running until the next clock cycle edge.

[0007] Optionally, driving the design under test to continue running until a next clock cycle edge includes: Acquire the signal value of the first interface in each of the subroutines; the first interface is any interface in the subroutines; Determining a second interface in the design to be tested that matches the first interface; The signal value is input to the second interface, and the design under test is driven to continue running until the next clock cycle edge.

[0008] Optionally, upon receiving the control signal sent by the control terminal, the program scheduler sequentially schedules the subprograms according to the execution order of the subprograms in the test program, including: The program scheduler, upon receiving the control signal sent by the control terminal, schedules the first subprogram in the test program according to the execution order of each subprogram in the test program, and monitors the running status of the first subprogram; The program scheduler schedules a second subprogram when the first subprogram runs to a preset position; wherein the second subprogram is a next subprogram corresponding to the first subprogram.

[0009] Optionally, before the control end reads the clock signal of the design to be tested, the method further includes: According to the test logic of the test program, a waiting function is added in a preset position of each subprogram; the waiting function is used to pause the running of the subprogram.

[0010] On the other hand, an embodiment of the present invention discloses a program control device, which is applied to a control system. The control system includes a control terminal and a program scheduler. The device includes: A reading module, used to read the clock signal of the design under test; A sending module, used for pausing the operation of the design to be tested and sending a control signal to the program scheduler when the clock signal reaches a clock cycle edge; A scheduling module, for scheduling the subroutines in the test program in sequence according to the execution order of the subroutines in the test program when receiving a control signal sent by the control terminal; The sending module is used to send a wake-up signal to the control end when each subroutine in the test program runs to a preset position; The driving module is used to drive the design under test to continue running to the next clock cycle edge when a wake-up signal is received.

[0011] Optionally, the device further comprises: An acquisition module, configured to acquire a first operation result of the design to be tested when the clock signal reaches an edge of a clock cycle; and acquire a second operation result corresponding to the at least one subroutine when at least one subroutine runs to a preset position; A matching module, used for matching the first operation result with the second operation result; The determination submodule is used to determine that the design to be tested runs correctly when the first running result matches the second running result; and to determine that the design to be tested runs incorrectly when the first running result does not match the second running result.

[0012] Optionally, the driving module includes: The driving submodule is used to call the driving interface when receiving the wake-up signal, send a driving signal to the design under test, and drive the design under test to continue running until the next clock cycle edge.

[0013] Optionally, the driving module further includes: An acquisition submodule, used for acquiring a signal value of a first interface in each of the subprograms; the first interface is any interface in the subprogram; A first determination submodule, used to determine a second interface in the design to be tested that matches the first interface; An input module is used to input the signal value to the second interface and drive the design under test to continue running to the next clock cycle edge.

[0014] Optionally, the scheduling module further includes: A first scheduling submodule, configured to schedule a first subprogram in the test program according to the execution order of each subprogram in the test program when receiving a control signal sent by the control terminal; A monitoring module, used for monitoring the running status of the first subroutine; The second scheduling submodule is used to schedule a second subprogram when the first subprogram runs to a preset position; wherein the second subprogram is the next subprogram corresponding to the first subprogram.

[0015] Optionally, the device further comprises: An adding module is used to add a waiting function in a preset position of each subprogram according to the test logic of the test program; the waiting function is used to pause the running of the subprogram.

[0016] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned program control method.

[0017] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned program control method.

[0018] The embodiments of the present invention include the following advantages: The embodiment of the present invention provides a program control method, the control system includes a control end and a program scheduler, in the process of program control, when the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of each subroutines in the test program; when each subroutines in the test program runs to a preset position, a wake-up signal is sent to the control end; at the same time, the control end reads the clock signal of the design to be tested, starts to drive the design to be tested, and when the clock signal reaches a clock cycle edge, the operation of the design to be tested is paused, and a control signal is sent to the program scheduler; that is, the scheduling of the subroutines by the program scheduler and the driving of the design to be tested by the control end are executed alternately, and then the hardware clock can be controlled and parallel operations can be completed through the software programming language, thereby improving the program control efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0020] Figure 1 is a flowchart of steps of an embodiment of a program control method of the present invention; Figure 2It is a schematic diagram of the architecture of a control system of the present invention; Figure 3 It is a schematic diagram of the execution sequence flow of a program in a model of the present invention; Figure 4 is a structural block diagram of an embodiment of a program control device of the present invention; Figure 5 It is a structural block diagram of an electronic device provided by an example of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0023] Method Embodiment Reference Figure 1 , shows a flowchart of a program control method embodiment of the present invention, the method may specifically include the following steps: Step S101, the control end reads the clock signal of the design to be tested, and when the clock signal reaches a clock cycle edge, the operation of the design to be tested is suspended, and a control signal is sent to the program scheduler; Step S102: when receiving the control signal sent by the control end, the program scheduler sequentially schedules the subprograms according to the execution order of each subprogram in the test program; when each subprogram in the test program runs to a preset position, a wake-up signal is sent to the control end; Step S103: When receiving the wake-up signal, the control end drives the design under test to continue running until the next clock cycle edge.

[0024] The program control method provided in the embodiment of the present invention can be applied to a control system, wherein the control system includes a control terminal and a program scheduler. Figure 2 , shows a schematic diagram of the architecture of a control system provided by an embodiment of the present invention. Figure 2 As shown, the control end is used to drive the design to be tested, and the program scheduler is used to schedule and process each subroutine in the test program. The program scheduler in the present invention may include a component that can schedule and process each subroutine. The program scheduler arranges the scheduling order of the program reasonably so that resources such as the central processing unit (CPU) are kept as busy as possible to reduce idle time.

[0025] In the embodiment of the present invention, through the interaction between the control terminal and the program scheduler, the parallel control of each subprogram in the test program and the synchronous control of the test program and the design to be tested can be realized.

[0026] Exemplarily, the control end in the embodiment of the present invention may first read the clock signal of the design under test, and when the clock signal reaches a clock cycle edge, suspend the operation of the design under test and send a control signal to the program scheduler.

[0027] The control signal is used to instruct the program scheduler to schedule the subroutines in sequence according to the execution order of each subroutine in the test program.

[0028] The design under test is driven by a clock signal. The operation of the design under test can be suspended by controlling the clock signal. When the input of the clock signal in the design under test is stopped, the design under test will also stop running. The design under test (DUT) refers to the circuit design or implementation to be tested in prototype verification. For example, the design under test can be a register transfer level (RTL) circuit or other hardware design.

[0029] When receiving the control signal sent by the control end, the program scheduler schedules the subprograms in the test program in sequence according to the execution order of each subprogram in the test program; when each subprogram in the test program runs to a preset position, a wake-up signal is sent to the control end.

[0030] Among them, the test program is used to test the performance or correctness of the design under test to verify whether the design under test meets the expected functional and performance requirements.

[0031] As an example, the user can write a test program in advance according to the test requirements, and divide the test program into at least one subroutine according to the dependencies and execution order of the test cases or execution flows in the test program, and determine the execution order of each subroutine. It should be noted that the subroutines in the embodiment of the present invention can be executed in parallel. For example, assuming that the test program contains subroutine 1, subroutine 2 and subroutine 3, in one execution stage, subroutine 1 can be run to a preset position first, then subroutine 2 can be run to a preset position, and finally subroutine 3 can be run to a preset position; in the next execution stage, it continues to run from subroutine 1, and the parallel control of the subroutines is realized by executing each subroutine in segments.

[0032] The preset position refers to the position where the waiting function is added in each subroutine. When the subroutine reaches the preset position, the program scheduler will pause the running of the subroutine.

[0033] The wake-up signal can be used to trigger the drive to continue running the design under test, and can also be used to wake up the waiting signals of each subroutine when receiving the control signal sent by the control end, so as to avoid the situation where each subroutine cannot continue to run and continues to stop at the preset position.

[0034] Exemplarily, when the test program includes subprogram 1, subprogram 2, subprogram 3, ..., and other programs, the program scheduler can schedule subprogram 1, subprogram 2, subprogram 3, ..., and other subprograms in sequence, and then send a wake-up signal to the control end when subprogram 1, subprogram 2, subprogram 3, ..., and other subprograms have all run to preset positions.

[0035] When the control end receives the wake-up signal, it drives the design under test to continue running until the next clock cycle edge, thereby realizing synchronous control of the test program and the design under test.

[0036] Reference Figure 3 , shows a schematic diagram of the execution sequence flow of a program in a model of the present invention, which may specifically include the following: Based on the coroutine in the software programming language, the hardware's demand for parallel operation is met. Users can design multiple coroutines that run simultaneously and write independent control logic in each coroutine.

[0037] In this model, a control terminal is used to manage the hardware clock, and the control terminal is also implemented by a coroutine. Since the design in chip verification only changes state at the clock edge, the control terminal stops at the clock edge continuously. Each time it stops, the DUT clock is actually advanced and directly pushed to the next clock edge. Between ①② and between ②③, it is driven by the control terminal.

[0038] For example, refer to Figure 3, the test program refers to ①, ②, ③, etc. Test program ① includes a.value=1, b.value=2 and Await in subprogram 1, c.value=1, d.value=3 and Await in subprogram 2, e.value=5, f.value=6 and Await in subprogram 3 and other subprograms; when the program scheduler receives the control signal sent by the control end, it starts to schedule subprogram 1. When subprogram 1 runs to Await, the program scheduler can schedule subprogram 2. When subprogram 2 runs to Await, the program scheduler can schedule subprogram 3. Similarly, when subprogram 3 runs to Await, the program scheduler can schedule the next subprogram until the test program is completed. If all subroutines of sequence ① have run to the Await position, it means that program test program ① has finished running, and then the design under test can be driven by the control end. When the design under test runs to the edge of the next clock cycle, the running of the design under test is paused and the running of test program ② is started. Similarly, the program scheduler starts scheduling subroutine 1, scheduling subroutine 2, scheduling subroutine 3, and sequentially executes (print (c.value), a.value=2, Await) in subroutine 1, (c.valid=0, d.valid=1, Await) in subroutine 2, (print (e.value), e.value=4, Await) in subroutine 3, and so on, to achieve synchronous control of the test program and the design under test.

[0039] The control end sends (control signal) event signals to guide the operation of each coroutine. Every time the control end reaches a clock edge, it stops and sends an event signal to inform other coroutines that the clock has reached the next edge. Other coroutines synchronize with the DUT clock by detecting this signal. When all coroutines are executed to wait for the next clock signal, control is returned to the control end to continue driving the DUT.

[0040] The embodiment of the present invention provides a program control method, the control system includes a control end and a program scheduler, in the process of program control, when the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of each subroutines in the test program; when each subroutines in the test program runs to a preset position, a wake-up signal is sent to the control end; at the same time, the control end reads the clock signal of the design to be tested, starts to drive the design to be tested, and when the clock signal reaches a clock cycle edge, the operation of the design to be tested is paused, and a control signal is sent to the program scheduler; that is, the scheduling of subroutines and driving of the design to be tested by the program scheduler are executed alternately, and then the hardware clock can be controlled and parallel operations can be completed through the software programming language, thereby improving the program control efficiency.

[0041] In an embodiment of the present invention, the program control method may specifically include the following steps: Step S104: when the clock signal reaches a clock cycle edge, obtain a first running result of the design to be tested.

[0042] In the embodiment of the present invention, during the process of program control, the control system may also obtain the first operation result of the design to be tested when the clock signal reaches an edge of a clock cycle.

[0043] In the embodiment of the present invention, the running result of the design under test may include the intermediate result generated during the running process of the design under test, or may include the final result output by the design under test. According to the running result of the design under test, it can be verified whether the design under test meets the expected function.

[0044] The first running result of the design to be tested may be one or a group of numerical values, or may be state information or timing information, etc., which is not limited in the embodiments of the present invention.

[0045] Illustratively, in an embodiment of the present invention, taking the design to be tested as an RTL circuit as an example, when the first result is data output, the data output may be one or a group of values. Specifically, the data output may be a digital signal after filtering, amplification, and the like.

[0046] Alternatively, in the embodiment of the present invention, the first operation result of the design to be tested may be timing information represented by a square wave. For example, the first operation result may be timing information with a step size of 2 and an amplitude of 2 on the time axis.

[0047] Step S105: When at least one subprogram has run to a preset position, a second running result corresponding to at least one subprogram is obtained.

[0048] In an embodiment of the present invention, after obtaining the first operating result of the design to be tested when the clock signal reaches a clock cycle edge, the control system can also obtain the second operating result corresponding to at least one subroutine when at least one subroutine runs to a preset position.

[0049] Exemplarily, when subprogram 1, subprogram 2, subprogram 3, ..., etc., all subprograms are run to a preset position, the second running results corresponding to all subprograms can be obtained.

[0050] The second running result of the subroutine may include an intermediate result generated during the running of the subroutine, or may include a final result output after the subroutine runs. The second running result is used as a reference value of the first running result of the design to be tested to verify whether the running of the design to be tested is wrong.

[0051] The second running result of the subroutine may be one or a group of numerical values, or may be state information or timing information, etc., which is not limited in the embodiments of the present invention.

[0052] Illustratively, in an embodiment of the present invention, taking the design to be tested as an RTL circuit as an example, when the second operating result of the subroutine is a numerical value, its output may be one or a group of numerical values. Specifically, the second operating result output by the subroutine may be a digital signal after filtering, amplification, and other processing.

[0053] Alternatively, in the embodiment of the present invention, the second running result of the subroutine may be timing information represented by a square wave. For example, the second running result may be timing information with a step size of 2 and an amplitude of 2 on the time axis.

[0054] It can be understood that, in the embodiment of the present invention, when at least one subprogram runs to a preset position, the obtained second running result may include the running results of each subprogram.

[0055] Exemplarily, when subprogram 1 runs to a preset position, the running result corresponding to subprogram 1 is [0, 2], and when subprogram 2 runs to a preset position, the running result corresponding to subprogram 2 is [0, 3], ..., after all subprograms run to the preset positions, the second running result corresponding to the at least one subprogram may be a collection of the running results corresponding to each subprogram.

[0056] Step S106: Match the first operation result with the second operation result.

[0057] In an embodiment of the present invention, when at least one subroutine runs to a preset position, after obtaining a second running result corresponding to at least one subroutine, the control system can also match the first running result with the second running result, and determine whether the design to be tested runs incorrectly based on the matching result.

[0058] It is understandable that the situation where the first operating result matches the second operating result includes that the first operating result is the same as the second operating result, or the first operating result and the second operating result belong to the same reference interval, and so on.

[0059] Exemplarily, in an embodiment of the present invention, when the first running result of the design to be tested and the second running result of the subroutine are both numerical values, the two sets of numerical values ​​are compared. Assuming that the first running result of the design to be tested is 1, and the second running result corresponding to at least one subroutine is 2, at this time, the first running result of the device to be tested is different from the second running result of the subroutine, and it can be determined that the first running result does not match the second running result.

[0060] Alternatively, in an embodiment of the present invention, when the first operation result of the design to be tested and the second operation result of the subroutine are both timing information, the two sets of timing information are compared. When the step length and amplitude corresponding to the first operation result of the design to be tested are the same as the step length and amplitude corresponding to the second operation result of the subroutine, at this time, the first operation result of the device to be tested is the same as the second operation result of the subroutine, and it can be determined that the first operation result matches the second operation result.

[0061] Step S107: When the first operation result matches the second operation result, it is determined that the design to be tested operates correctly.

[0062] In the embodiment of the present invention, after matching the first operation result with the second operation result, if the first operation result matches the second operation result, it is determined that the design to be tested operates correctly.

[0063] Step S108: When the first operation result does not match the second operation result, determine that the design under test has an operation error.

[0064] In the embodiment of the present invention, after matching the first operation result with the second operation result, the control system may also determine that the design to be tested has an operation error if the first operation result does not match the second operation result.

[0065] Furthermore, when it is determined that an error occurs in the operation of the design to be tested, the operation of the design to be tested and each subroutine may be suspended, and the design to be tested may be debugged using simulation software.

[0066] In an optional embodiment of the present invention, when the control end receives the wake-up signal, driving the design under test to continue running until the next clock cycle edge may specifically include the following steps: Step S1031: When receiving the wake-up signal, the control end calls the driving interface and sends a driving signal to the design under test, so as to drive the design under test to continue running until the next clock cycle edge.

[0067] In the embodiment of the present invention, the control end calls the driving interface to send a driving signal to the design under test, or calls the driving interface to realize the transmission of a clock signal.

[0068] The driver interface can be a logic module in the test platform that generates and controls the input signals to the DUT interface. The core function of the driver interface is to provide the DUT with input stimuli (such as clock, data, and control signals) that comply with the protocol specifications and simulate the interaction behavior in the real environment to verify whether the function and timing of the DUT are normal.

[0069] Exemplarily, the control end may also send a driving signal to the design under test through a driving protocol.

[0070] In an optional embodiment of the present invention, the step of driving the design under test to continue running until the next clock cycle edge may specifically include the following steps: Step S1032, obtaining the signal value of the first interface in each subroutine; the first interface is any interface in the subroutine; Step S1033, determining a second interface in the design to be tested that matches the first interface; Step S1034: input the signal value to the second interface, and drive the design under test to continue running until the next clock cycle edge.

[0071] In the embodiment of the present invention, during the process of program control, the control end can obtain the signal value of the first interface in each subprogram; the first interface is any interface in the subprogram.

[0072] The signal value of the first interface in each subroutine is used to drive the design under test. The signal value can be transmitted to the design under test through the interface of the design under test, thereby controlling the operation of the design under test.

[0073] After acquiring the signal value of the first interface in each subroutine, the control end may also determine the second interface matching the first interface in the design to be tested.

[0074] Different mapping methods may be used to map the first interface to the second interface, thereby determining the second interface that matches the first interface in the design to be tested.

[0075] Exemplarily, in an embodiment of the present invention, two groups of interfaces in the design to be tested, such as AXI4 and Tilelink, can be obtained separately first, that is, the interface of the design to be tested is determined, and the AXI4 interface needs to be driven by each interface in each subroutine. At this time, it is necessary to define a virtual AXI4 interface and let the verification code (each interface in each subroutine) drive this virtual AXI4 interface.

[0076] Exemplarily, the process of matching the first interface with the second interface of the design to be tested may include: obtaining the name of the first interface in the first subprogram and capturing the name of the design to be tested. When the name of the design to be tested only has a common prefix more than the name of the first interface in the first subprogram, prefix mapping may be used to match the first interface with the second interface of the design to be tested.

[0077] For example, when the design to be tested has a common prefix more than the name in the first interface in the first subroutine, such as io_a, io_b, io_cin, io_sum, io_cout, in this case, the prefix io_ can be specified as the mapping method to map to the DUT, that is, when the common prefix can be extracted, io_ is directly used as the mapping method, so that a is connected to io_a, b is connected to io_b, cin is connected to io_cin, sum is connected to io_sum, and cout is connected to io_cout. When the prefix of the new design to be tested is not io_, but inout_a, inout_b, inout_cin, inout_sum, inout_cout, inout_ is used for mapping in order to be able to connect. That is, by identifying this prefix, the same one behind it is connected to it.

[0078] Alternatively, the process of matching the first interface with the second interface of the design to be tested may include: obtaining the name of the first interface in the first subroutine and capturing the name of the design to be tested. When the name of the design to be tested can be expressed by a regular expression, a regular expression mapping can be used to match the first interface with the second interface of the design to be tested.

[0079] Exemplarily, this mapping method can be used when the signal name in the DUT can be matched by a regular expression, and the captured name can match the name in the interface. For example, the above can be matched with the regular expression r"io_(.*)", and the characters captured by the brackets just match the name in the interface. If there are multiple capture groups, they are linked into a string in order and then matched. Among them, regular expression mapping refers to writing a matching rule, and then matching the first interface in the first subroutine with the second interface of the design to be tested. The "io_(.*)" matching pattern is to capture the (signal) after io_.

[0080] Alternatively, the process of matching the first interface with the second interface of the design to be tested may include: obtaining the name of the first interface in the first subroutine, while capturing the name of the design to be tested, establishing a one-to-one mapping relationship by passing in a dictionary, and then matching the first interface with the second interface of the design to be tested.

[0081] For example, a one-to-one mapping relationship is established by passing in a dictionary. This is consistent with the traditional connection method (but the mapping can be achieved through multiple layers of nesting, the dictionary contains prefix mapping, and the prefix mapping includes regular expression mapping), and the mapping is completed through the dictionary in the first interface in the first subroutine. For example, {"a": "io_a", "b": "io_b", "cin": "io_cin", "cout": "io_cout"}.

[0082] After determining the second interface in the design under test that matches the first interface, the control end may also input a signal value to the second interface and drive the design under test to continue running until the next clock cycle edge.

[0083] Among them, the port can be assigned to the design under test, that is, each subroutine transmits the data required for the operation of the design under test to the design under test, and then the design under test can be controlled through each interface in each subroutine.

[0084] In an optional embodiment of the present invention, the program scheduler schedules the subprograms in sequence according to the execution order of each subprogram in the test program when receiving the control signal sent by the control terminal, which may specifically include the following steps: Step S1021, when receiving the control signal sent by the control end, the program scheduler schedules the first subprogram in the test program according to the execution order of each subprogram in the test program, and monitors the running status of the first subprogram.

[0085] Step S1022: When the first subprogram runs to a preset position, the program scheduler schedules the second subprogram; wherein the second subprogram is the next subprogram corresponding to the first subprogram.

[0086] In an embodiment of the present invention, during the process of program control, the program scheduler, upon receiving a control signal sent by the control end, schedules the first subprogram in the test program according to the execution order of each subprogram in the test program and monitors the running status of the first subprogram.

[0087] Exemplarily, in the embodiment of the present invention, the first subroutine is any subroutine in the scheduling test program, and may be the first subroutine in the scheduling test program, or the last subroutine, or an intermediate subroutine in the scheduling test program, which is not limited in the embodiment of the present invention.

[0088] The program scheduler determines the execution progress of the first subprogram by monitoring the running status of the first subprogram, and schedules the second subprogram when the first subprogram runs to a preset position; wherein the second subprogram is the next subprogram corresponding to the first subprogram.

[0089] The second subroutine is the next subroutine corresponding to the first subroutine. For example, refer to Figure 3 , when the first subroutine is the first subroutine (subroutine 1), the second subroutine is the next subroutine (subroutine 2) adjacent to the first subroutine; when the first subroutine is an intermediate subroutine in the scheduling test program, the second subroutine is the next subroutine adjacent to the intermediate subroutine. For example, if the first subroutine is subroutine 2, the second subroutine is subroutine 3, which is not limited in the embodiments of the present invention.

[0090] In an embodiment of the present invention, when the program scheduler receives a control signal sent by the control end, it schedules the subprograms in sequence according to the execution order of each subprogram in the test program. Each time a subprogram in the test program is scheduled, the running status of the subprogram can be monitored. When the subprogram runs to a preset position, the scheduling process starts for the next subprogram adjacent to the subprogram.

[0091] In the embodiment of the present invention, before the control end reads the clock signal of the design to be tested, the following steps may also be included: According to the test logic of the test program, a waiting function is added in the preset position of each subroutine; the waiting function is used to pause the running of the subroutine.

[0092] In the embodiment of the present invention, the test logic of the test program refers to the core part of the test program, which is used to check the running results and determine whether the test is passed. By designing a well-designed test logic, the functional correctness of the DUT can be effectively verified.

[0093] The wait function refers to an execution code used to pause the running of a subroutine. When each subroutine runs to the wait function, the subroutine will stop running.

[0094] In the embodiment of the present invention, before the control end reads the clock signal of the design to be tested, the control system may also add a waiting function in a preset position of each subroutine according to the test logic of the test program.

[0095] For example, refer to Figure 3 The waiting function refers to the Await function added in each subroutine. When the program scheduler schedules subroutine 1, when subroutine 1 runs to the position of the Await function, it will stop here.

[0096] In summary, an embodiment of the present invention provides a program control method, which is applied to a control system, wherein the control system includes a control end and a program scheduler. During the program control process, the program scheduler schedules the subroutines in sequence according to the execution order of each subroutine in the test program when receiving a control signal sent by the control end; when each subroutine in the test program runs to a preset position, a wake-up signal is sent to the control end; at the same time, the control end reads the clock signal of the design to be tested, starts to drive the design to be tested, and when the clock signal reaches a clock cycle edge, pauses the operation of the design to be tested, and sends a control signal to the program scheduler; that is, the scheduling of the subroutines by the program scheduler and the driving of the design to be tested by the control end are executed alternately, and then the hardware clock can be controlled and parallel operations can be completed through the software programming language, thereby improving the program control efficiency.

[0097] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0098] Device Embodiment Reference Figure 4 , shows a structural block diagram of a program control device of the present invention, the device is applied to a control system, the control system includes a control terminal and a program scheduler, the device includes: A reading module 301 is used to read the clock signal of the design to be tested; A sending module 302, configured to suspend the operation of the design under test and send a control signal to the program scheduler when the clock signal reaches a clock cycle edge; The scheduling module 303 is used to schedule the subroutines in the test program in order of execution upon receiving the control signal sent by the control terminal; The sending module is used to send a wake-up signal to the control end when each subroutine in the test program runs to a preset position; The driving module 304 is used to drive the design under test to continue running until the next clock cycle edge when receiving the wake-up signal.

[0099] Optionally, the device further comprises: An acquisition module, configured to acquire a first operation result of the design to be tested when the clock signal reaches an edge of a clock cycle; and acquire a second operation result corresponding to the at least one subroutine when at least one subroutine runs to a preset position; A matching module, used for matching the first operation result with the second operation result; The determination submodule is used to determine that the design to be tested runs correctly when the first running result matches the second running result; and to determine that the design to be tested runs incorrectly when the first running result does not match the second running result.

[0100] Optionally, the driving module includes: The driving submodule is used to call the driving interface when receiving the wake-up signal, send a driving signal to the design under test, and drive the design under test to continue running until the next clock cycle edge.

[0101] Optionally, the driving module further includes: An acquisition submodule, used for acquiring a signal value of a first interface in each of the subprograms; the first interface is any interface in the subprogram; A first determination submodule, used to determine a second interface in the design to be tested that matches the first interface; An input module is used to input the signal value to the second interface and drive the design under test to continue running to the next clock cycle edge.

[0102] Optionally, upon receiving the control signal sent by the control terminal, the program scheduler sequentially schedules the subprograms according to the execution order of the subprograms in the test program, including: A first scheduling submodule, configured to schedule a first subprogram in the test program according to the execution order of each subprogram in the test program when receiving a control signal sent by the control terminal; A monitoring module, used for monitoring the running status of the first subroutine; The second scheduling submodule is used to schedule a second subprogram when the first subprogram runs to a preset position; wherein the second subprogram is the next subprogram corresponding to the first subprogram.

[0103] Optionally, before the control end reads the clock signal of the design to be tested, the method further includes: An adding module is used to add a waiting function in a preset position of each subprogram according to the test logic of the test program; the waiting function is used to pause the running of the subprogram.

[0104] In summary, an embodiment of the present invention provides a program control device. During the program control process, when the program scheduler receives the control signal sent by the control end, it schedules the subroutines in sequence according to the execution order of each subroutine in the test program; when each subroutine in the test program runs to a preset position, a wake-up signal is sent to the control end; at the same time, the control end reads the clock signal of the design to be tested, starts to drive the design to be tested, and when the clock signal reaches a clock cycle edge, the operation of the design to be tested is paused, and a control signal is sent to the program scheduler; that is, the scheduling of the subroutines by the program scheduler and the driving of the design to be tested by the control end are executed alternately, and then the hardware clock can be controlled and parallel operations can be completed through the software programming language, thereby improving the program control efficiency.

[0105] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0108] Reference Figure 5 , is a structural block diagram of an electronic device for program control provided by an embodiment of the present invention. Figure 5 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the program control method of the aforementioned embodiment.

[0109] The processor may be a central processing unit (CPU), a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0110] The communication bus may include a path to transmit information between the memory and the communication interface. The communication bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0111] The memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or may be an electrically erasable programmable read-only memory (EEPROM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0112] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The program control method shown.

[0113] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0114] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0115] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0116] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0117] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable terminal device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0118] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0119] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0120] The program control method, device, electronic device and storage medium provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A program control method, characterized in that: Applied to a control system, the control system includes a control terminal and a program scheduler, and the method includes: The control end reads the clock signal of the design to be tested, and when the clock signal reaches a clock cycle edge, suspends the operation of the design to be tested, and sends a control signal to the program scheduler; The program scheduler schedules the subprograms in the test program in order according to the execution order of the subprograms in the test program when receiving the control signal sent by the control end; and sends a wake-up signal to the control end when all the subprograms in the test program run to a preset position; When receiving the wake-up signal, the control end drives the design under test to continue running until the next clock cycle edge.

2. The method according to claim 1, characterized in that The method further comprises: When the clock signal reaches a clock cycle edge, obtaining a first operation result of the design to be tested; When at least one subprogram runs to a preset position, obtaining a second running result corresponding to the at least one subprogram; Matching the first operation result with the second operation result; When the first operation result matches the second operation result, determining that the design to be tested operates correctly; When the first operation result does not match the second operation result, it is determined that the design under test has an operation error.

3. The method according to claim 1, characterized in that When the control end receives the wake-up signal, driving the design under test to continue running until the next clock cycle edge includes: When receiving the wake-up signal, the control end calls the driving interface to send a driving signal to the design under test, so as to drive the design under test to continue running until the next clock cycle edge.

4. The method according to claim 1, characterized in that: The driving the design under test to continue running until the next clock cycle edge includes: Acquire the signal value of the first interface in each of the subroutines; the first interface is any interface in the subroutines; Determining a second interface in the design to be tested that matches the first interface; The signal value is input to the second interface, and the design under test is driven to continue running until the next clock cycle edge.

5. The method according to claim 1, characterized in that The program scheduler, upon receiving the control signal sent by the control terminal, sequentially schedules the subprograms according to the execution order of the subprograms in the test program, including: The program scheduler, upon receiving the control signal sent by the control terminal, schedules the first subprogram in the test program according to the execution order of each subprogram in the test program, and monitors the running status of the first subprogram; The program scheduler schedules a second subprogram when the first subprogram runs to a preset position; wherein the second subprogram is a next subprogram corresponding to the first subprogram.

6. The method according to claim 1, characterized in that Before the control terminal reads the clock signal of the design to be tested, the method further includes: According to the test logic of the test program, a waiting function is added in a preset position of each subprogram; the waiting function is used to pause the running of the subprogram.

7. A program control device, characterized in that: Applied to a control system, the control system includes a control terminal and a program scheduler, and the device includes: A reading module, used to read the clock signal of the design under test; A sending module, used for pausing the operation of the design to be tested and sending a control signal to the program scheduler when the clock signal reaches a clock cycle edge; A scheduling module, for scheduling the subroutines in the test program in sequence according to the execution order of the subroutines in the test program when receiving a control signal sent by the control terminal; The sending module is used to send a wake-up signal to the control end when each subroutine in the test program runs to a preset position; The driving module is used to drive the design under test to continue running to the next clock cycle edge when a wake-up signal is received.

8. The device according to claim 7, characterized in that The device also includes: An acquisition module, configured to acquire a first operation result of the design to be tested when the clock signal reaches an edge of a clock cycle; and acquire a second operation result corresponding to the at least one subroutine when at least one subroutine runs to a preset position; A matching module, used for matching the first operation result with the second operation result; The determination submodule is used to determine that the design to be tested runs correctly when the first running result matches the second running result; and to determine that the design to be tested runs incorrectly when the first running result does not match the second running result.

9. The device according to claim 7, characterized in that The driving module comprises: The driving submodule is used to call the driving interface when receiving the wake-up signal, send a driving signal to the design under test, and drive the design under test to continue running until the next clock cycle edge.

10. An electronic device, characterized in that: The electronic device comprises a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the program control method according to any one of claims 1 to 6.

11. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the program control method according to any one of claims 1 to 6.

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