A RISC-V Instruction Set Extension Method Containing posit Format Instructions and a RISC-V Processor

Abstract

A method for extending the RISC-V instruction set including posit format instructions provided by the present invention comprises modifying the RISC-V instruction set so that the RISC-V instruction set supports posit format instructions; the modification of the RISC-V instruction set includes modifying the operation code, using a specific operation code as an identifier for the posit format instructions; using the funct3 field encoding, the funct5 field encoding or the functp field encoding to distinguish the specific types of the posit format instructions; using the rs1, rs2, and rd field encodings to represent the addresses of source operand 1, the address of source operand 2, and the destination register address respectively; using the es field encoding to select the exponent bit width of the destination operand of the posit format instructions. The present invention also provides a RISC-V processor for executing the RISC-V instruction set generated by a method for extending the RISC-V instruction set including posit format instructions.

Description

Technical Field

[0001] The present invention belongs to the technical field of RISC-V instruction set architecture, and particularly relates to a method for expanding the RISC-V instruction set including posit format instructions and a RISC-V processor. Background Art

[0002] The instruction set architecture (ISA), as the interface between software and hardware, plays a bridging role connecting the two worlds and has a fundamental impact on the performance of computer systems. It not only defines the rules for the processor to execute operations, but also is directly related to the algorithm efficiency and the utilization efficiency of hardware resources. In particular, by customizing specific application instruction sets, it is possible to optimize the operation process for professional fields such as image processing, reduce unnecessary calculation steps, and improve the processing speed and efficiency.

[0003] RISC-V, as a modern and open-source reduced instruction set architecture, has become an ideal platform for innovation with its modular and highly scalable design. It not only integrates the successful elements of previous ISAs, but also avoids historical legacy problems, provides basic instruction sets (such as RV32I and RV64I for 32-bit and 64-bit environments) and diverse extended instruction sets (covering multiplication and division, atomic operations, floating-point operations, compressed instructions, etc.), and deliberately reserves space for custom instructions, greatly enhancing its ability to adapt to different application scenarios.

[0004] The posit format is a numerical representation method that is more flexible and accurate than the traditional IEEE 754 floating-point number. Due to its higher numerical density, smaller rounding error, and wider dynamic range, it has become an emerging choice in the fields of embedded systems and low-power computing. Especially in resource-constrained scenarios, such as Internet of Things devices, signal processing, and machine learning inference, the posit format exhibits significant advantages. Since existing mainstream processor architectures are usually optimized for the IEEE 754 format, the hardware support for the posit format is not yet perfect.

[0005] At the same time, the CORDIC (Coordinate Rotation Digital Computer) algorithm is an iterative algorithm applicable to transcendental function calculations (such as trigonometric functions, logarithms, exponents) and complex operations such as square roots. Its high efficiency and hardware friendliness make it one of the main methods for embedded processors to implement transcendental functions. Traditional CORDIC algorithms are mostly based on the IEEE754 floating-point format, and expanding it to support the computational requirements of the posit format requires re-designing the data path and operation mechanism, which is not suitable for application.

[0006] Therefore, it is necessary to develop a method for extending transcendental functions and data conversion instruction sets in Posit format based on the RISC-V instruction set, so that embedded processors can support Posit format calculations. Summary of the Invention

[0007] The present invention provides a method for extending the RISC-V instruction set including Posit format instructions and a RISC-V processor. Through custom instruction extension, the combination of Posit format number representation and the CORDIC algorithm can not only achieve efficient transcendental function calculations, but also support efficient data conversion between IEEE 754 floating-point numbers and Posit format numbers.

[0008] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above objects or other objects, a method for extending the RISC-V instruction set including Posit format instructions provided by one technical solution of the present invention includes modifying the RISC-V instruction set so that the RISC-V instruction set supports Posit format instructions; the modification of the RISC-V instruction set includes modifying the operation code and using a specific operation code as the identifier of the Posit format instruction; using the funct3 field encoding, funct5 field encoding or functp field encoding to distinguish the specific types of Posit format instructions; using the rs1, rs2, rd field encodings to represent the addresses of source operand 1, the address of source operand 2, and the destination register address respectively; using the es field encoding to select the exponent bit width of the destination operand of the Posit format instruction.

[0010] Use the reserved custom-0 encoding field of the RISC-V instruction set as the operation code of the Posit format instruction.

[0011] The es field encoding is the 25-26 bit field of the RISC-V instruction encoding.

[0012] The types of the Posit format instructions include: Posit format number conversion instructions, Posit format number load and store instructions, and Posit transcendental function instructions; the Posit format number conversion instructions are distinguished by the funct3 field encoding, or jointly distinguished by the funct3 field encoding and the functp field encoding; the Posit format number load and store instructions use the single-precision load and store instruction encoding format of the RISC-V instruction set, and replace the operation code of the single-precision load and store instruction encoding format of the RISC-V instruction set with the operation code of the Posit format instruction; the Posit transcendental function instructions are distinguished by the funct5 field encoding.

[0013] The encoding of the funct3 field is used to distinguish the instructions for converting Posit-format numbers to single-precision floating-point numbers, converting Posit-format numbers to integer data, converting integer data to Posit-format numbers, and converting single-precision floating-point numbers to Posit-format numbers; the combined encoding of the funct3 field and the functp field is used to distinguish the instructions for converting Posit-format numbers to each other.

[0014] The encoding of the Posit-format number conversion instructions for each other also includes the es-rs and es-rd field encodings, which represent the exponent bit widths of the source operand and the destination operand respectively; the es-rd field encoding is the 25-26 bit field of the RISC-V instruction encoding, and the es-rs field encoding is the 27-28 bit field of the RISC-V instruction encoding.

[0015] If the es-rd field encoding and the es-rs field encoding of the Posit-format number conversion instruction for each other are the same, no Posit-format number conversion is required; if the es-rd field encoding and the es-rs field encoding of the Posit-format number conversion instruction for each other are different, the Posit-format number conversion is performed according to the es-rd field.

[0016] After encoding the Posit-format instructions, modify the riscv-opcodes of the compiler so that the Posit-format instructions can be recognized by the compiler, and generate machine codes containing Posit-format for the processor to execute.

[0017] The funct3 field encoding of the posit-format number conversion instruction and the funct5 field encoding of the posit transcendental function instruction are both written in Gray code; the funct5 field encoding of the posit-format number conversion instruction and the funct3 field encoding of the posit transcendental function instruction are both 0.

[0018] Another technical solution of the present invention provides a RISC-V processor for executing the RISC-V instruction set generated by the above-described RISC-V instruction set extension method including posit format instructions. The RISC-V processor includes at least a decoding module, an execution module, and a register file. The decoding module customizes a posit format instruction decoding data path for decoding posit format instructions. The execution module includes a posit format number execution unit, and the posit format number execution unit includes a posit processing unit and a CORDIC unit. The register file includes posit format number registers. The decoding module parses the Posit format instruction to generate function control logic signals, and fetches the Posit format number from the posit format number registers to the execution module according to the control logic signals. The posit format number conversion unit in the posit processing unit is used to perform type conversion of the posit format number. The CORDIC unit performs different transcendental function operations on the input posit format number.

[0019] The posit format number execution unit further includes the Posit decoder and the Posit encoder. The posit processing unit and the CORDIC unit share the same Posit decoder and Posit encoder. The Posit decoder decomposes the input Posit format number into an exponent, a mantissa, and a sign bit. The posit processing unit and the CORDIC unit respectively receive the output results of the Posit decoder. The operation results of the posit processing unit and the CORDIC unit are selected by the multiplexer and output to the Posit encoder, and the Posit encoder converts the exponent, mantissa, and sign bit after operation into a posit format number. The multiplexer, the posit processing unit, and the CORDIC unit are all controlled by two different enable signals.

[0020] The CORDIC unit includes 2 Posit multiply-accumulate units, a Posit multiplication unit, a Posit addition unit, and a storage unit for CORDIC algorithm iterative calculation. The storage unit stores angles, status factors, and scale factors, and gradually calls them during the calculation process.

[0021] The Posit multiplication unit is a configurable Posit multiplication unit, which selects Posit multipliers with different bit widths according to different bit width parameter selection signals; the multiplier bit widths of the configurable Posit multiplication unit include: 8×8 bits, 16×8 bits, 32×8 bits, 16×16 bits, 32×16 bits, and 32×32 bits.

[0022] Compared with the prior art, the beneficial effects of the present invention mainly include: 1. Posit format number transcendental function instructions and Posit format number type conversion instructions are added to the RISC-V instruction set architecture, filling the gap in the Posit format transcendental function instruction set. At the same time, instructions for converting Posit numbers to other types of data and instructions for converting Posit format numbers with different precisions are provided. The designed instructions are comprehensive and concise, which is beneficial to the subsequent supplement of Posit format instructions.

[0023] 2. The Posit CORDIC instruction set of the present invention greatly compresses the number of instructions for Posit transcendental functions; the designed instructions use Gray code encoding to improve the reliability of data transmission; when designing the custom instruction encoding, the funct5 field and the funct3 field are kept at a low level for as many bits as possible to reduce the circuit power consumption.

[0024] 3. Through a unique encoding form, Posit numbers can select exponents in a small range, increasing the flexibility of precision and range during data operations, strengthening the flexibility and generality of various precision calculations. Compared with the basic RISC-V floating-point instruction set, the Posit format instructions designed by the present invention can change the data precision without changing the RISC-V instruction set, greatly improving the precision and flexibility of the processor's data operations.

[0025] 4. The posit processing unit and the CORDIC unit share the Posit encoder, the Posit decoder, and some multiply-accumulate units, reducing the processor resource overhead; at the same time, a configurable multiplication unit with multi-bit wide enable is used, and multipliers with different bit widths are reasonably used according to the mantissa bits of the Posit format number, greatly reducing the circuit power consumption.

[0026] To make the above and other purposes, features, and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0028] Figure 1 The Posit number format used in the present invention.

[0029] Figure 2 The basic architecture diagram of the RISC-V processor used in the present invention.

[0030] Figure 3 A custom instruction encoding format for Posit format number type conversion and transcendental function instructions in the present invention.

[0031] Figure 4 The encoding format of the Posit format number conversion instruction in the present invention.

[0032] Figure 5 The encoding format of the Posit format number load instruction in the present invention.

[0033] Figure 6 The encoding format of the Posit format number store instruction in the present invention.

[0034] Figure 7 The custom instruction encoding of the Posit format number type conversion instruction, load and store instructions, and transcendental function instructions in the present invention.

[0035] Figure 8 The basic architecture diagram of the Posit format number conversion unit and the Posit CORDIC unit in the present invention.

[0036] Figure 9 The basic architecture diagram of the Posit CORDIC unit in the present invention.

[0037] Figure 10 The schematic diagram of the Posit configurable multiplication unit in the present invention. Detailed implementation manners

[0038] Regarding the foregoing and other technical contents, features, and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front, or back, etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0039] Embodiment 1

[0040] Embodiment 1 provides a method for expanding the RISC-V instruction set including posit format instructions, which is characterized by modifying the RISC-V instruction set so that the RISC-V instruction set supports posit format instructions; the modification of the RISC-V instruction set includes modifying the opcode and using a specific opcode as the identifier of the posit format instruction; using the funct3 field encoding, funct5 field encoding or functp field encoding to distinguish the specific types of posit format instructions; using the rs1, rs2, and rd field encodings to represent the addresses of source operand 1, the address of source operand 2, and the destination register address respectively; using the es field encoding to select the exponent bit width of the destination operand of the posit format instruction.

[0041] The technical solution in Embodiment 1 will be specifically explained below in conjunction with the accompanying drawings.

[0042] A method for expanding the RISC-V instruction set including posit format instructions provided by Embodiment 1 is based on the basic architecture of the RISC-V instruction set and modifies the RISC-V instruction set so that it can support Posit format number type conversion instructions, Posit format number load and store instructions, and Posit format transcendental function instructions.

[0043] As Figure 1 shown, the specific representation form of a 32-bit (bits 0-31) Posit format number, where the s field represents the positive or negative of the Posit format number, the regime field is the scale bit representing the dynamic range of the exponent, the exponent field represents the exponent, and the fraction field represents the mantissa.

[0044] When designing the instruction set for Posit format numbers in Embodiment 1, according to the existing framework of RISC-V and in combination with the usual floating-point instruction set design structure, the existing RISC-V instruction set architecture is modified so that it can be compatible with Posit format instructions.

[0045] The specific modifications include: 1. Modifying the RISC-V instruction set opcode (i.e., Figure 3 the opcode code in it) for the identification of posit format instructions. 2. Using funct5, funct3, and functp to identify the specific instruction types. 3. Using rs1, rs2, and rd as the addresses of source operand register number 1, source operand register number 2, and destination register address respectively. 4. Adding a new es field to select the exponent bit width of the Posit format number operand.

[0046] 1. Modifying the RISC-V instruction set opcode

[0047] Use the custom-0 encoding field reserved by the RISC-V instruction set as the opcode of the posit format instruction (i.e., Figure 3 the opcode in). The posit format instruction is not included in the RISC-V base instruction set. Therefore, the space specifically prepared for the custom instruction set in the RISC-V instruction set is used, and the custom-0 field is used for the encoding design of the posit format custom instruction set (the custom-0 field is used as the opcode). This does not affect the decoding path of the floating-point instruction set, and at the same time makes the decoding of the posit format instruction more convenient, enabling unified design and making the posit format hardware module separately configurable, which conforms to the advantages of the modular configuration of the RISC-V instruction set.

[0048] 2. Use funct5, funct3, and functp to identify the specific instruction type

[0049] The types of posit format instructions include: posit format number conversion instructions, posit format number load and store instructions, and posit transcendental function instructions.

[0050] 2.1. posit format number conversion instructions

[0051] The posit format number conversion instructions include the posit format number to single-precision floating-point number instruction, the posit format number to integer data instruction, the integer data to posit format number instruction, the single-precision floating-point number to posit format number instruction, and the posit format number mutual conversion instruction. The posit format number conversion instructions are distinguished by the funct3 field encoding, or jointly distinguished by the funct3 field encoding and the functp field encoding.

[0052] Figure 3 For general posit format number conversion instructions, they are distinguished by the funct3 field encoding, and include the posit format number to single-precision floating-point number instruction Pcvt.s.p ( Figure 7 visible), the posit format number to integer data instruction Pcvt.w.p, the integer data to posit format number instruction Pcvt.p.w, and the single-precision floating-point number to posit format number instruction Pcvt.p.s.

[0053] Figure 4 For the encoding format of the posit format number mutual conversion instruction Pcvt.p.p, the posit format number mutual conversion instruction is used for the conversion of posit format numbers with different precisions. The Pcvt.p.p instruction is identified by the combined use of the functp field encoding and the funct3 field encoding. Among them, Figure 4The instruction encoding for converting between posit format numbers includes the es-rd field encoding and the es-rs field encoding, which represent the exponent bit widths of the destination operand and the source operand respectively. If the es-rd field encoding and the es-rs field encoding are the same, indicating that the exponents of the source operand and the destination operand are the same, no conversion is required. If the bit widths are different, data format conversion needs to be performed according to the specific es-rd field encoding. The specific conversion is executed by the hardware circuit, and only the improvement of the instruction set architecture is introduced here.

[0054] 2.2. posit format number load and store instructions

[0055] See Figure 5 and Figure 6 The posit format number load and store instructions use the single-precision load and store instruction encoding format of the RISC-V instruction set (the existing instruction types in the RISC-V instruction set architecture), and replace the opcode (opcode code) of the single-precision load and store instruction encoding format of the RISC-V instruction set with the posit format instruction opcode (i.e., the custom-0 encoding field). In this way, at the instruction fetch stage, it can be determined according to the opcode type that the load and store instructions are used for posit format numbers. See Figure 7 For the posit format number load instruction Plw, a posit data value is loaded from the data storage area into the posit format number register. The posit format number store instruction Psw stores a Posit value in the Posit register into the data memory.

[0056] 2.3. posit transcendental function instructions

[0057] The posit transcendental function instructions are distinguished by the funct5 field encoding. See Figure 7 The types of posit transcendental function instructions are Psin, Pcos, Ptan, Partan, Psinh, Pcosh, Ptanh, Partanh, Pexp, Pln.

[0058] Combined with Figure 7 For the above instructions, except for the load and store instructions, other data are all single-operand instructions, so the source operand 2 (rs2) is all 0.

[0059] Among them, the funct3 field of the Posit format number conversion instruction is written in Gray code, and the funct5 field of the Posit format number transcendental function instruction is written in Gray code, which greatly improves the stability of the circuit and reduces the probability of misdecoding. At the same time, the funct5 field of the Posit format number conversion instruction and the funct3 field of the transcendental function instruction are all set to 0, reducing the switching frequency during circuit operation. By this method, the reliability of the processor decoding is greatly improved and the power consumption during processor operation is reduced.

[0060] 3. Use rs1, rs2, and rd as the addresses of source operand register number 1, source operand register number 2, and destination register respectively

[0061] When the RISC-V processor processes Posit format instructions, the decoding module generates corresponding control signals, and at the same time reads the operands from the registers according to the register addresses rs1 and rs2, and the destination register receives the operation result according to the rd address.

[0062] 4. Add a new es field

[0063] In the 32-bit instruction field encoding, use the [26:25] bits as the es field to make the Posit format number optional exponent bit width, greatly increasing the flexibility and selectivity of data operation precision and range. Its dynamic range characteristics can effectively cover values from very small to very large, and is more extensive in the representation range than traditional RISC-V floating-point instructions. Since there is no NaN (abbreviation for "Not a Number", a special value in the IEEE 754 floating-point standard) in the Posit format number, it reduces processing complexity and error propagation, and can greatly improve computing performance, resource efficiency, and result credibility in edge computing and approximate computing scenarios.

[0064] After encoding the Posit format instructions, modify the riscv-opcodes of the compiler so that it can be recognized by the compiler, and then generate the machine code containing Posit format instructions, improving the precision and flexibility of data operation. The addition of Posit transcendental instructions reduces the number of instructions for ordinary Posit instructions to execute transcendental functions and improves the operation efficiency.

[0065] Embodiment 2

[0066] Embodiment 2 provides a RISC-V processor for executing the RISC-V instruction set generated by the RISC-V instruction set extension method including posit format instructions in Embodiment 1. The RISC-V processor includes at least a decoding module, an execution module, and a register file. The decoding module customizes the data path for decoding posit format instructions for decoding posit format instructions. The execution module includes a posit format number execution unit, and the posit format number execution unit includes a posit processing unit (abbreviated as PPU, that is, the PPU module in Figure 2 ), and a CORDIC unit. The register file includes a posit format number register (abbreviated as PRF, that is, the PRF module in Figure 2 ). The decoding module parses the Posit format instructions to generate function control logic signals, and fetches the Posit format numbers from the posit format number register to the execution module according to the function control logic signals. The posit format number conversion unit in the posit processing unit is used to perform the type conversion of the posit format numbers. The CORDIC unit performs different transcendental function operations on the input posit format numbers.

[0067] The following further explains the RISC-V processor in Embodiment 2 with reference to the accompanying drawings.

[0068] As Figure 2 shown, it is a framework diagram of the RISC-V processor of the present invention, which is a 5-stage pipeline sequential single-issue processor core. The processor core includes the following structures: program counter, instruction memory, decoding module, execution module, load / store module, register file, and data memory.

[0069] Among them, the program counter is responsible for generating the instruction address according to the current condition, and the instruction memory fetches instructions according to the instruction address; the decoding module is responsible for decoding the 32-bit data fetched, obtaining the source operand address, destination operand address and instruction control signals. The instruction control signals include load / store signals, ALU control signals, jump control signals, FPU control signals, Posit and CORDIC control signals. At the same time, according to the source operand and destination operand addresses, the data at the corresponding addresses are fetched from the corresponding register files. Integer instructions are fetched from the general-purpose registers, floating-point type instructions are fetched from the floating-point registers, and Posit type instructions are fetched from the Posit register file; in the execution stage, according to the corresponding instruction control signals decoded, arithmetic operations are performed on the corresponding data, and the final result is selected through a multiplexer, and the finally output result is transmitted to the load / store module; if the instruction is related to load / store, the instruction memory interacts with the register file, and the register file includes the general-purpose register file, floating-point register file, Posit register file. If not, the data is transmitted to the write-back stage.

[0070] The following starts from the processing process of each stage of the RISC-V processor and makes a detailed explanation of the RISC-V processor in Embodiment 2.

[0071] 1. Instruction fetch stage

[0072] The program counter starts to generate the instruction address and reads the 32-bit instruction at the current address in the instruction memory.

[0073] 2. Decoding stage

[0074] The 32-bit instruction fetched from the instruction fetch stage is sent to the decoding module through the instruction fetch and decode register for instruction decoding operations. According to the differences in the opcode, funct5, funct3, functp, and es fields of the posit format instruction, the decoding module generates the control signals for the corresponding instruction. At the same time, according to the register addresses rs1 and rs2, the operands are read from the registers, and the destination register receives the operation result according to the rd address. es represents the width of the exponent bit of the Posit format number, and the default value is 00, corresponding to a Posit format data exponent bit width of 2 bits. The posit format number exponent bit widths corresponding to the encoding values of the es, es-rd, and es-rs fields are shown in Table 1 below.

[0075] Table 1: Correspondence table of encoding values of es, es-rd, and es-rs fields and posit format number exponent bit widths

[0076]

[0077] 3. Execution unit

[0078] The execution module in Embodiment 2 is designed with a Posit format number execution unit, which executes different instruction operations together with the ALU calculation unit, MUL calculation unit, etc. in the conventional execution module of the RISC-V processor. The Posit format number execution unit includes a posit processing unit and a CORDIC unit, as shown in Figure 8 , both the posit processing unit and the CORDIC unit use a Posit decoder and a Posit encoder to improve the reuse unit and reduce circuit resource consumption. The posit processing unit includes a posite data conversion unit.

[0079] Specifically: as shown in Figure 8 , the input Posit format number enters the Posit decoder for processing, divides the 32-bit Posit number into three parts: exponent, mantissa, and sign bit, judges whether to perform Posit data conversion or CORDIC calculation according to the two enable signals Pcvt-en and P-CORDIC-en, inputs to the corresponding unit for corresponding operations, and after the operations are completed, outputs the corresponding results to the Posit encoder through a data selector according to the two enable signals. The Posit encoder converts the three parts of 32-bit exponent, mantissa, and sign bit into the Posit format data form through operations.

[0080] As shown in Figure 9 is the structural diagram of the CORDIC operation unit in Posit format, which is used for CORDIC algorithm iterative operations. The CORDIC unit also includes 2 Posit format multiply-accumulate units, 1 Posit multiplication unit, and 1 Posit addition unit. The 2 Posit format multiply-accumulate units are Posit format multiply-accumulate fusers, 1 Posit multiplication unit is a Posit multiplier, and 1 Posit addition unit is a Posit adder.

[0081] Specifically, when the CORDIC operation unit executes the CORDIC algorithm iterative operation, it uses the Posit multiply-accumulate module, Posit addition module, and Posit multiplication module of the CORDIC operation unit to perform operations according to the following formulas (1), (2), and (3), and at the same time angle, status factor, and scale factor are stored in the storage unit of the CORDIC operation unit and are gradually called during the calculation process.

[0082] Among them, the CORDIC unit can work in vector mode and rotation mode. In the rotation mode (RotationMode), CORDIC rotates an initial vector to a specified angle. The goal is to obtain the final coordinates through a series of rotations; in the vector mode (Vector Mode), CORDIC is mainly used to calculate the synthesis result of two known vectors. It can calculate the coordinates (x, y) of a given vector and its included angle with the reference axis, and the calculated polar coordinates (r, ), where r is the modulus of the vector, is the angle.

[0083] The iterative calculation formula of the generalized CORDIC is as follows:

[0084]

[0085]

[0086]

[0087]

[0088] Among them, when the CORDIC operation is in rotation mode, ; when the CORDIC operation is in vector mode, ; when , it is applicable to circular coordinates; when m = 0, it is applicable to linear coordinates; when m = -1, it is applicable to hyperbolic coordinates. In the above formula, and are the coordinates of each iteration, is the cumulative value of the rotation angle, is the rotation direction (taking 1 or -1), indicating clockwise or counterclockwise rotation, is the angle of the i-th step of rotation.

[0089] As shown in Figure 10, it is a configurable Posit multiplication unit. Due to the particularity of Posit format numbers, the mantissa results that appear in the Posit decoding stage include different bit-width forms. The present invention selects signals according to different bit-width parameters. When performing Posit multiplication or multiply-accumulate operations on the CORDIC unit, different bit-width Posit multipliers can be selected according to the different mantissa bit-widths, greatly reducing the circuit power consumption, and at the same time conforming to the characteristic that the bit-width of the Posit data mantissa varies after decoding. The Posit configurable multiplication unit includes 6 configurable multiplication units with different bit-widths of 8×8, 16×8, 32×8, 16×16, 32×16, and 32×32 bits. After the mantissa bit-width result appears in the Posit decoder, the bit-width of the Posit configurable multiplication unit is configured according to the mantissa bit-width result, efficiently utilizing the circuit resources.

[0090] In the execution stage, according to the control signals generated in the decoding stage, the corresponding data enters different execution units. Among them, the posit processing unit is responsible for performing the conversion between Posit numbers and single-precision floating-point numbers and integers, and the CORDIC unit is responsible for calculating the transcendental functions of Posit numbers. At the end of the execution stage, there is a multiplexer. Since the execution stage includes execution units such as ALU, FPU, and Posit, all of which generate operation results, a multiplexer is added at the end of the execution stage to select the correct output result through the control signals in the decoding stage.

[0091] 4. Load and Store Stage

[0092] If it is a load / store instruction, it interacts with the data memory. If it is not a load / store instruction, the data is output to the register file through the pipeline register, and different register files are selected according to the data type. The register file includes the general-purpose register file GPR, the floating-point register file FPR, and the Posit register file PRF.

[0093] The above has introduced in detail a method for expanding the RISC-V instruction set including posit format instructions and a RISC-V processor provided by the present invention. In this article, specific examples are used to illustrate the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for expanding the RISC-V instruction set including posit format instructions, characterized in that, Including modifying the RISC-V instruction set so that the RISC-V instruction set supports posit format instructions; The modification of the RISC-V instruction set includes modifying the opcode and using a specific opcode as the identifier for posit format instructions; Using the funct3 field encoding, funct5 field encoding, or functp field encoding to distinguish the specific types of posit format instructions; Using the rs1, rs2, and rd field encodings to represent the addresses of source operand 1, source operand 2, and the destination register address respectively; Using the es field encoding to select the exponent bit width of the destination operand of posit format instructions.

2. A method for expanding the RISC-V instruction set including posit format instructions according to claim 1, characterized in that Using the reserved custom-0 encoding field in the RISC-V instruction set as the opcode for posit format instructions.

3. A method for expanding the RISC-V instruction set including posit format instructions according to claim 1, characterized in that, The es field encoding is the 25-26 bit field of the RISC-V instruction encoding.

4. A method for expanding the RISC-V instruction set including posit format instructions according to claim 1, characterized in that The types of the posit format instructions include: posit format number conversion instructions, posit format number load and store instructions, and posit transcendental function instructions; The posit format number conversion instructions are distinguished by the funct3 field encoding, or jointly by the funct3 field encoding and the functp field encoding; The posit format number load and store instructions use the encoding format of the single-precision load and store instructions in the RISC-V instruction set, and replace the opcode of the encoding format of the single-precision load and store instructions in the RISC-V instruction set with the opcode of the posit format instructions; The posit transcendental function instructions are distinguished by the funct5 field encoding.

5. A method for expanding the RISC-V instruction set including posit format instructions according to claim 4, characterized in that, Distinguishing the Posit format number to single-precision floating-point number instruction, Posit format number to integer data instruction, integer data to Posit format number instruction, and single-precision floating-point number to Posit format number instruction by the funct3 field encoding; Jointly distinguishing the Posit format number mutual conversion instructions by the funct3 field encoding and the functp field encoding.

6. A method for extending the RISC-V instruction set including posit format instructions according to claim 5, wherein The encoding of the Posit format number mutual conversion instructions also includes the es-rs and es-rd field encodings, which represent the exponent bit widths of the source operand and the destination operand respectively; The es-rd field encoding is the 25-26 bit field of the RISC-V instruction encoding, and the es-rs field encoding is the 27-28 bit field of the RISC-V instruction encoding.

7. A method for extending the RISC-V instruction set including posit format instructions according to claim 6, characterized in that If the es-rd field encoding and the es-rs field encoding of the Posit format number mutual conversion instruction are the same, no Posit format number conversion is required; If the es-rd field encoding and the es-rs field encoding of the Posit format number mutual conversion instruction are different, the Posit format number is converted according to the es-rd field.

8. A method for expanding the RISC-V instruction set including posit format instructions according to claim 1, characterized in that After encoding the posit format instructions, modify the riscv-opcodes of the compiler so that the posit format instructions can be recognized by the compiler, and generate machine codes containing the posit format instructions for the processor to execute.

9. A method for expanding the RISC-V instruction set including posit format instructions according to claim 4, characterized in that The funct3 field encoding of the posit format number conversion instruction and the funct5 field encoding of the posit transcendental function instruction are both written in Gray code; The funct5 field encoding of the posit format number conversion instruction and the funct3 field encoding of the posit transcendental function instruction are both 0.

10. A RISC-V processor for executing a RISC-V instruction set generated by a RISC-V instruction set extension method including posit format instructions according to any one of claims 1-9, the RISC-V processor at least including a decoding module, an execution module, and a register file, characterized in that; The decoding module customizes the posit format instruction decoding data path for decoding posit format instructions; The execution module includes a posit format number execution unit, and the posit format number execution unit includes a posit processing unit and a CORDIC unit; The register file includes posit format number registers; The decoding module parses the Posit format instruction to generate function control logic signals, and fetches the Posit format number from the posit format number register to the execution module according to the control logic signals; The posit format number conversion unit in the posit processing unit is used to perform the type conversion of the posit format number; The CORDIC unit performs different transcendental function operations on the input posit format number.

11. A RISC-V processor according to claim 10, wherein, The posit format number execution unit further includes a Posit decoder and a Posit encoder; The posit processing unit and the CORDIC unit share the same Posit decoder and Posit encoder; The Posit decoder decomposes the input Posit format number into an exponent, a mantissa, and a sign bit; The posit processing unit and the CORDIC unit respectively receive the output results of the Posit decoder; The operation results of the posit processing unit and the CORDIC unit are selected by a multiplexer and output to the Posit encoder, and the Posit encoder converts the exponent, mantissa, and sign bit after the operation into a posit format number; The multiplexer, the posit processing unit, and the CORDIC unit are all controlled by two different enable signals.

12. A RISC-V processor according to claim 10, characterized in that, The CORDIC unit includes 2 Posit multiply-accumulate units, a Posit multiplication unit, a Posit addition unit, and a storage unit for iterative calculation of the CORDIC algorithm; The storage unit stores the α angle, the σ state factor, and the K scale factor, and gradually calls them during the calculation process.

13. A RISC-V processor according to claim 12, characterized in that, The Posit multiplication unit is a configurable Posit multiplication unit, and the configurable Posit multiplication unit selects Posit multipliers with different bit widths according to different bit width parameter selection signals; The bit widths of the multipliers of the configurable Posit multiplication unit include: 8×8 bits, 16×8 bits, 32×8 bits, 16×16 bits, 32×16 bits, and 32×32 bits.

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