Data processing method and device in assembly line, medium and program product

Abstract

The invention relates to the technical field of processors, and discloses a data processing method and device in an assembly line, a medium and a program product.The method comprises the steps that under the condition that a to-be-executed identifier represents that to-be-processed data exist at present, the current check value of a barrier check symbol and the current check value of a state check symbol are compared, executing the to-be-processed data under the condition that the current check value of the barrier check symbol is inconsistent with the current check value of the state check symbol; after execution of the to-be-processed data is completed, a transmission instruction is sent to the next adjacent assembly line, the stage identifier in the execution state instance is updated so as to enter the next data processing stage, and the transmission instruction is used for guiding the next assembly line to update the to-be-executed identifier in the memory barrier instance of the next assembly line. According to the technical scheme provided by one or more embodiments, the utilization rate of hardware resources can be improved.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a data processing method, device, medium and program product in a pipeline. Background Art

[0002] In the field of parallel computing of processors, in order to improve the utilization of hardware resources, a double buffer mechanism can be used to reorder the instructions of each stage in different pipelines, so that the data calculation instructions and data storage instructions of different pipelines overlap in timing, so as to allow the data calculation instructions on different pipelines to occupy hardware resources in turn as much as possible, so as to improve the utilization of hardware resources.

[0003] In order to implement the above-mentioned double buffering mechanism in the related art, it is usually necessary to modify the business code to adapt to the instruction alternation processing process under the double buffering mechanism. However, when the compiler compiles the modified business code, the instructions may be executed out of order, thereby failing to achieve the expected effect, and the utilization rate of hardware resources is still not high enough.

[0004] In view of this, a more efficient pipeline data processing method is currently needed to improve the utilization of hardware resources. Summary of the invention

[0005] The present application provides a data processing method, device, medium and program product in a pipeline, which can improve the utilization rate of hardware resources.

[0006] The first aspect of the present application provides a data processing method in a pipeline, wherein the pipeline is configured with a memory barrier instance and an execution status instance, wherein the memory barrier instance includes a pending execution identifier and a barrier check character, and the execution status instance includes a stage identifier and a state check character; the method comprises: when the pending execution identifier indicates that there is currently pending data, comparing the current check values ​​of the barrier check character and the state check character, and executing the pending data when the current check values ​​of the barrier check character and the state check character are inconsistent; after the pending data is executed, sending a transfer instruction to the next adjacent pipeline, and updating the stage identifier in the execution status instance to enter the next data processing stage, wherein the transfer instruction is used to guide the next pipeline to update the pending execution identifier in its own memory barrier instance.

[0007] The technical solution provided by this embodiment can configure each pipeline involved in the work with its own memory barrier instance and execution state instance, and both instances contain their own member parameters. Among them, for any pipeline, the data to be processed will only be executed when the check values ​​of the barrier check symbol and the state check symbol are inconsistent. After executing the data to be processed, the current pipeline will send a transfer instruction to the next adjacent pipeline and enter the next data processing stage. The next pipeline can update the pending execution flag in its own memory barrier instance according to the transfer instruction, and then it can determine whether the pending data is currently available based on the updated pending execution flag. It can be seen that before executing the data to be processed, the pipeline will perform a comparison process of the barrier check symbol and the state check symbol, and only the pipeline that meets the conditions can execute the data to be processed. This processing method can avoid the out-of-order execution of instructions and ensure that the business code can run according to the established logic. At the same time, after executing the data to be processed, the pipeline will pass the data processing process to the next adjacent pipeline to ensure that each pipeline can alternately use hardware resources for data processing. This method can accurately and stably rotate hardware resources between different pipelines, thereby greatly improving the utilization rate of hardware resources.

[0008] In one embodiment, when each pipeline is initialized, the barrier check symbols in each of the memory barrier instances are configured as a first specified value, only one of the execution state instances has a state check symbol configured as a second specified value, and the state check symbols of the remaining execution state instances are configured as the first specified value, wherein the first specified value and the second specified value are different values.

[0009] In this embodiment, the member parameters in the memory barrier instance and the execution state instance of each pipeline can be initialized and configured. Among them, only the state check symbol of one execution state instance will be configured as the second specified value, and the state check symbols of the other execution state instances will be configured as the first specified value that is the same as the barrier check symbol. In this way, in the same time period, only one pipeline will meet the condition that the check values ​​of the barrier check symbol and the state check symbol are inconsistent, and the pipeline that meets this condition will enter the data processing flow. In this way, for the same hardware resource, only one pipeline will occupy the hardware resource in the same time period, and after the pipeline executes the data to be processed, it will rotate the hardware resource to the next adjacent pipeline by passing instructions. This processing method can rotate the hardware resources in different pipelines in an orderly manner, and at the same time, it can avoid the situation where different pipelines grab hardware resources from each other in the same time period, thereby improving the stability of data processing.

[0010] In one embodiment, the method further includes: if the pending execution flag indicates that there is currently no data to be processed, resetting the value of the pending execution flag and flipping the current value of the barrier check symbol to another different value, wherein the pending execution flag after resetting the value indicates that there is currently data to be processed.

[0011] In this embodiment, if the pending execution flag indicates that there is currently no data to be processed, it is necessary to reset the pending execution flag and flip the barrier check symbol. The purpose of this processing is that the reset pending execution flag can indicate that there is currently data to be processed, so that the subsequent check value comparison process between the barrier check symbol and the status check symbol can be performed; and by flipping the barrier check symbol, it can be ensured that only one pipeline will meet the data processing conditions in the same period of time, thereby being able to stably rotate hardware resources.

[0012] In one embodiment, sending a transfer instruction to the next adjacent pipeline includes: identifying the pipeline identifier of the current pipeline and incrementally updating the pipeline identifier; obtaining the total number of pipelines currently participating in the work, and using the incrementally updated pipeline identifier to perform modulo processing on the total number to obtain the target identifier of the next adjacent pipeline; sending a transfer instruction to the pipeline having the target identifier.

[0013] In this embodiment, the target identifier of the next pipeline can be accurately determined by the remainder algorithm, and the transfer instruction can be accurately sent based on the target identifier, thereby ensuring the accuracy and stability of data processing.

[0014] In one embodiment, sending a transfer instruction to an adjacent next pipeline includes: identifying a data processing stage currently represented by the stage identifier, and sending a transfer instruction to the same data processing stage in the next pipeline.

[0015] In this embodiment, since the pipeline usually includes multiple different data processing stages, after the current pipeline completes data processing in the current data processing stage, it should send a transfer instruction to the same data processing stage of the next pipeline. This ensures that transfer instructions can be sent back and forth between the same data processing stages, does not cause disorder in the data processing stages, and improves the accuracy and stability of data processing.

[0016] In one embodiment, after updating the stage identifier in the execution state instance, the method further includes: determining whether the updated stage identifier represents that the next data processing stage returns to the initial stage; if not, after entering the next data processing stage, retaining the updated stage identifier and maintaining the value of the state check symbol unchanged; if so, after returning to the initial stage, resetting the stage identifier and flipping the current assignment of the state check symbol to another different value.

[0017] In this embodiment, when the last data processing stage completes data processing, the process will return to the initial stage. When returning to the initial stage, the stage identifier needs to be reset to ensure that the stage identifier corresponds to the actual data processing stage. At the same time, the state check symbol needs to be flipped to ensure that only one pipeline meets the data processing conditions in the same period, so that the hardware resources can be rotated stably.

[0018] In one embodiment, the method further includes: when the current check values ​​of the barrier check character and the state check character are consistent, maintaining a waiting state until the check values ​​of the barrier check character and the state check character are changed to be inconsistent, and then executing the data to be processed.

[0019] In this embodiment, if the check values ​​of the barrier check character and the state check character are consistent, the current pipeline cannot process data and needs to remain in a waiting state. This ensures that only one pipeline occupies hardware resources in the same period, and the other pipelines can be in a waiting state, thereby rotating hardware resources in different pipelines in an orderly manner, and avoiding different pipelines from competing for hardware resources in the same period, thereby improving the stability of data processing.

[0020] On the other hand, the present application further provides a data processing device in a pipeline, wherein the pipeline is configured with a memory barrier instance and an execution state instance, wherein the memory barrier instance includes a pending execution identifier and a barrier check symbol, and the execution state instance includes a stage identifier and a state check symbol; the device comprises: a comparison execution unit, configured to compare the current check values ​​of the barrier check character and the state check character when the to-be-executed identifier indicates that there is currently to-be-processed data, and to execute the to-be-processed data when the current check values ​​of the barrier check character and the state check character are inconsistent; An instruction transfer unit is used to send a transfer instruction to the next adjacent pipeline after the execution of the data to be processed is completed, and to update the stage identifier in the execution status instance to enter the next data processing stage, wherein the transfer instruction is used to guide the next pipeline to update the to-be-executed identifier in its own memory barrier instance.

[0021] On the other hand, the present application also provides an electronic device, including: a memory storing computer instructions; and at least one processor for executing the computer instructions in the memory to execute the data processing method in the pipeline in the above-mentioned embodiment.

[0022] On the other hand, the present application further provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the data processing method in the pipeline in the above-mentioned embodiment.

[0023] On the other hand, the present application further provides a computer program product, including computer instructions, which, when executed by a processor, enable the processor to execute the data processing method in the pipeline in the above-mentioned embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 is a schematic diagram of a double buffer mechanism in the related art; Figure 2 A flowchart of a data processing method in a pipeline provided by one embodiment of the present application; Figure 3 A schematic diagram of a data processing process of two pipelines provided for an embodiment of the present application; Figure 4 A schematic diagram of a data processing timing provided for an embodiment of the present application; Figure 5 A schematic diagram of functional modules of a data processing device in a pipeline provided by one embodiment of the present application; Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​can be based on additional conditions or beyond the described values ​​in practice.

[0028] See also Figure 1 In the related art, the instructions at each stage in the pipeline can be Figure 1 The data computing instructions are rearranged in the manner shown, so that the data computing instructions overlap with the data loading instructions and the data storage instructions in timing. In this way, after processing the data computing instructions of one pipeline, the hardware resources can be used to process the data computing instructions of another pipeline without waiting for a long time, thereby improving the utilization rate of the hardware resources.

[0029] To achieve Figure 1 The instruction processing method shown in the figure requires a great deal of modification to the business code in the related technology. For example, in the loop structure, the statements of various types of instructions of different pipelines need to be listed in sequence. However, when the compiler is compiling and optimizing, it is likely to rearrange these statements, which will destroy the original execution logic of the business code and make it impossible to accurately implement Figure 1 Instruction overlap scenario shown. In addition, since instructions are executed out of order, hardware resources cannot be accurately scheduled into the expected pipeline.

[0030] The embodiment of the present application provides a data processing method in a pipeline, which can avoid a large degree of modification of the business code, but only requires inserting a small amount of formatted statements into the business code. At the same time, based on the memory barrier mechanism, it can ensure that the business code is executed in the expected order. Furthermore, it can also achieve accurate scheduling of hardware resources by controlling the member parameters in the instance.

[0031] The data processing method in the pipeline provided in the present application can be applied to an artificial intelligence processor, specifically any one of a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural network Processing Unit), a DPU (Deep learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Graphics Processing Unit).

[0032] Two classes can be pre-implemented in this application: PipelineState and PingPongPipelineBar, the functions that these two classes can achieve are described in detail below.

[0033] PipelineState can contain member parameters stages, stage_id, and parity, where stages can represent the number of data processing stages expected to be used to control the pipeline in the current instance. In actual applications, stages can be assigned corresponding values ​​according to the number of data processing stages. For example, if there are currently 5 data processing stages, the value of stages can be 5. Stage_id can be used to indicate the current data processing stage of the pipeline. Generally speaking, the value range of stage_id can be [0, stages-1]. For example, if the pipeline contains two data processing stages, then stage_id can take the value of 0 or 1, 0 represents the first data processing stage, and 1 represents the second data processing stage. Parity in PipelineState can be used to represent the state checksum, which usually takes the value of 0 or 1. The functions implemented by PipelineState can be summarized as follows: after the current data processing stage ends, stage_id will be incremented to point to the next data processing stage. At the same time, PipelineState also has a stage_id judgment process. If the stage_id after incremental processing is the last data processing stage, the stage_id will be reset to 0, and the parity value in PipelineState will be flipped (from 0 to 1, or from 1 to 0).

[0034] PingPongPipelineBar mainly implements two functions: wait function and arrive function. When the wait function is executed, it can trigger the verification code comparison process. By comparing whether the two verification codes from different sources are inconsistent, it can be determined whether the data processing process can be performed in the current pipeline. When the arrival function is executed, it can send an arrival instruction to the specified pipeline (usually the next adjacent pipeline) to try to rotate the hardware resources from the current pipeline to the next pipeline.

[0035] Based on the two classes implemented above, in this application, two different instances can be configured for each pipeline involved in the work: memory barrier instance (Mbar) and execution state instance (State). Assuming that there are currently two pipelines involved in the data processing flow, then these two pipelines will have their own memory barrier instance and execution state instance. Different pipelines can manage their own instances, so as to execute the data processing flow based on these two instances.

[0036] In this application, the member parameters in the memory barrier instance may include a pending execution identifier (pnd) and a barrier check symbol (prt), and the member parameters in the execution state instance may include a stage identifier (stage) and a state check symbol (parity). Figure 2 and Figure 3 , to illustrate the data processing method in the pipeline in one embodiment of the present application.

[0037] S1: When the to-be-executed identifier indicates that there is currently data to be processed, compare the current check values ​​of the barrier check character and the state check character, and when the current check values ​​of the barrier check character and the state check character are inconsistent, execute the data to be processed.

[0038] See also Figure 3 , Figure 3 A schematic diagram of the data processing process using two pipelines as examples is provided. Figure 3 The 6 timing subgraphs of the data processing process are shown in the figure. The numbers (1 to 6) in the upper left corner of each timing subgraph can represent the timing identifier corresponding to the timing subgraph. In each timing subgraph, it is assumed that the pipelines currently involved in the work are c0 and c1, and both pipelines have two data processing stages stage0 and stage1. Pipelines c0 and c1 have their own memory barrier instances (Mbar) and execution state instances (State). As mentioned above, the memory barrier instance Mbar can include a pending identifier (pnd) and a barrier check symbol (prt), and the member parameters in the execution state instance State can include a stage identifier (stage) and a state check symbol (parity).

[0039] In one embodiment, when each pipeline is initialized, member parameters in the memory barrier instance and the execution state instance can be initialized and assigned values. The barrier check symbol in each memory barrier instance is configured as a first specified value, and only one execution state instance in each execution state instance has a state check symbol configured as a second specified value, and the state check symbols of the remaining execution state instances are configured as the first specified value, wherein the first specified value and the second specified value are different values.

[0040] For example, the first specified value may be 0, and the second specified value may be 1. Figure 3 In the timing subgraph with the timing identifier 1, only the status check of pipeline c0 is configured as 1, and the status check of pipeline c1 is configured as 0. At the same time, the barrier checkers of the two pipelines are both configured as 0. In practical applications, other member parameters can also be initialized. For example, the pending flag in the memory barrier instance can be configured as the amount of data to be processed. Figure 3 The amount of data is represented by 1 (pnd=1). For another example, the stage identifier in the execution state instance can be configured to 0 (stage0), indicating that it starts from the first data processing stage. Of course, the initialization assignments listed above are just examples for the convenience of explanation, and do not mean that the technical solution of the present application can only be assigned in the above manner. In fact, those skilled in the art, after understanding the essence of the technical solution of the present application, can flexibly perform initialization assignments according to actual conditions.

[0041] In this embodiment, the pipeline can first determine whether the pending flag indicates that there is currently data to be processed. Generally speaking, when the value of the pending flag is not 0, it can indicate that there is currently data to be processed; and when the value of the pending flag is equal to 0, it indicates that there is currently no data to be processed. Figure 3 Taking the timing subgraph with the timing identifier 1 as an example, the pnd in pipelines c0 and c1 are both 1, indicating that there is currently data to be processed.

[0042] In this embodiment, the member parameters in the memory barrier instance and the execution state instance of each pipeline can be initialized and configured. Among them, only the state check symbol of one execution state instance will be configured as the second specified value, and the state check symbols of the other execution state instances will be configured as the first specified value that is the same as the barrier check symbol. In this way, in the same time period, only one pipeline will meet the condition that the check values ​​of the barrier check symbol and the state check symbol are inconsistent, and the pipeline that meets this condition will enter the data processing flow. In this way, for the same hardware resource, only one pipeline will occupy the hardware resource in the same time period, and after the pipeline executes the data to be processed, it will rotate the hardware resource to the next adjacent pipeline by passing instructions. This processing method can rotate the hardware resources in different pipelines in an orderly manner, and at the same time, it can avoid the situation where different pipelines grab hardware resources from each other in the same time period, thereby improving the stability of data processing.

[0043] When confirming that there is data to be processed, each pipeline can compare the current check values ​​of the barrier checker and the state checker, and execute the data to be processed if the current check values ​​of the barrier checker and the state checker are inconsistent. Figure 3 For example, in the timing subgraph with timing identifier 1, the prt of pipeline c0 is 0 and the parity is 1, which are inconsistent. At this time, pipeline c0 can execute the data to be processed in stage0. However, the prt and parity of pipeline c1 are both 0, which are consistent. Therefore, pipeline c1 does not meet the preconditions for data processing and cannot execute the data to be processed. In other words, in the data processing stage of stage0, only pipeline c0 can execute the data to be processed at the same time; while pipeline c1 can only be in a waiting state.

[0044] It can be seen that in one embodiment of the present application, when the current check values ​​of the barrier check character and the state check character are consistent, it is necessary to maintain a waiting state until the check values ​​of the barrier check character and the state check character are changed to be inconsistent before the data to be processed can be executed.

[0045] In this embodiment, if the check values ​​of the barrier check character and the state check character are consistent, the current pipeline cannot process data and needs to remain in a waiting state. This ensures that only one pipeline occupies hardware resources in the same period, and the other pipelines can be in a waiting state, thereby rotating hardware resources in different pipelines in an orderly manner, and avoiding different pipelines from competing for hardware resources in the same period, thereby improving the stability of data processing.

[0046] S3: After the execution of the data to be processed is completed, a transfer instruction is sent to the next adjacent pipeline, and the stage identifier in the execution status instance is updated to enter the next data processing stage, wherein the transfer instruction is used to guide the next pipeline to update the to-be-executed identifier in its own memory barrier instance.

[0047] In this embodiment, after the pipeline has executed the data to be processed, it can send a transfer instruction to the next adjacent pipeline, so as to rotate the hardware resources to the next pipeline. Then, the pipeline can update the stage identifier in the execution state instance to enter the next data processing stage. Figure 3 For example, in the timing subgraph with timing identifier 1, after pipeline c0 has executed the data to be processed in stage0, it can send a transfer instruction to pipeline c1 and update the stage identifier to stage1, thereby entering the data processing stage of stage1 in the timing subgraph with timing identifier 2. It should be noted that after entering the next data processing stage, the value of the state check symbol of the pipeline will not change. Please refer to Figure 3 In the timing subgraph with timing identifier 2, after pipeline c0 enters stage1, the parity in the execution state instance State is still 1.

[0048] In this embodiment, after receiving the transfer instruction, the next adjacent pipeline will update the pending flag in its own memory barrier instance. Specifically, the value of the pending flag can be reduced by one, indicating that the current pending data has been processed by the previous pipeline. Figure 3 Taking the timing subgraph with timing identifier 2 as an example, after pipeline c1 receives the transfer instruction, it will reduce pnd from 1 to 0.

[0049] In one embodiment, when the pending execution flag indicates that there is no pending data to be processed, the value of the pending execution flag needs to be reset, and the current value of the barrier check symbol is flipped to another different value, wherein the pending execution flag after the reset value indicates that there is currently pending data to be processed. Figure 3In the timing subgraph with the timing identifier 2, after pipeline C1 reduces pnd from 1 to 0, pnd indicates that pipeline C1 currently has no data to be processed. At this time, if the overall operation process has not yet ended, the pnd of pipeline C1 will be reset to 1, and the prt of pipeline C1 will also flip from 0 to 1, and then enter the scene shown in the timing subgraph with the timing identifier 3. In the timing subgraph with the timing identifier 3, the pnd of pipeline C1 is reset to 1, and the prt of pipeline C1 is also reset to 1. In this way, the pnd of pipeline C1 after reset can represent that it currently has data to be processed. It should be noted that pnd only indicates the amount of data that needs to be processed by the pipeline in the current data processing stage. When pnd changes from 1 to 0, it indicates that there is no data that needs to be processed by the pipeline in the current data processing stage. However, in the overall data processing process, new data to be processed is usually continuously loaded into the pipeline. Therefore, when pnd changes from 1 to 0, in order to enable the pipeline to process the newly loaded data normally, pnd needs to be reset to 1, so that the pipeline can continue to enter the data processing process.

[0050] In this embodiment, if the pending execution flag indicates that there is currently no data to be processed, it is necessary to reset the pending execution flag and flip the barrier check symbol. The purpose of this processing is that the reset pending execution flag can indicate that there is currently data to be processed, so that the subsequent check value comparison process between the barrier check symbol and the status check symbol can be performed; and by flipping the barrier check symbol, it can be ensured that only one pipeline will meet the data processing conditions in the same period of time, thereby being able to stably rotate hardware resources.

[0051] In this embodiment, if Figure 3 As shown in the timing sub-diagram with the timing identifier 3, after resetting the pending execution identifier and flipping the barrier check symbol, pipeline c1 can compare the current check values ​​of the barrier check symbol and the state check symbol. At this time, the barrier check symbol prt is 1 and the state check symbol parity is 0, and the two are inconsistent, so pipeline c1 can start the data processing process of stage0. Similarly, after completing the data processing process of stage0, pipeline c1 can send a transfer instruction to the adjacent pipeline c0, and can update the stage identifier in its own execution state instance (from stage0 to stage1). During this process, the state check symbol parity of pipeline c1 remains unchanged and is still 0. For details, please refer to Figure 3 In the timing subgraph with the timing identifier 4, in this timing subgraph, the stage identifier of pipeline c1 is updated from Stage0 to Stage1, and the Parity remains 0.

[0052] from Figure 3It can be seen from the timing sub-graph with the timing identifier 2 that after pipeline c0 enters stage1, since the assignments of prt and parity are still inconsistent, pipeline c0 can still execute the data processing process of stage1. From the timing point of view, the process of pipeline c0 executing stage1 is synchronized with the process of pipeline c1 executing stage0, but in actual applications, these two processes will not occupy the same hardware resources. The reason is that in actual applications, stage0 and stage1 can correspond to different types of instructions. For example, stage0 can correspond to data calculation instructions, and stage1 can correspond to data storage instructions. When these two instructions are actually processed, they are processed separately by different hardware resources, so that stage1 of pipeline c0 and stage0 of pipeline c1 can be carried out at the same time. The final timing processing effect can be shown as follows. Figure 4 As shown. Figure 4 In the example, mma can represent the processing of data calculation instructions, and store can represent the processing of data storage instructions. At the beginning, both pipelines c0 and c1 will perform the checksum comparison process, and the result is that only pipeline c0 can perform the processing of stage0, which corresponds to Figure 4 At the beginning, only pipeline c0 executes mma. When pipeline c0 enters stage1 and starts processing data storage instructions, pipeline c1 can enter the processing process of stage0 (that is, the processing process of mma) at the same time. In this way, the store of pipeline c0 and the mma of pipeline c1 can overlap in timing, and the subsequent processes are similar. Figure 4 It can be seen that for the hardware resources processing MMA, they will rotate back and forth between pipelines c0 and c1, greatly improving the utilization of the hardware resources.

[0053] The technical solution provided by this embodiment can configure each pipeline involved in the work with its own memory barrier instance and execution state instance, and both instances contain their own member parameters. Among them, for any pipeline, the data to be processed will only be executed when the check values ​​of the barrier check symbol and the state check symbol are inconsistent. After executing the data to be processed, the current pipeline will send a transfer instruction to the next adjacent pipeline and enter the next data processing stage. The next pipeline can update the pending execution flag in its own memory barrier instance according to the transfer instruction, and then it can determine whether the pending data is currently available based on the updated pending execution flag. It can be seen that before executing the data to be processed, the pipeline will perform a comparison process of the barrier check symbol and the state check symbol, and only the pipeline that meets the conditions can execute the data to be processed. This processing method can avoid the out-of-order execution of instructions and ensure that the business code can run according to the established logic. At the same time, after executing the data to be processed, the pipeline will pass the data processing process to the next adjacent pipeline to ensure that each pipeline can alternately use hardware resources for data processing. This method can accurately and stably rotate hardware resources between different pipelines, thereby greatly improving the utilization rate of hardware resources.

[0054] In one embodiment, after updating the stage identifier in the execution state instance, it can be determined whether the updated stage identifier represents the return of the next data processing stage to the initial stage. If not, after entering the next data processing stage, the updated stage identifier is retained and the value of the state check symbol is maintained unchanged; if so, after returning to the initial stage, the stage identifier is reset and the current value of the state check symbol is flipped to another different value. Figure 3Taking the timing subgraph with the timing identifier of 4 as an example, after pipeline c0 completes the data processing process of stage1, it will continue to accumulate stage identifiers. In binary, the result of accumulating stage identifiers is to change from stage1 back to stage0. At this time, the updated stage identifier indicates that the next data processing stage has returned to the initial stage (stage0). In this case, pipeline c0 needs to reset the stage identifier to stage0 (in the timing subgraph with the timing identifier of 4, the execution state instance State of pipeline c0 is Stage0), and needs to flip the state check symbol parity from 1 to 0 (in the timing subgraph with the timing identifier of 4, the execution state instance State of pipeline c0 is Parity0). If the updated stage identifier does not indicate that the next data processing stage has returned to the initial stage, then after entering the next data processing stage, the updated stage identifier can be retained and the value of the state check symbol can be maintained unchanged. For example, in the timing subgraph with the timing identifier 2, when pipeline c0 enters stage1 from stage0, the stage identifier can be retained as the updated stage1, and the parity is not flipped and remains 1. Subsequently, the parameter change process presented in the timing subgraphs with the timing identifiers 5 and 6 is similar to the parameter change process in the aforementioned timing subgraphs, and will not be repeated here.

[0055] In this embodiment, when the last data processing stage completes data processing, the process will return to the initial stage. When returning to the initial stage, the stage identifier needs to be reset to ensure that the stage identifier corresponds to the actual data processing stage. At the same time, the state check symbol needs to be flipped to ensure that only one pipeline meets the data processing conditions in the same period, so that the hardware resources can be rotated stably.

[0056] From the above description, it can be found that by flipping the values ​​of the barrier check character and the state check character in different scenarios, it is possible to ensure that the hardware resources of the data calculation instructions are continuously rotated between the two pipelines, thereby realizing a double buffering mechanism.

[0057] In one embodiment, in order to accurately send the transfer instruction, when sending the transfer instruction to the next adjacent pipeline, the pipeline identifier of the current pipeline can be identified and the pipeline identifier can be incrementally updated. Then the total number of pipelines currently participating in the work can be obtained, and the total number can be modulo processed using the pipeline identifier after incremental update to obtain the target identifier of the next adjacent pipeline. In this way, the transfer instruction can be sent to the pipeline with the target identifier. Figure 3For example, the timing subgraph with the timing identifier 1 in the figure, the pipeline identifier of pipeline c0 can be 0, and after incremental update, it can change from 0 to 1. The total number of pipelines currently involved in the work is 2, and 1 can be obtained by taking the modulus of 1 to 2, so that a transfer instruction can be sent to pipeline c1. Similarly, after completing the data processing flow, pipeline c1 can incrementally update 1 to get 2, and then take the modulus of 2 to 2 to get 0, so a transfer instruction can be sent to pipeline c0.

[0058] In this embodiment, the target identifier of the next pipeline can be accurately determined by the remainder algorithm, and the transfer instruction can be accurately sent based on the target identifier, thereby ensuring the accuracy and stability of data processing.

[0059] In one embodiment, sending a transfer instruction to the next adjacent pipeline includes: identifying the data processing stage currently represented by the stage identifier, and sending a transfer instruction to the same data processing stage in the next adjacent pipeline. Figure 3 Taking the timing subgraph with timing identifier 1 as an example, when pipeline c0 sends a transfer instruction to pipeline c1, since it is currently in the data processing stage of stage0, pipeline c0 will still send a transfer instruction for the data processing stage of stage0 of pipeline c1, but will not send a transfer instruction for the data processing stage of stage1 of pipeline c1.

[0060] In this embodiment, since the pipeline usually includes multiple different data processing stages, after the current pipeline completes data processing in the current data processing stage, it should send a transfer instruction to the same data processing stage of the next pipeline. This ensures that transfer instructions can be sent back and forth between the same data processing stages, does not cause disorder in the data processing stages, and improves the accuracy and stability of data processing.

[0061] From the perspective of the implementation logic of the business code, this application only needs to add the execution statement of the waiting function before the original data calculation instruction, and add the execution statement of the transfer function after the data calculation instruction; similarly, the execution statement of the waiting function can be added before the original data storage instruction, and the execution statement of the transfer function can be added after the data storage instruction. In this way, the execution logic of each of the above implementation methods can be implemented from the level of business code. This method has little modification to the original business code, and the execution statements of the waiting function and the transfer function can form the same set of collaborative codes, and the code modification is relatively simple.

[0062] See also Figure 5On the other hand, the present application also provides a data processing device in a pipeline, wherein the pipeline is configured with a memory barrier instance and an execution state instance, wherein the memory barrier instance includes a pending execution identifier and a barrier check symbol, and the execution state instance includes a stage identifier and a state check symbol; the device includes: The comparison execution unit 100 is used to compare the current check values ​​of the barrier check character and the state check character when the to-be-executed identifier indicates that there is currently to-be-processed data, and to execute the to-be-processed data when the current check values ​​of the barrier check character and the state check character are inconsistent; The instruction transfer unit 200 is used to send a transfer instruction to the next adjacent pipeline after the execution of the data to be processed is completed, and update the stage identifier in the execution status instance to enter the next data processing stage, wherein the transfer instruction is used to guide the next pipeline to update the to-be-executed identifier in its own memory barrier instance.

[0063] In one embodiment, when each pipeline is initialized, the barrier check symbols in each of the memory barrier instances are configured as a first specified value, only one of the execution state instances has a state check symbol configured as a second specified value, and the state check symbols of the remaining execution state instances are configured as the first specified value, wherein the first specified value and the second specified value are different values.

[0064] In one embodiment, if the pending execution flag indicates that there is currently no data to be processed, the value of the pending execution flag is reset, and the current value of the barrier check symbol is flipped to another different value, wherein the reset pending execution flag indicates that there is currently data to be processed.

[0065] In one embodiment, the instruction transfer unit is specifically used to identify the pipeline identifier of the current pipeline and incrementally update the pipeline identifier; obtain the total number of pipelines currently participating in the work, and use the incrementally updated pipeline identifier to perform modulo processing on the total number to obtain the target identifier of the next adjacent pipeline; and send a transfer instruction to the pipeline with the target identifier.

[0066] In one embodiment, the instruction transfer unit is specifically used to identify the data processing stage currently represented by the stage identifier, and send a transfer instruction to the same data processing stage in the next pipeline.

[0067] In one embodiment, the instruction transmission unit is also used to determine whether the updated stage identifier represents that the next data processing stage returns to the initial stage. If not, after entering the next data processing stage, the updated stage identifier is retained and the value of the status check symbol is maintained unchanged; if so, after returning to the initial stage, the stage identifier is reset and the current assignment of the status check symbol is flipped to another different value.

[0068] In one embodiment, the comparison execution unit is further used to maintain a waiting state when the current check values ​​of the barrier check character and the state check character are consistent, and execute the data to be processed after the check values ​​of the barrier check character and the state check character are changed to be inconsistent.

[0069] On the other hand, the present application also provides an electronic device, including: a memory storing computer instructions; and at least one processor for executing the computer instructions in the memory to execute the data processing method in the pipeline in the above-mentioned embodiment.

[0070] On the other hand, the present application further provides a computer-readable storage medium on which computer instructions are stored. When the computer instructions are executed by a processor, the processor executes the data processing method in the pipeline in the above-mentioned embodiment.

[0071] On the other hand, the present application further provides a computer program product, including computer instructions, which, when executed by a processor, enable the processor to execute the data processing method in the pipeline in the above-mentioned embodiment.

[0072] See also Figure 6 , Figure 6 is a schematic diagram of the structure of an electronic device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the electronic device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the electronic device, including instructions stored in or on the memory to display graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple electronic devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0073] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0074] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0075] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0076] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0077] The electronic device further comprises a communication interface 30 for the electronic device to communicate with other devices or a communication network.

[0078] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0079] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0080] The present application is described with reference to the flowcharts and / or block diagrams of the methods and systems according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0084] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0085] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0086] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A data processing method in a pipeline, characterized in that: The pipeline is configured with a memory barrier instance and an execution state instance, wherein the memory barrier instance includes a pending execution identifier and a barrier check symbol, and the execution state instance includes a stage identifier and a state check symbol; the method includes: When the to-be-executed identifier indicates that there is currently data to be processed, comparing the current check values ​​of the barrier check character and the state check character, and executing the data to be processed when the current check values ​​of the barrier check character and the state check character are inconsistent; After the data to be processed is executed, a transfer instruction is sent to the next adjacent pipeline, and the stage identifier in the execution status instance is updated to enter the next data processing stage, wherein the transfer instruction is used to guide the next pipeline to update the to-be-executed identifier in its own memory barrier instance.

2. The method according to claim 1, characterized in that When each pipeline is initialized, the barrier check symbols in each of the memory barrier instances are configured as the first specified value, only one of the execution state instances has its state check symbol configured as the second specified value, and the state check symbols of the remaining execution state instances are configured as the first specified value, wherein the first specified value and the second specified value are different values.

3. The method according to claim 1, characterized in that: The method further comprises: If the pending execution flag indicates that there is currently no data to be processed, the value of the pending execution flag is reset, and the current value of the barrier check symbol is flipped to another different value, wherein the pending execution flag after the reset value assignment indicates that there is currently data to be processed.

4. The method according to claim 1, characterized in that Sending a transfer instruction to the next adjacent pipeline includes: Identify the pipeline identifier of the current pipeline, and incrementally update the pipeline identifier; Obtain the total number of currently participating pipelines, and perform modulo processing on the total number using the pipeline identifier updated incrementally to obtain the target identifier of the next adjacent pipeline; Send a transfer instruction to the pipeline having the target identifier.

5. The method according to claim 1 or 4, characterized in that: Sending a transfer instruction to the next adjacent pipeline includes: The data processing stage currently represented by the stage identifier is identified, and a pass-through instruction is sent for the same data processing stage in the next pipeline.

6. The method according to claim 1 or 3, characterized in that: After updating the phase identifier in the execution state instance, the method further includes: Determine whether the updated stage identifier represents that the next data processing stage returns to the initial stage. If not, after entering the next data processing stage, retain the updated stage identifier and maintain the value of the state check symbol unchanged; if so, after returning to the initial stage, reset the stage identifier and flip the current assignment of the state check symbol to another different value.

7. The method according to claim 1 or 3, characterized in that: The method further comprises: When the current check values ​​of the barrier check character and the state check character are consistent, the waiting state is maintained until the check values ​​of the barrier check character and the state check character are changed to be inconsistent, and then the data to be processed is executed.

8. A data processing device in a pipeline, characterized in that: The pipeline is configured with a memory barrier instance and an execution state instance, wherein the memory barrier instance includes a pending execution identifier and a barrier check symbol, and the execution state instance includes a stage identifier and a state check symbol; the device includes: a comparison execution unit, configured to compare the current check values ​​of the barrier check character and the state check character when the to-be-executed identifier indicates that there is currently to-be-processed data, and to execute the to-be-processed data when the current check values ​​of the barrier check character and the state check character are inconsistent; An instruction transfer unit is used to send a transfer instruction to the next adjacent pipeline after the execution of the data to be processed is completed, and to update the stage identifier in the execution status instance to enter the next data processing stage, wherein the transfer instruction is used to guide the next pipeline to update the to-be-executed identifier in its own memory barrier instance.

9. An electronic device, characterized in that: include: a memory storing computer instructions; At least one processor, configured to execute the computer instructions in the memory to perform the method according to any one of claims 1-7.

10. A computer-readable storage medium having computer instructions stored thereon, characterized in that: When the computer instructions are executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 7.

11. A computer program product comprising computer instructions, characterized in that: When the computer instructions are executed by a processor, the processor is caused to perform the method according to any one of claims 1 to 7.

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