Design method and system capable of nesting DSR priorities

Abstract

The invention discloses a DSR priority nestable design method and a DSR priority nestable design system. The method comprises the following steps: on the basis of the original interrupt source number designed by a chip, newly adding a preset first number of interrupt sources; performing priority setting on the preset first number of interrupt sources; and simulating the DSR program by using the preset first number of interrupt sources to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority sequence executes the DSR program according to the set priority. According to the scheme provided by the invention, the real-time problem and the hardware blocking problem in the Freertos system can be more stably solved.

Description

Technical Field

[0001] The present invention relates to the technical field of interrupt processing, and in particular to a design method and system for nested DSR priorities. Background Art

[0002] Interrupt Service Routine (ISR) and Deferred Service Routine (DSR) are two important concepts in interrupt handling, especially in FreeRTOS real-time operating system. ISR and DSR are part of interrupt handling, and they work together to handle interrupts efficiently.

[0003] ISR is an interrupt service routine, which is responsible for responding to interrupt requests quickly. Its main function is to perform fast hardware-related operations as quickly as possible, such as reading data or clearing interrupt flags. Since ISR needs to execute quickly, it usually only contains necessary and fast code and avoids complex processing logic to reduce interrupt latency.

[0004] DSR is a delayed service routine that handles unfinished tasks in ISR. When ISR is executed, if there are tasks that need further processing, these tasks will be postponed to DSR. DSR is usually executed after ISR, allowing the system to continue processing other tasks after ISR handles urgent tasks, thereby improving the overall efficiency and responsiveness of the system.

[0005] The working mechanism of ISR and DSR is as follows: ‌When an interrupt occurs‌: The hardware generates an interrupt signal and calls the ISR. The ISR quickly performs the necessary hardware operations, such as reading data or clearing the interrupt flag. If the task is complex, the ISR will mark the remaining tasks as pending. At the right time, the DSR is called to complete the tasks not completed by the ISR. The DSR can be executed when the system is idle, or wait for a certain condition to be met before executing.

[0006] In Freertos system, timer daemon task is usually used as DSR program. However, in Freertos system, all DSRs must be queued in the queue for execution, that is, regardless of the priority of ISR, DSRs are uniformly executed in the queue order with the same priority. This may cause the DSR execution time of low-priority interrupts to be long, delaying the execution of DSRs of high-priority interrupts, and affecting the real-time performance of the entire system.

[0007] If the DSR of an interrupt is abnormally blocked, the DSRs queued in the queue cannot be executed, and the ISR corresponding to the queued DSR cannot be executed (because the unmask work corresponding to the interrupt is completed in the DSR), which eventually causes the entire application to fail to run. Summary of the invention

[0008] In order to solve the above technical problems, an embodiment of the present invention provides a design method and system for nested DSR priorities.

[0009] The technical solution of the embodiment of the present invention is achieved as follows: An embodiment of the present invention provides a design method for nested DSR priorities, the method comprising: Based on the original number of interrupt sources in the chip design, a first number of interrupt sources are added; Setting priorities for the preset first number of interrupt sources; The preset first number of interrupt sources are used to simulate the DSR program to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority sequence executes the DSR program according to the set priority.

[0010] In one embodiment, when the interrupt controller executes the DSR program according to the set priority, the process of executing each DSR program is independent of each other, and the DSR program with a higher priority is executed first.

[0011] In one embodiment, after an ISR task is completed, a DSR program is triggered to execute the DSR task.

[0012] In one embodiment, one ISR program executes one ISR task, and the priority of any ISR program is higher than the priority of all DSR programs.

[0013] In one embodiment, the interrupt controller first executes the ISR program according to the set priority at any time, and then executes the DSR program according to the set priority after all ISR programs are executed.

[0014] An embodiment of the present invention also provides a DSR priority nestable design system, comprising: a processor and a memory for storing a computer program that can be run on the processor; wherein the processor executes the steps of the above-mentioned method when running the computer program.

[0015] The embodiments of the present invention have the following beneficial effects: (1) High real-time performance: The execution real-time performance of high-priority ISRs is not affected by any delay in processing low-priority interrupts, which is used to ensure the real-time processing of high-priority interrupts.

[0016] (2) The DSR program is triggered directly by an interrupt without the intervention of the scheduler.

[0017] (3) Preemptible delay processing to avoid DSR priority flipping. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of a flow chart of a design method for nested DSR priorities according to an embodiment of the present invention; Figure 2 A schematic diagram of a processing flow in a scenario according to an embodiment of the present invention; Figure 3 A schematic diagram of a processing flow of the prior art in a scenario; Figure 4 1 is a diagram showing the internal structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0019] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0020] The embodiment of the present invention provides a design method for nesting DSR priorities, such as Figure 1 As shown, the method includes: Step 101: adding a preset first number of interrupt sources based on the original number of interrupt sources in the chip design; Step 102: setting priorities for the preset first number of interrupt sources; Step 103: Use the preset first number of interrupt sources to simulate the DSR program to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority sequence executes the DSR program according to the set priority.

[0021] In previous technologies, traditional DSRs are pure software, and all delayed interrupt handlers need to be queued in chronological order. Regardless of the priority of the interrupt itself, the corresponding DSRs have the same priority and are executed in the order they enter the queue.

[0022] The present application utilizes the nestable feature of ISR and uses ISR to simulate DSR, so that DSR also has a priority, and the ISR of a high-priority interrupt can be executed first, and the high-priority DSR can also be executed first.

[0023] This embodiment will reserve N IRQ numbers (i.e., interrupt sources) to simulate DSR when the CPU configures NVIC. The reserved N IRQ numbers do not have hardware interrupt connections and are only used as simulated DSRs in the Freertos system. For example, when designing a chip, if the product itself requires 100 interrupt sources, then this embodiment will add an additional 32 reserved interrupt sources during chip design, which are not connected to peripherals and are idle IRQs. When the Freertos system is running, the ISR programs corresponding to these reserved IRQs will be simulated as DSR programs, so that the DSR programs have a nesting function. (Nesting means that the higher the priority, the higher the execution priority).

[0024] That is, in the prior art, the DSR program corresponding to the ISR program is a pure software queue, which is executed in chronological order. In this embodiment, the ISR simulates the DSR, so that the DSR can have a priority and be executed according to the priority.

[0025] Specifically, the method provided in this embodiment mainly includes the following contents: 1. When designing the chip architecture, reserve N IRQs to simulate the DSR interrupt number; 2. Set the priority of N IRQs, N is the highest priority, 0 is the lowest priority, and high-priority interrupts can nest low-priority interrupts; replace the DSR program with the interrupt ISR program corresponding to N IRQs, so that the DSR program has priority.

[0026] 3. The interrupt controller NVIC of ARM-M CPU supports interrupt nesting function.

[0027] 4. After the normal ISR is executed, the DSR is triggered. DSRs have different priorities, and DSRs of different priorities will not affect each other, and high-priority DSRs can preempt low-priority DSRs.

[0028] That is, in this embodiment, ISR0 can correspond to an independent DSR0, and the execution time and real-time performance of ISR0 and DSR0 of this interrupt are not affected by DSR1 (and other low-priority DSR) programs. DSR can also be divided into priorities, and the DSR0 corresponding to a high-priority ISR0 also has a high priority, and DSR0 can nest a low-priority DSR1. High-priority ISR can ensure real-time performance.

[0029] For ease of understanding, the present embodiment is described below using a specific scenario.

[0030] See also Figure 2 In this embodiment, the scenario where the low priority DSR1 is nested is as follows: 1. At time t1, ISR1 is executing.

[0031] 2. At time T2, ISR1 is executed and DSR1 begins to execute.

[0032] 3. At time T3, DSR1 is not executed yet, and the high priority interrupt ISR0 is executed.

[0033] 4. At time T4, ISR0 is executed and DSR0 begins to execute.

[0034] 5. At T5, DSR0 is executed (ISR0 can be triggered again at this time), and DSR1 is executed again.

[0035] 6. At time T6, DSR1 is executed and returns to thread execution.

[0036] Real-time requirement: T3~T5 is the execution time of 0 priority interrupt. After T5, ISR0 can be triggered again. Figure 2 Middle red arrow.

[0037] The processing flow chart of the same scenario without using the solution of this embodiment is as follows Figure 3 As shown, including: 1. At time t1, ISR1 is executing.

[0038] 2. At time T2, ISR1 is executed and DSR1 begins to execute.

[0039] 3. At time T3, DSR1 is not executed yet, and the high priority interrupt ISR0 is executed.

[0040] 4. At time T4, ISR0 is executed and DSR1 continues to be executed.

[0041] 5. At T5, after DSR1 is executed, DSR0 is executed (because ISR1 is executed first, DSR1 enters the queue first, and ISR0 is executed later, so DSR0 enters the queue later).

[0042] 6. At T6, DSR0 is executed and the thread starts to execute. ISR0 can be triggered at T6, such as Figure 3 Shown by the red line.

[0043] Real-time issue: The re-triggering of ISR0 depends on the execution time of DSR1, that is, the time from T4 to T5, which affects the real-time performance of ISR0.

[0044] In summary, because this embodiment uses ISR to simulate DSR, the real-time execution of the high-priority ISR is not affected by any delay in the processing of low-priority interrupts, so as to ensure the real-time processing of high-priority interrupts, and can more stably solve the real-time problems and hardware blocking problems in the FreeRTOS system.

[0045] In order to implement the method of an embodiment of the present invention, an embodiment of the present invention also provides a DSR priority nested design system, including: a processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, the steps of the above-mentioned method are executed.

[0046] The above-mentioned system provided in this embodiment belongs to the same concept as the above-mentioned method embodiment. The specific implementation process thereof is detailed in the method embodiment and will not be repeated here.

[0047] In order to implement the method of the embodiment of the present invention, the embodiment of the present invention also provides a computer program product, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the steps of the above method.

[0048] Based on the hardware implementation of the above program modules, and in order to implement the method of the embodiment of the present invention, the embodiment of the present invention further provides an electronic device (computer device). Specifically, in one embodiment, the computer device may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A06. The network interface A02 of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor A01, the method of any one of the above embodiments is implemented. The display screen A04 of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device A05 of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0049] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0050] The device provided by the embodiment of the present invention includes a processor, a memory, and a program stored in the memory and executable on the processor. When the processor executes the program, the method of any one of the above embodiments is implemented.

[0051] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0052] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0053] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0054] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0055] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0056] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0057] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0058] It can be understood that the memory of the embodiment of the present invention can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memories described in the embodiments of the present invention are intended to include, but are not limited to, these and any other suitable types of memories.

[0059] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0060] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A design method for nested DSR priorities, characterized in that: The method comprises: Based on the original number of interrupt sources in the chip design, a first number of interrupt sources are added; Setting priorities for the preset first number of interrupt sources; The preset first number of interrupt sources are used to simulate the DSR program to replace the original DSR program to execute the DSR task, so that the interrupt controller supporting the priority sequence executes the DSR program according to the set priority.

2. The design method for nested DSR priorities according to claim 1, characterized in that: When the interrupt controller executes the DSR program according to the set priority, the process of executing each DSR program is independent of each other, and the DSR program with a higher priority is executed first.

3. The design method for nested DSR priorities according to claim 2, characterized in that: After an ISR task is executed, a DSR program is triggered to execute the DSR task.

4. The design method for nested DSR priorities according to claim 3, characterized in that: An ISR program executes an ISR task, and the priority of any ISR program is higher than the priority of all DSR programs.

5. The design method for nested DSR priorities according to claim 4, characterized in that: At any time, the interrupt controller first executes the ISR program according to the set priority. After all ISR programs are executed, the DSR program is executed according to the set priority.

6. A design system in which DSR priorities can be nested, characterized in that: include: A processor and a memory for storing a computer program that can be run on the processor; wherein, when the processor is used to run the computer program, the steps of the method according to any one of claims 1 to 5 are executed.

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