Chip verification method and device, equipment and medium

Abstract

The embodiment of the invention discloses a chip verification method, device, equipment and medium, which are suitable for the field of chip testing, and the method comprises the following steps: verifying a floating point calculation module by adopting a formalized verification method based on the data path description of the floating point calculation module of the chip until a set verification completion condition is reached; verifying the circuit operation logic code of the function level module of the chip based on the test case by adopting a general verification method; wherein the function level module comprises at least two floating point calculation modules. According to the technical scheme provided by the invention, the completeness of chip verification can be improved, and the resource consumption of chip verification is saved.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and in particular to a chip verification method, device, equipment and medium. Background Art

[0002] Chip verification is an important part of ensuring the correctness and reliability of integrated circuit design. Its importance lies in its ability to detect defects and errors in the design in advance, avoiding huge economic losses and time delays caused by discovering problems after chip manufacturing.

[0003] An important part of chip verification is to verify the completeness of the chip through various test cases. However, since the test cases themselves are limited, it is impossible to cover all verification situations. Furthermore, as the chip integration becomes higher and higher, the amount of data required for verification increases, and the current verification method consumes a lot of computing resources and time resources. Summary of the invention

[0004] The technical solution of the embodiment of the present invention provides a chip verification method, device, equipment and medium. Through the solution of the embodiment of the present invention, the chip verification efficiency and completeness can be improved, and the verification resources required for chip verification can be saved.

[0005] In a first aspect, an embodiment of the present invention provides a chip verification method, comprising:

[0006] Using a formal verification method, based on a data path description of the floating-point calculation module of the chip, the floating-point calculation module is verified until a set verification completion condition is met;

[0007] A general verification method is adopted to verify the circuit operation logic code of the functional level module of the chip based on test cases; wherein the functional level module includes at least two floating-point calculation modules.

[0008] In a second aspect, an embodiment of the present invention provides a chip verification device, including:

[0009] A formal verification module, used to verify the floating-point calculation module of the chip based on the data path description of the floating-point calculation module by using a formal verification method until a set verification completion condition is met;

[0010] A general verification module is used to verify the circuit operation logic code of the functional level module of the chip based on the test case by adopting a general verification method; wherein the functional level module includes at least two floating-point calculation modules.

[0011] In a third aspect, an embodiment of the present invention provides an electronic device, the electronic device comprising:

[0012] at least one processor; and

[0013] a memory communicatively connected to the at least one processor; wherein,

[0014] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the chip verification method described in any one of the embodiments of the present invention.

[0015] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip verification method described in any one of the embodiments of the present invention when executed.

[0016] The embodiment of the present invention provides a chip verification method, device, equipment and medium, the method comprising: using a formal verification method, based on the data path description of the floating-point calculation module of the chip, verifying the floating-point calculation module until the set verification completion condition is reached; using a general verification method, based on the test case, verifying the circuit operation logic code of the functional-level module of the chip; wherein the functional-level module includes at least two floating-point calculation modules. Specifically, verifying the chip at different levels can improve the completeness of chip verification, and at the same time, it can avoid the shortcomings of a single verification method, improve the efficiency of verification, and reduce the resources required for verification. wherein, the verification at different levels is to verify the floating-point calculation module of the chip and the functional-level module including the floating-point calculation module. the technical solution of the embodiment of the present invention can improve the efficiency and completeness of chip verification, and save the verification resources required for chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flowchart of a chip verification method provided in Embodiment 1 of the present invention;

[0019] Figure 2 A flowchart of a chip verification method provided in Embodiment 2 of the present invention;

[0020] Figure 3 A schematic diagram of a chip verification method provided by an embodiment of the present invention;

[0021] Figure 4A schematic diagram of a chip verification method provided by an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of the structure of a chip verification device provided in Embodiment 3 of the present invention;

[0023] Figure 6 A schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0026] It should be noted that the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the technical solution of the present disclosure are in compliance with the relevant laws and regulations and do not violate public order and good morals.

[0027] Embodiment 1

[0028] Figure 1 A flowchart of a chip verification method provided in Embodiment 1 of the present invention is specifically applicable to the case of performing computational verification on a chip. The method can be executed by a chip verification device, which can be composed of software and / or hardware and configured in a computer or server.

[0029] like Figure 1 As shown, including:

[0030] Step 110: Using a formal verification method, based on the data path description of the floating-point calculation module of the chip, verify the floating-point calculation module until a set verification completion condition is met.

[0031] Among them, the formal verification of the chip is a method that uses mathematical tools and logic analysis techniques to verify the correctness of the chip design. It mathematically models the chip circuit, and then exhausts the input states that the circuit can reach during the system operation as much as possible, and then detects whether the output state corresponding to the input state is ideal to determine whether there is a logical error in the chip circuit. The floating-point calculation module is used to perform floating-point operations on the chip. Floating-point operations can include basic operations such as addition, subtraction, multiplication, division, square root, exponentiation and logarithm. The floating-point calculation module is also used to verify the accuracy and rounding method of floating-point data. Further, since the implementation of a single function may require multiple continuous operations, the data path describes the path of continuous floating-point operations, and the path may include the calculation process path of the data and the input and output flow path of the operation result. Setting the verification completion condition may include at least one of the verification time condition, the verification convergence condition and the verification number condition. The verification completion condition is used to determine whether the verification is completed. If completed, the formal verification of the chip is stopped. Setting the verification completion condition indicates that the set goal of the formal verification is achieved without achieving the result of full convergence of the verification.

[0032] Specifically, to formally verify the chip, it is necessary to determine whether the data paths, calculation results and calculation states of the floating-point calculation module are accurate. Furthermore, in the process of formal verification, it is necessary to quickly traverse all test spaces to cover all possible boundary conditions and abnormal situations as much as possible. When the complexity of the data space and the chip involved is large, the formal verification method cannot find an understandable solution or a method of proving the data in a short time, resulting in failure to converge. It is then difficult to evaluate the completeness of the verification, that is, whether all possible test scenarios have been verified. This may cause potential design defects to be missed. Therefore, it is necessary to perform secondary verification on the high-level of the floating-point calculation module, that is, the functional-level module implemented by the floating-point calculation module set, through the method of the embodiment of the present invention, to improve the completeness of the verification and reduce the resources of the verification, so as to achieve the state where the formal verification has not converged, and the verification result can be quickly determined and the verification process can be completed.

[0033] Step 120: adopt a general verification method to verify the circuit operation logic code of the functional level module of the chip based on the test case; wherein the functional level module includes at least two floating-point calculation modules.

[0034] Among them, the general verification method is to cover the verification space through random input, and the random input can verify many verification situations that cannot be directly touched by manpower. The test case is a test case for general verification of the functional level module, which is used to characterize different usage scenarios and boundary conditions, including the preset input of verification, ideal output and test process, etc. The general verification method needs to verify the circuit operation logic code of the functional level module according to the test case. Therefore, if the number of test cases directly affects the coverage of the verification, however, the test case often cannot traverse all the verification scenarios, and writing a large number of test cases will be inefficient. A lot of resources. Further, even if there are test cases for all scenarios, the use of a large number of test cases will consume a lot of verification time. Therefore, it is necessary to use the method of the embodiment of the present invention to save resource consumption as much as possible while ensuring that the verification effect is achieved. The chip can be divided into multiple levels from the size of the structure. The functional level module refers to a module that realizes a specific function, specifically a set function that can be tested with a test case, and the module will include at least two floating-point calculation modules. The circuit operation logic code is the code that characterizes the circuit of the chip. The circuit operation logic code can simulate the composition, operation mode, connection relationship and each circuit node of the circuit.

[0035] Specifically, the floating-point calculation module may be verified at a high-level functional module to ensure that the entire floating-point calculation module meets the correctness and reliability of the functional module or subsystem.

[0036] Specifically, through formal verification of the chip, we can quickly find the errors in the chip and verify whether it has converged, and then verify the higher-level functional modules, verify the random numbers and eigenvalues, and quickly realize the verification and delivery of the floating-point calculation module.

[0037] Optionally, the floating-point calculation module includes at least one of the following: a dot product calculation module, an accumulation module, and a multiplication and division module; the functional level module includes: a neural network engine.

[0038] Among them, the dot product calculation module, the accumulation module and the multiplication and division module are used to perform dot product calculation, accumulation calculation and multiplication and division calculation respectively. The neural network engine is used to perform convolution, pooling and use the activation function module of the neural network.

[0039] An embodiment of the present invention provides a chip verification method, the method comprising: using a formal verification method, based on the data path description of the floating-point calculation module of the chip, verifying the floating-point calculation module until the set verification completion condition is reached; using a general verification method, based on the test case, verifying the circuit operation logic code of the functional-level module of the chip; wherein the functional-level module includes at least two floating-point calculation modules. Specifically, verifying the chip at different levels can improve the completeness of chip verification, and at the same time, can avoid the shortcomings of a single verification method. Furthermore, through verification at different levels, the efficiency of verification can be improved and the resources required for verification can be reduced. Among them, the verification at different levels is to verify the floating-point calculation module of the chip and the functional-level module including the floating-point calculation module. The technical solution of the embodiment of the present invention can improve the efficiency and completeness of chip verification and save the verification resources required for chip verification.

[0040] Embodiment 2

[0041] Figure 2 This is a flow chart of a chip verification method provided in the second embodiment of the present invention. The method is based on the above embodiment and further defines the specific methods of chip formal verification and general verification.

[0042] like Figure 2 As shown, including:

[0043] Step 210: Under the condition of no over-constraint, a formal verification method is used to verify the floating-point calculation module based on the data path description of the floating-point calculation module of the chip, until it is determined that the error condition of the floating-point calculation module meets the first set error condition, and the verification time reaches the second set time condition without convergence, then the no-over-constraint verification link is stopped; wherein the over-constraint condition includes: setting a complete data space of the input data range boundary.

[0044] Among them, no over-constraint can be understood as performing data verification on the floating-point calculation module without constraints. Exemplarily, the formal verification tools in this field can be used to preliminarily check whether there are obvious logical errors or functional defects in the circuit of the chip under the condition of no over-constraint. The error situation characterizes the result of formal verification, and the error situation can include whether there is a bug and whether the verification result converges. Among them, non-convergence means that the formal verification has not found all possible data paths, but since there is no bug in the design itself, no error will be reported.

[0045] The first set error condition may be that the error condition is bug-free and non-convergence. Specifically, the goal of formal verification without over-constraint is to ensure that the chip design is logically correct, but further verification may be required to ensure that all possible data scenarios are covered. Furthermore, in the case of non-convergence, if the verification time reaches the second set time condition, the verification can be stopped. Among them, since the verification itself consumes a lot of time resources, if the verification time reaches the second set time condition and there is no bug, it can be preliminarily considered that the chip design is logically accurate. However, due to the lack of convergence, it is necessary to verify it through the subsequent method of the embodiment of the present invention. By setting the second set time condition, it can be ensured that the preliminary verification stage of the chip does not consume too much time resources.

[0046] Optionally, after stopping the no over-constraint verification phase, the following steps are also included:

[0047] A formal verification method is adopted to verify the data path description of the floating-point calculation module of the chip using input data with over-constraint conditions, until the convergence condition is reached, it is determined that the set verification completion condition is met, and the formal verification is stopped.

[0048] The convergence condition may be a result of formal verification that represents the convergence of verification, and the verification completion condition is used to determine whether the chip design is correct based on the verification result. If correct, the verification completion condition is met and the formal verification is stopped.

[0049] Specifically, after proving that the chip design is logically accurate without over-constraints, more constraints can be imposed on the data path description of the floating-point calculation module of the chip, such as taking special values ​​for the exponent and base of the floating-point number. In this way, it can be ensured that the chip design can work correctly under all possible input conditions.

[0050] Furthermore, if the result of the formal verification indicates that all the proof paths or data paths have been determined, and the result of the formal verification indicates the accuracy of the circuit design of the chip, the formal verification is stopped.

[0051] Optionally, the constraint condition includes at least one of the following: a value range of an exponent or base of a floating point number.

[0052] Step 220: Generate a test case that uses random data or set range data as input data.

[0053] Specifically, before general verification, multiple test cases need to be written to cover different scenarios and boundary conditions. Different test cases can be generated using random data or pre-set range data.

[0054] Step 230: adopt a general verification method to verify the circuit operation logic coding of the functional level module of the chip based on the test case.

[0055] Specifically, the circuit operation logic coding of the functional-level modules of the chip can be verified based on the test cases, and code coverage analysis tools, for example, can be used to monitor the code coverage during the test process to ensure that an ideal verification result is achieved, where an ideal verification result can be that the circuit operation logic coding is completely covered and there are no operation bugs.

[0056] Optionally, after verifying the circuit operation logic code of the functional level module of the chip based on the test case, the method further includes:

[0057] Detecting code coverage for verifying the circuit running logic code;

[0058] According to the code coverage, the adopted test cases are adjusted and the verification of the general verification method is continued.

[0059] Specifically, code coverage refers to the proportion of circuit operation logic code actually executed by the test case to the total circuit operation logic code during the verification process. If the code coverage is less than a preset threshold, such as 100%, the test case used is adjusted, and the verification of the general verification method is continued based on the adjusted test case.

[0060] For example, Figure 3 A schematic diagram of a verification method for a chip provided by an embodiment of the present invention. Specifically, for the verification of the floating-point calculation module of the chip, it is necessary to first build a corresponding verification environment through a formal verification tool, and determine whether there is a bug in the circuit design of the chip without overconstraint. Further, if the result of the formal verification shows that the current circuit design is bug-free but not converged without overconstraint, it is proved that the circuit design is correct in its preliminary logic. Further, it is necessary to update the overconstraint to overconstraint, and perform corresponding formal verification. And the verification result is characterized as convergence. Further, in the case of convergence, the circuit operation logic code of the function-level module is verified by UVM (Universal Verification Methodology, unified verification method), and the verification is based on random data or set range data as a test case for input data. If the verification result of UVM verification is characterized by no bug and the circuit operation logic code is completely covered, the verification task is completed this time. It should be noted that before UVM verification, it is necessary to build a simulation environment of the UVM framework, and the specific construction method is not limited here.

[0061] For example, Figure 4A schematic diagram of a verification method for a chip provided in an embodiment of the present invention, the flow chart provides a specific example for the implementation of the technical solution of the present invention. Among them, the DPU (Dot Product Unit, dot product calculation unit) unit corresponds to the floating-point calculation module in the embodiment of the present invention; UVM verification corresponds to general verification; AIE (AI Engine, neural network engine) is a neural network engine component, corresponding to a functional level module. Specifically, the DPU includes a huge amount of data space to be tested, and the DPU implements 64 groups of a*b addition (where a and b are both FP8 floating point numbers). If the number of all addition combinations of the DPU is traversed, there will be 2^1024 possibilities, and the convergence cannot be verified by using "formal verification without over-constraint". Therefore, for this situation, after the DPU is bug-free but not convergent, the DPU can be split into addition design and multiplication design, respectively, and formal verification is performed under over-constraint. Multiplication verification only needs to complete a set of a*b numbers, and the remaining numbers will be constrained to fixed values, and the convergence verification of multiplication can be completed. The addition verification randomly selects 2 groups of a*b according to a certain regular method, and the remaining numbers are constrained to fixed values, so that the convergence verification of the addition can be completed. Further, the random numbers and special values ​​of all numbers are verified in the AIE component environment, and finally the delivery of the relatively complete verification of the DPU can be completed. The present invention can better ensure the verification quality and completeness of the floating-point calculation module by adopting a verification method combining formal verification with UVM verification, while saving verification resources.

[0062] An embodiment of the present invention provides a chip verification method. The technical solution of the present invention can avoid the shortcomings of a single verification method, improve the verification efficiency, and reduce the resources required for chip verification by combining a formal verification method with a general verification method.

[0063] Embodiment 3

[0064] Figure 5 This is a schematic diagram of the structure of a chip verification device provided by Embodiment 3 of the present invention. Figure 5 As shown, the device comprises:

[0065] The formal verification module 310 is used to verify the floating-point calculation module of the chip based on the data path description of the floating-point calculation module using a formal verification method until a set verification completion condition is met.

[0066] The general verification module 320 is used to verify the circuit operation logic code of the functional level module of the chip based on the test case by adopting a general verification method; wherein the functional level module includes at least two floating-point calculation modules.

[0067] The embodiment of the present invention provides a chip verification device, which verifies the floating-point calculation module of the chip based on the data path description of the floating-point calculation module of the chip by adopting a formal verification method until the set verification completion condition is reached; the circuit operation logic code of the functional-level module of the chip is verified based on the test case by adopting a general verification method; wherein the functional-level module includes at least two floating-point calculation modules. Specifically, verifying the chip at different levels can improve the completeness of chip verification, and at the same time, can avoid the shortcomings of a single verification method. Furthermore, through verification at different levels, the efficiency of verification can be improved and the resources required for verification can be reduced. Among them, the verification at different levels is to verify the floating-point calculation module of the chip and the functional-level module including the floating-point calculation module. The technical solution of the embodiment of the present invention can improve the efficiency and completeness of chip verification and save the verification resources required for chip verification.

[0068] Optionally, the formal verification module 310 includes:

[0069] The unconstrained unit is used to verify the floating-point calculation module of the chip using a formal verification method based on the data path description of the floating-point calculation module of the chip under the condition of no over-constraint, until it is determined that the error of the floating-point calculation module meets the first set error condition, and the verification time reaches the second set time condition when there is no convergence, then the no over-constraint verification link is stopped. Wherein, the over-constraint condition includes: setting the complete data space of the input data range boundary.

[0070] The formal verification module 310 also includes:

[0071] The over-constraint unit is used to use a formal verification method to verify the data path description of the floating-point calculation module of the chip using input data with over-constraint conditions until a convergence condition is reached, determine that a set verification completion condition is reached, and stop formal verification. Optionally, the over-constraint condition includes at least one of the following: a value range of the exponent or base of a floating-point number.

[0072] Optionally, the general verification module 320 includes:

[0073] A test case generation unit, used for generating test cases using random data or set range data as input data;

[0074] The verification unit is used to verify the circuit operation logic coding of the functional level module of the chip based on the test case by adopting a general verification method.

[0075] The general verification module 320 also includes:

[0076] A detection unit, used to detect code coverage for verifying the circuit operation logic code;

[0077] The cruise unit is used to adjust the adopted test cases according to the code coverage and continue the verification of the general verification method.

[0078] Optionally, the floating-point calculation module includes at least one of the following: a dot product calculation module, an accumulation module, and a multiplication and division module; the functional level module includes: a neural network engine.

[0079] Optionally, the chip is an artificial intelligence chip, and the functional-level module is a functional module required for running a machine learning model.

[0080] The chip verification device provided in the embodiment of the present invention can execute the chip verification method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0081] Embodiment 4

[0082] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0083] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0084] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0085] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a chip verification method.

[0086] In some embodiments, the chip verification method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the chip verification method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the chip verification method in any other appropriate manner (e.g., by means of firmware).

[0087] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0088] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0089] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0090] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0091] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0092] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0093] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0094] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip verification method, characterized in that: include: Using a formal verification method, based on a data path description of the floating-point calculation module of the chip, the floating-point calculation module is verified until a set verification completion condition is met; A general verification method is adopted to verify the circuit operation logic code of the functional level module of the chip based on test cases; wherein the functional level module includes at least two floating-point calculation modules.

2. The method according to claim 1, characterized in that Using a formal verification method, based on the data path description of the floating-point calculation module of the chip, verifying the floating-point calculation module includes: Under the condition of no over-constraint, a formal verification method is used to verify the floating-point calculation module based on the data path description of the floating-point calculation module of the chip, until it is determined that the error condition of the floating-point calculation module meets the first set error condition, and the verification time reaches the second set time condition when there is no convergence, then the no over-constraint verification link is stopped; The over-constraint condition includes: setting a complete data space of the input data range boundary.

3. The method according to claim 2, characterized in that After stopping the no over-constraint verification phase, it also includes: A formal verification method is adopted to verify the data path description of the floating-point calculation module of the chip using input data with over-constraint conditions, until the convergence condition is reached, it is determined that the set verification completion condition is met, and the formal verification is stopped.

4. The method according to claim 3, characterized in that The over-constraint condition includes at least one of the following: a value range of an exponent or base of a floating point number.

5. The method according to any one of claims 1 to 4, characterized in that: Using a general verification method, the circuit operation logic coding of the functional level module of the chip is verified based on the test case, including: Generate test cases that use random data or set range data as input data; A general verification method is adopted to verify the circuit operation logic coding of the functional level module of the chip based on test cases.

6. The method according to claim 5, characterized in that After verifying the circuit operation logic code of the functional level module of the chip based on the test case, it also includes: Detecting code coverage for verifying the circuit running logic code; According to the code coverage, the adopted test cases are adjusted and the verification of the general verification method is continued.

7. The method according to any one of claims 1 to 4, characterized in that: The floating-point calculation module includes at least one of the following: a dot product calculation module, an accumulation module and a multiplication and division module; the functional level module includes: a neural network engine.

8. The method according to claim 7, characterized in that The chip is an artificial intelligence chip, and the functional-level module is a functional module required for the operation of a machine learning model.

9. A chip verification device, characterized in that: include: A formal verification module, used to verify the floating-point calculation module of the chip based on the data path description of the floating-point calculation module by using a formal verification method until a set verification completion condition is met; A general verification module is used to verify the circuit operation logic code of the functional level module of the chip based on the test case by adopting a general verification method; wherein the functional level module includes at least two floating-point calculation modules.

10. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the chip verification method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip verification method according to any one of claims 1 to 8 when executed.

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