A control and management system, method, electronic device and storage medium

Abstract

The present disclosure provides a control management system, method, electronic device and storage medium, which relate to the field of computer technology. The system is applied to an ARM server and includes: an out-of-band JTAG link management module for monitoring multiple JTAG signals output by the system-on-chip of the ARM processor, identifying the fault information of the system-on-chip of the ARM processor, and sending the fault information to the BMC; and further for generating a JTAG link routing control signal; the system-on-chip of the ARM processor for sending multiple JTAG signals to the out-of-band JTAG link management module; and further for receiving and responding to the JTAG link routing control signal to switch the topology mode of the JTAG link; the BMC for receiving and recording the fault information and sending the fault information to the remote operation and maintenance terminal. This technical solution solves the core problems of low efficiency of manual point-by-point detection, strong physical operation dependence and ineffective CPU downtime monitoring in the traditional solution, realizes significant reduction of operation and maintenance delay and cost, and provides high-reliability and low-latency operation and maintenance support for the large-scale deployment of ARM servers.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a control management system, method, electronic device, and storage medium. Background Art

[0002] The rapid development of the digital computing power industry has promoted the expansion of the scale of data centers, and the requirements for server reliability and operation and maintenance efficiency have been continuously improved. Compared with servers on traditional X86 platforms, servers on the ARM platform have become the core choice for high-energy efficiency scenarios due to advantages such as multiple cores, small volume, and low power consumption. However, the large-scale deployment of ARM servers also faces challenges such as low fault location efficiency and complex operation and maintenance. Especially when starting abnormally (such as firmware crashes) or running downtime, the traditional JTAG link management relies on manual point-by-point detection, resulting in operation and maintenance delays, seriously restricting business continuity, and becoming a key bottleneck for the large-scale commercial use of ARM servers.

[0003] Current conventional ARM servers adopt a point-to-point direct-connected JTAG (Joint Test Action Group) topology, where the JTAG module is directly connected to physical pins, having significant defects, including: 1. The fixed unidirectional path cannot dynamically switch routes or collect signals in parallel, and fault troubleshooting requires grabbing data module by module, with low efficiency; 2. It relies on physical operations and has no remote debugging function, and abnormal information cannot be transmitted in real time, requiring on-site intervention, with high costs; 3. The control logic depends on in-band processing by the CPU, and the monitoring function fails when the CPU crashes, with high risks; 4. Fault codes are fragmented and stored in different JTAG channels, making it difficult to integrate and analyze. Summary of the Invention

[0004] The present disclosure provides a control management system, method, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0005] According to a first aspect of the present disclosure, a control management system is provided. The system is applied to an ARM server, and the system includes: an out-of-band JTAG link management module, an ARM processor system-on-chip, and a baseboard management controller BMC; the out-of-band JTAG link management module is communicatively connected to the ARM processor system-on-chip and the BMC respectively;

[0006] The out-of-band JTAG link management module is configured to, after the ARM server is powered on, monitor multiple JTAG signals output by the ARM processor system-on-chip, identify fault information during the startup and operation of the ARM processor system-on-chip, and send the fault information to the BMC; and is further configured to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip;

[0007] The ARM processor system-on-chip is used to send multiple JTAG signals to the out-of-band JTAG link management module after the ARM server is powered on. The multiple JTAG signals carry the startup information and running information of the ARM processor system-on-chip. It is also used to receive and respond to the JTAG link routing control signal to switch the topological mode of the JTAG link.

[0008] The BMC is used to receive and record the fault information and send the fault information to the remote operation and maintenance terminal.

[0009] In an implementable embodiment, the out-of-band JTAG link management module is implemented by a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA), and includes a JTAG control module and a JTAG slave device module.

[0010] The JTAG control module is used to monitor multiple JTAG ports on the ARM processor system-on-chip to obtain corresponding multiple JTAG signals, parallelly analyze the multiple JTAG signals through the CPLD or FPGA to obtain the fault information, and send the fault information to the JTAG slave device module.

[0011] The JTAG slave device module is used to receive the fault information and send it to the BMC through a multiplexer.

[0012] In an implementable embodiment, the JTAG control module includes a monitoring unit and a fault judgment unit:

[0013] The monitoring unit is used to monitor multiple JTAG ports on the ARM processor system-on-chip to obtain multiple JTAG signals.

[0014] The fault judgment unit is used to detect whether the power-on completion indication signal of the ARM processor system-on-chip is normally sent when a JTAG signal fault is recognized.

[0015] If the power-on completion indication signal is not normally sent, the first fault information is determined.

[0016] If the power-on completion indication signal is normally sent, a detection process is started for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

[0017] In an implementable embodiment, when the fault judgment unit starts a detection process for the CPU management core to obtain a detection result, it is specifically used for:

[0018] If the startup completion signal of the CPU management core is not detected within a preset time, the second fault information is determined.

[0019] If the startup completion signal of the CPU management core is detected within a preset time, it is determined that the ARM server is running normally.

[0020] In an implementable embodiment, the ARM processor system-on-chip includes a main CPU processor and a slave CPU processor;

[0021] A first general-purpose input / output GPIO and multiple JTAG ports are respectively provided on the main CPU processor and the slave CPU processor;

[0022] The first GPIO is used to receive the JTAG link routing control signal;

[0023] The multiple JTAG ports at least include: a debug access port, a peripheral management port, a power management port, and a system-on-chip port.

[0024] In an implementable embodiment, an in-position signal output port is provided on the slave CPU processor, which is used to send an in-position output signal to the main CPU processor, the BMC, and the CPLD or FPGA to detect whether the slave CPU processor is in position;

[0025] If the slave CPU processor is in position, the JTAG control module reads the JTAG signal of the slave CPU processor and sends a JTAG link routing control signal;

[0026] If the slave CPU processor is not in position, the JTAG control module stops reading the JTAG signal of the slave CPU processor and stops sending the JTAG link routing control signal to the slave CPU processor.

[0027] In an implementable embodiment, the BMC includes a JTAG master device module, which is used to receive the fault information of the JTAG master device module and record the fault information in a time record table through the BMC;

[0028] The BMC is also used to generate an alarm message according to the fault information and feedback it to the remote operation and maintenance end.

[0029] In an implementable embodiment, the JTAG master device module is further used to send a firmware upgrade instruction or an information acquisition instruction to the CPLD or FPGA through the multiplexer.

[0030] In an implementable embodiment, the system further includes a local interface module, which is used for an external debugging terminal to connect to the out-of-band JTAG link management module through the local interface module to obtain the fault information; and is also used for the external debugging terminal to send a JTAG link routing control signal to the out-of-band JTAG link management module through the local interface module; the external debugging terminal is hardware or software connected to the ARM server.

[0031] According to a second aspect of the present disclosure, a control and management method is provided, which is applied to an out-of-band JTAG link management module in an ARM server. The out-of-band JTAG link management module is respectively communicatively connected to a system-on-chip of an ARM processor and a baseboard management controller (BMC). The method includes:

[0032] After the ARM server is powered on, monitor a plurality of JTAG signals output by the system-on-chip of the ARM processor, where the plurality of JTAG signals carry startup information and running information of the system-on-chip of the ARM processor;

[0033] According to the plurality of JTAG signals, identify fault information during startup and operation of the system-on-chip of the ARM processor;

[0034] Send the fault information to the BMC so that the BMC records the fault information and sends it to a remote operation and maintenance terminal.

[0035] In an implementable embodiment, the out-of-band JTAG link management module is implemented by a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA).

[0036] In an implementable embodiment, the system-on-chip of the ARM processor includes a main CPU processor and a slave CPU processor. The main CPU processor and the slave CPU processor are respectively provided with a first general-purpose input / output (GPIO) and a plurality of JTAG ports. The method further includes:

[0037] Generate a JTAG link routing control signal and send it to the first GPIO of the system-on-chip of the ARM processor to switch the topology mode of the JTAG link;

[0038] The plurality of JTAG ports at least include: a debug access port, a peripheral management port, a power management port, and a system-on-chip port.

[0039] In an implementable embodiment, the monitoring of the plurality of JTAG signals output by the system-on-chip of the ARM processor includes:

[0040] Monitor the plurality of JTAG ports of the system-on-chip of the ARM processor to obtain corresponding plurality of JTAG signals;

[0041] Identifying the fault information of the ARM processor system-on-chip during startup and operation according to the JTAG signal, including:

[0042] Parsing the multiple JTAG signals in parallel through the CPLD or FPGA to obtain the fault information;

[0043] Sending the fault information to the BMC, including:

[0044] Using a multiplexer to send the fault information to the BMC.

[0045] In an implementable manner, the parsing the multiple JTAG signals in parallel through the CPLD or FPGA to obtain the fault information includes:

[0046] When a JTAG signal fault is identified, detecting whether the power-on completion indication signal of the ARM processor system-on-chip is normally sent;

[0047] If the power-on completion indication signal is not normally sent, determining the first fault information;

[0048] If the power-on completion indication signal is normally sent, starting a detection process for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

[0049] In an implementable manner, the starting a detection process for the CPU management core in the ARM processor system-on-chip includes:

[0050] If the startup completion signal of the CPU management core is not detected within a preset time, determining the second fault information;

[0051] If the startup completion signal of the CPU management core is detected within a preset time, determining that the ARM server is running normally.

[0052] In an implementable manner, the method further includes:

[0053] Receiving an on-site output signal sent from the on-site signal output port of the CPU processor to detect whether the slave CPU processor is on-site;

[0054] If the slave CPU processor is on-site, reading the JTAG signal of the slave CPU processor and sending a corresponding JTAG link routing control signal;

[0055] If the slave CPU processor is not on-site, stopping reading the JTAG signal of the slave CPU processor and stopping sending the JTAG link routing control signal to the slave CPU processor.

[0056] In one implementable manner, the method further includes:

[0057] Receiving, by a multiplexer, a firmware upgrade instruction or an information acquisition instruction from the BMC;

[0058] Executing the firmware upgrade instruction to update the logic code of the CPLD or FPGA, or responding to the information acquisition instruction to feedback status information.

[0059] In one implementable manner, the method further includes:

[0060] Connecting to an external debugging terminal through a local interface module to obtain the fault information or receive a JTAG link routing control signal sent by the external debugging terminal;

[0061] The external debugging terminal is hardware or software connected to the ARM server.

[0062] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0063] At least one processor; and

[0064] A memory communicatively connected to the at least one processor; wherein,

[0065] The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method of the present disclosure.

[0066] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the method of the present disclosure.

[0067] The control management system, method, electronic device and storage medium of the present disclosure are applied to an ARM server and include: an out-of-band JTAG link management module, which is used to monitor multiple JTAG signals output by the system-on-chip of the ARM processor after the ARM server is powered on, identify fault information during the startup and operation of the system-on-chip of the ARM processor, and send the fault information to the BMC; it is also used to generate JTAG link routing control signals and send them to the system-on-chip of the ARM processor; the system-on-chip of the ARM processor is used to send multiple JTAG signals to the out-of-band JTAG link management module after the ARM server is powered on, and the multiple JTAG signals carry the startup information and operation information of the system-on-chip of the ARM processor; it is also used to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link; the BMC is used to receive and record the fault information and send the fault information to the remote operation and maintenance end. In this way, the out-of-band JTAG link management module runs independently of the system-on-chip of the ARM processor, parses multiple JTAG signals in real time and in parallel to obtain fault information, generates JTAG link routing control signals to realize the switching of the JTAG link mode, and transmits the fault information to the BMC at the same time to realize structured storage and remote alarm. Through the technical solution of the present disclosure, the core problems of low efficiency of manual point-by-point detection, strong physical operation dependence and ineffective CPU downtime monitoring in the traditional solution are solved, and the operation and maintenance delay and cost are significantly reduced, providing high-reliability and low-latency operation and maintenance support for the large-scale deployment of ARM servers.

[0068] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become easily understood. In the drawings, several embodiments of the present disclosure are shown in an exemplary rather than restrictive manner, where:

[0070] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0071] Figure 1 shows the structural schematic diagram of the control management system according to the embodiment of the present disclosure Figure 1 ;

[0072] Figure 2 shows the structural schematic diagram of the out-of-band JTAG link management module according to the embodiment of the present disclosure;

[0073] Figure 3 shows the structural schematic diagram of the control management system according to the embodiment of the present disclosure Figure 2 ;

[0074] Figure 4 Shows a schematic diagram of the implementation process of the control management method according to an embodiment of the present disclosure;

[0075] Figure 5 Shows a schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0076] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts fall within the protection scope of the present disclosure.

[0077] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0079] The present disclosure provides a control management system, which is applied to an ARM server, as Figure 1 shown. The system includes: an out-of-band JTAG link management module 10, an ARM processor system-on-chip 20, and a baseboard management controller BMC 30; the out-of-band JTAG link management module 10 is communicatively connected to the ARM processor system-on-chip 20 and the BMC 30 respectively;

[0080] The out-of-band JTAG link management module 10 is configured to monitor a plurality of JTAG signals output by the ARM processor system-on-chip 20 after the ARM server is powered on, identify fault information during the startup and operation of the ARM processor system-on-chip 20, and send the fault information to the BMC 30; and is further configured to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip 20.

[0081] In this example, the out-of-band JTAG link management module 10 is connected to the ARM processor system-on-chip 20 and the BMC 30 through a physical communication link. Its core functions include: after the ARM server is powered on, continuously monitoring multiple JTAG signals output by the ARM processor system-on-chip 20, where the JTAG signals cover the status information generated by the ARM processor system-on-chip 20 during the startup phase (such as firmware verification, register initialization) and the running phase (such as peripheral communication, power management); subsequently, by parsing the JTAG signals, identifying the fault types of the ARM processor system-on-chip 20, such as abnormal situations like startup timeout, running crash, etc., and transmitting the fault information to the BMC 30. At the same time, the out-of-band JTAG link management module 10 can also dynamically adjust the topological connection mode of the JTAG link by actively generating JTAG link routing control signals and sending them to the ARM processor system-on-chip 20.

[0082] The ARM processor system-on-chip 20 is used to send multiple JTAG signals to the out-of-band JTAG link management module 10 after the ARM server is powered on, where the multiple JTAG signals carry the startup information and running information of the ARM processor system-on-chip 20; it is also used to receive and respond to the JTAG link routing control signal to switch the topological mode of the JTAG link.

[0083] In this example, after the ARM server is powered on, the ARM processor system-on-chip (ARMSoC) 20 outputs multiple JTAG signals corresponding to multiple internally set JTAG ports. These signals carry the startup information and running information of the ARM processor system-on-chip 20, such as the register status of the debug access port, the initialization result of the peripheral interface, the voltage / temperature parameters of the power supply, and the global status of the system-on-chip, etc. At the same time, the ARM processor system-on-chip 20 is also used to receive the JTAG link routing control signal from the out-of-band JTAG link management module 10 and adjust the physical connection path of the internal JTAG link in response to this signal to achieve flexible adaptation to different debugging or monitoring scenarios.

[0084] The BMC 30 is used to receive and record the fault information and send the fault information to the remote operation and maintenance terminal.

[0085] In this example, the BMC (Baseboard Management Controller) 30 receives and stores the fault information from the out-of-band JTAG link management module 10, records it in chronological order, including information such as the fault type identifier, the occurrence timestamp, and the associated processor node. In addition, the BMC 30 is also used to push the fault information to a remote operation and maintenance terminal, supporting the operation and maintenance personnel to view the fault details in real time and perform remote diagnosis operations.

[0086] The present disclosure provides a control and management system applied to an ARM server, including: an out-of-band JTAG link management module 10, configured to monitor multiple JTAG signals output by the ARM processor system-on-chip 20 after the ARM server is powered on, identify the fault information during the startup and operation of the ARM processor system-on-chip 20, and send the fault information to the BMC 30; and further configured to generate a JTAG link routing control signal and send it to the ARM processor system-on-chip 20; the ARM processor system-on-chip 20, configured to send multiple JTAG signals carrying the startup information and operation information of the ARM processor system-on-chip 20 to the out-of-band JTAG link management module 10 after the ARM server is powered on; and further configured to receive and respond to the JTAG link routing control signal to switch the topology mode of the JTAG link; the BMC 30, configured to receive and record the fault information and send the fault information to a remote operation and maintenance terminal. In this way, the out-of-band JTAG link management module 10 operates independently of the ARM processor system-on-chip 20, parallelly parses multiple JTAG signals in real time to obtain the fault information, generates a JTAG link routing control signal to implement the switching of the JTAG link mode, and at the same time transmits the fault information to the BMC 30 to achieve structured storage and remote alarm. Through the technical solution of the present disclosure, the core problems of low efficiency of manual point-by-point detection, strong physical operation dependence, and CPU downtime monitoring failure in the traditional solution are solved, significantly reducing the operation and maintenance delay and cost, and providing high-reliability and low-latency operation and maintenance support for the large-scale deployment of ARM servers.

[0087] In one example, the out-of-band JTAG link management module 10 is implemented by a complex programmable logic device CPLD or a field programmable gate array FPGA, such as Figure 2 shown, including: a JTAG control module 101 and a JTAG slave device module 102.

[0088] In the technical solution of the present disclosure, the out-of-band JTAG link management module 10 implemented based on a complex programmable logic device CPLD or a field programmable gate array FPGA. Combining Figure 2 and Figure 3Taking the CPLD to implement the out-of-band JTAG link management module 10 function as an example, the JTAG control module 101 (JTAG Switch, JTAG SW) and the JTAG slave device module 102 (JTAG SLAVE) are integrated internally to respectively implement the parallel analysis of multiple JTAG signals of the ARM processor system-on-chip 20 and the directional transmission of fault information. The specific implementation logic is as follows:

[0089] The JTAG control module 101 is used to monitor multiple JTAG ports on the ARM processor system-on-chip 20 to obtain corresponding multiple JTAG signals, parse the multiple JTAG signals in parallel through the CPLD or FPGA to obtain the fault information, and send the fault information to the JTAG slave device module 102.

[0090] In this example, the JTAG control module 101 captures the original signal streams of multiple JTAG signals by monitoring multiple JTAG ports on the ARM processor system-on-chip 20. In the CPLD or FPGA, after preprocessing the multiple original JTAG signals to eliminate the high-frequency noise interference in the original signals, the multiple JTAG signals are analyzed in parallel to obtain the analysis results. A fault information data packet containing the fault type, timestamp and signal source is generated according to the analysis results, and the fault information is transmitted to the JTAG slave device module 102.

[0091] The JTAG slave device module 102 is used to receive the fault information and send it to the BMC 30 through a multiplexer.

[0092] In this example, the JTAG slave device module 102 receives the data packet of fault information sent by the JTAG control module 101 and routes it to the BMC30 through a multiplexer (MUX). Specifically, the multiplexer selects the transmission path according to the BMC30 interface status. If the BMC30 interface is idle, the high-speed direct connection mode is adopted to transmit the complete data packet at one time through a parallel bus (such as 8-bit GPIO); if the BMC30 interface is busy, the serial mode is enabled to split the data packet into single-byte units and transmit it in time-sharing through the I2C interface to avoid data blocking.

[0093] In one example, the JTAG control module 101, such as Figure 2 As shown, it includes a monitoring unit 1011 and a fault judgment unit 1012:

[0094] The monitoring unit 1011 is used to monitor multiple JTAG ports of the ARM processor system on chip 20 to obtain multiple JTAG signals.

[0095] In this example, the monitoring unit 1011 uses a signal capture circuit inside the CPLD or FPGA to collect in real time multiple original JTAG signals output from multiple JTAG ports on the system-on-chip 20 of the ARM processor, and preprocesses the original signals to remove high-frequency noise interference. Subsequently, the stable multiple JTAG signals are transmitted to the fault judgment unit 1012 for parallel analysis and fault judgment.

[0096] The fault judgment unit 1012 is configured to, when identifying a JTAG signal fault, detect whether the power-on completion indication signal of the system-on-chip 20 of the ARM processor is normally issued; if the power-on completion indication signal is not normally issued, determine the first fault information; if the power-on completion indication signal is normally issued, start a detection process for the CPU management core in the system-on-chip 20 of the ARM processor to obtain a detection result.

[0097] In this example, when the fault judgment unit 1012 detects a JTAG signal fault anomaly, it triggers the power-on completion indication signal detection logic in the system-on-chip 20 of the ARM processor, including:

[0098] Read the level status of the CPU_PWR_GOOD pin of the system-on-chip 20 of the ARM processor. If it is not pulled high to the effective level after power-on, it is determined that the power-on completion indication signal is not normally issued, and the first fault information is generated based on the judgment result and fed back to the BMC 30.

[0099] If the level of the CPU_PWR_GOOD pin is pulled high to the effective level after power-on, it is determined that the power-on completion indication signal is normally issued. At this time, it is necessary to further analyze and judge the source of the fault. Therefore, a detection process for the CPU management core in the system-on-chip 20 of the ARM processor is started to obtain a detection result for analysis and judgment.

[0100] In one example, when the fault judgment unit 1012 starts a detection process for the CPU management core to obtain a detection result, it is specifically configured to: if the startup completion signal of the CPU management core is not detected within a preset time, determine the second fault information; if the startup completion signal of the CPU management core is detected within a preset time, determine that the ARM server is running normally.

[0101] In this example, after the fault judgment unit 1012 detects the power-on completion execution signal of the ARM processor system-on-chip 20, it starts a timer and continuously monitors the startup completion signal SCP_READY of the CPU management core. If the startup completion signal is detected to be stable at a high level within a preset time, for example, 10 seconds, it is determined that the ARM server starts and runs normally; if no valid signal is detected within the preset time, it is determined that there is a "CPU startup anomaly" fault, and the second fault information is generated and the system status parameters (such as voltage value, the last signal sampling result) at the timeout moment are recorded for subsequent diagnostic analysis.

[0102] In one example, the ARM processor system-on-chip 20 includes a main CPU processor and a slave CPU processor.

[0103] In this example, the ARM processor system-on-chip 20 adopts a multi-CPU architecture, including a main CPU processor and at least one slave CPU processor. Among them, the main and slave CPU processors each have an independent and identical configured hardware interface, including a first general-purpose input / output GPIO and multiple JTAG ports, to implement the out-of-band JTAG link management module 10 for dynamic JTAG link control and multi-dimensional status monitoring. Among them:

[0104] The first GPIO is used to receive the JTAG link routing control signal.

[0105] Taking the dual-CPU processor as an example, as Figure 3 shown, the first general-purpose input / output GPIO interfaces of the main CPU processor (CPU0) and the slave CPU processor (CPU1) are used to receive the JTAG link routing control signal JTAG_DAISYCHAIN_DIS from the out-of-band JTAG link management module 10, so that the ARM processor system-on-chip 20 switches the topology mode of the JTAG link according to this signal. The correspondence between the JTAG_DAISYCHAIN_DIS signal level and the JTAG link mode is as follows: when the signal level is low, it indicates that the merging mode is enabled; when the signal level is high, it indicates that the independent mode is enabled.

[0106] The multiple JTAG ports at least include: a debug access port, a peripheral management port, a power management port, and a system-on-chip port. Among them, as Figure 3 shown:

[0107] Debug Access Port (JTAG_DAP): Provides access to the CPU core register set. For example, the JTAG_DAP of the main CPU processor supports full register read and write, and sends the CPU0_JTAG_DAP signal to the out-of-band JTAG link management module 10; the JTAG_DAP of the slave CPU processor only opens some registers to reduce the debug load and sends the CPU1_JTAG_DAP signal to the out-of-band JTAG link management module 10.

[0108] Peripheral Management Port (JTAG_IPP): Monitors the status of the peripheral controllers connected to the CPU. For example, the JTAG_IPP of the main CPU processor covers controllers such as PCIe / USB, and sends the CPU0_JTAG_IPP signal to the out-of-band JTAG link management module 10; the JTAG_IPP of the slave CPU processor only monitors the basic peripherals and sends the CPU1_JTAG_IPP signal to the out-of-band JTAG link management module 10.

[0109] Power Management Port (JTAG_PM): Transmits data such as voltage / temperature of the power module. For example, the JTAG_PM of the main CPU processor samples the core voltage and sends the CPU0_JTAG_PM signal to the out-of-band JTAG link management module 10; the JTAG_PM of the slave CPU processor monitors the I / O voltage and sends the CPU1_JTAG_PM signal to the out-of-band JTAG link management module 10.

[0110] System-on-Chip Port (JTAG_SoC): Feeds back the global status information of the system-on-chip. For example, the JTAG_SoC of the main CPU processor carries the secure boot verification result and the multi-core synchronization flag bit, and sends the CPU0_JTAG_SoC signal to the out-of-band JTAG link management module 10; the JTAG_SoC of the slave CPU processor only feeds back the local boot status and sends the CPU1_JTAG_SoC to the out-of-band JTAG link management module 10.

[0111] For the topology mode switching of the JTAG link, the first GPIO interfaces of the master and slave CPU processors are connected to the out-of-band JTAG link management module 10, which receives JTAG link routing control signals in real time. When the first GPIO of the master and slave CPU processors receives a high-level JTAG link routing control signal, the JTAG links of the master and slave CPU processors are switched to the independent mode. Taking the 2 groups of JTAG ports on the above master and slave CPU processors as an example, in the independent mode, the 2 groups of ports independently send JTAG signals to the out-of-band JTAG link management module 10. When the first GPIO of the master and slave CPU processors receives a low-level JTAG link routing control signal, the JTAG links of the master and slave CPU processors are switched to the combined mode. In the combined mode, all JATG signals are aggregated and sent to the out-of-band JTAG link management module 10 through a main port (such as JTAG_DAP).

[0112] In addition, based on the above combined mode, a group of JTAG signals in one CPU processor can be arranged and combined and then routed to another CPU processor, and the JTAG signals are output through the main port of one CPU processor.

[0113] It should be noted that the JTAG ports of the present disclosure include but are not limited to the above four types (debug access port, peripheral management port, power management port, and system-on-chip port). Any physical or logical interface that interacts with the out-of-band JTAG link management module 10 and is set inside the system-on-chip 20 of the ARM processor belongs to the protection scope of the JTAG ports described in the present disclosure, including but not limited to extended debug ports, security engine status feedback ports, multi-core synchronization monitoring ports, etc. The core feature of such ports is that they establish a communication link with the out-of-band JTAG link management module 10 through the standard JTAG protocol or a compatibility protocol, and are associated with the startup and running status, debug data, or control instructions of the system-on-chip 20 of the ARM processor. Their function implementation and interaction logic are all covered by the technical solution of the present disclosure.

[0114] In an example, an in-position signal output port is provided on the slave CPU processor, which is used to send an in-position output signal to the master CPU processor, BMC 30, and CPLD or FPGA to detect whether the slave CPU processor is in position.

[0115] In this example, as Figure 3As shown, the in-position output signal is transmitted from the CPU processor to the main CPU processor, BMC 30, and CPLD / FPGA through the set in-position signal output port (SLAVE_PRESENT_N) to inform whether the slave CPU processor is correctly in position. Among them, a bit signal detection port (SLAVE_PRESENT_N) is set on the main CPU processor. It should be noted that due to the different sending and receiving entities of the in-position signal, SLAVE_PRESENT_N is the in-position signal detection port on the main CPU processor and the in-position signal output port on the slave CPU processor; BMC 30 is used to update the system topology configuration by monitoring the in-position state of the slave CPU processor; the CPLD or FPGA's JTAG control module 101 receives the in-position signal through the input buffer and triggers the internal state machine to switch. The specific logic is as follows:

[0116] If the slave CPU processor is in position, the JTAG control module 101 reads the JTAG signal of the slave CPU processor and sends a JTAG link routing control signal.

[0117] In this example, when the SLAVE_PRESENT_N signal is at a low level (the slave CPU processor is in position), the JTAG control module 101 inside the CPLD or FPGA starts the JTAG signal acquisition and processing process of the slave CPU processor; at the same time, the JTAG control module 101 generates a JTAG link routing control signal for the slave CPU processor and sends it to the first GPIO interface of the slave CPU processor to trigger it to adjust the topology mode of the JTAG link.

[0118] If the slave CPU processor is not in position, the JTAG control module 101 stops reading the JTAG signal of the slave CPU processor and stops sending the JTAG link routing control signal to the slave CPU processor.

[0119] In this example, if the SLAVE_PRESENT_N signal is at a high level (the slave CPU processor is not in position), the JTAG control module 101 of the CPLD or FPGA disables all JTAG signal channels in the slave CPU processor: turns off the enable signal of the corresponding MUX channel and stops the JTAG_DAP, JTAG_IPP, JTAG_PM, and JTAG_SoC signal sampling and parsing operations of the slave CPU processor; at the same time, resets the state machine and timer dedicated to the slave CPU processor, releases the hardware resources to avoid invalid power consumption. In addition, the JTAG control module 101 stops generating and sending the JTAG link routing control signal for the slave CPU processor to prevent signal conflicts or misoperations and ensure the stable operation of the JTAG links of the main CPU processor and other in-position devices.

[0120] In one example, the BMC 30 includes a JTAG master device module, which is configured to receive fault information of the JTAG master device module and record the fault information in a time record table through the BMC 30; the BMC 30 is further configured to generate an alarm message according to the fault information and feedback the alarm message to the remote operation and maintenance terminal.

[0121] In this example, as Figure 3 shown, the BMC 30 integrates a JTAG master device module (JTAG MASTER), and is connected to the out-of-band JTAG link management module 10 through a multiplexer and lines BMC_JTAG and BMC_JTAG_MUX to receive a data packet of fault information (including a fault code, a timestamp, and associated parameters). The JTAG master device module of the BMC 30 parses the received data packet and writes it into a time record table of the System Event Log (SEL) for storage. When a new fault information record is added to the time record table, the BMC 30 extracts the fault type code and timestamp of the most recent record, encapsulates them into an alarm message, and sends the alarm message to the remote operation and maintenance terminal. After receiving the alarm message, the operation and maintenance terminal parses the message content and displays information such as the fault type, the occurrence time, and the associated hardware node through a user display interface.

[0122] In one example, the JTAG master device module is further configured to send a firmware upgrade instruction or an information acquisition instruction to the CPLD or FPGA through the multiplexer.

[0123] In this example, after the BMC 30 receives a firmware upgrade instruction or an information acquisition instruction sent by a user through the remote operation and maintenance terminal, the JTAG master device module provided in the BMC 30 is connected to the instruction receiving ports of the multiplexer, the line CPLD_JTAG, and the CPLD / FPGA through a second GPIO to transmit the user's firmware upgrade instruction and information acquisition instruction, that is, a BMC_CPLD_SELs signal.

[0124] Among them, the firmware upgrade instruction is used to update the hardware logic code of the CPLD or FPGA, for example, to repair routing logic defects of a debugging link, optimize a signal parsing algorithm, or enhance anti-interference capabilities, so as to ensure the function iteration and reliability improvement of the out-of-band JTAG link management module 10. The information acquisition instruction is used to read the internal state information of the CPLD or FPGA in real time, including the current JTAG link configuration mode, the value of a fault counter, etc., to provide visual data on the underlying hardware operation state for operation and maintenance personnel, and support root cause analysis of faults and system health assessment.

[0125] Through the above instruction interaction, without relying on processor resources, BMC30 can directly control the function upgrade and status monitoring of the CPLD or FPGA, strengthening the remote operation and maintenance capabilities of the ARM server.

[0126] In one example, the system further includes a local interface module, which is used for an external debugging terminal to connect to the out-of-band JTAG link management module 10 through the local interface module to obtain the fault information; it is also used for the external debugging terminal to send a JTAG link routing control signal to the out-of-band JTAG link management module 10 through the local interface module; the external debugging terminal is hardware or software connected to the ARM server.

[0127] In this example, the local interface module is directly connected to the out-of-band JTAG link management module 10 (CPLD / FPGA) through a physical interface such as a socket, etc., supporting on-site operation and maintenance personnel to access debugging tools to obtain fault information. As Figure 3 shown, the local interface module integrates standardized hardware interfaces (such as HDR2 or CON1 connectors), and its core functions include:

[0128] Reading the data packet of the fault information from the JTAG control module 101 of the out-of-band JTAG link management module 10 through a parallel bus or a serial protocol; supporting the external debugging tool to send a debugging instruction (such as a JTAG link routing control signal) through the interface, and sending the debugging instruction to the JTAG control module 101 in the out-of-band JTAG link management module 10 for execution, responding to the instruction and responding back to the debugging tool. Through connecting to this interface, on-site operation and maintenance personnel can directly access the fault storage area of the out-of-band JTAG link management module 10 or monitor the JTAG link status in real time, without relying on the remote channel of BMC30, which is applicable to network isolation environments or emergency hardware diagnosis scenarios, significantly improving the on-site problem location efficiency.

[0129] In one example, BMC30 is also used to send a JTAG link routing control signal and a local interface control signal to the out-of-band JTAG link management module 10.

[0130] As Figure 3 shown, when BMC30 receives the JTAG link routing switching instruction from the remote operation and maintenance end, it sends the JTAG link routing control signal CPU_JTAG_DSYCHN_DIS_BMC_GPIO to the out-of-band JTAG link management module 10, so that the out-of-band JTAG link management module 10 responds to this signal and forwards the JTAG link routing control signal to the ARM processor system-on-chip 20, thereby realizing the switching of the JTAG link topology mode in the master and slave CPU processors.

[0131] In addition, BMC30 is also used to send the local interface control signal BMC_CON1_SEL_BMC_GPIO to the out-of-band JTAG link management module 10, which is used to control the connection and data transmission between the local interface module and the out-of-band JTAG link management module 10.

[0132] In addition to BMC30 being able to send JTAG link routing control signals and local interface control signals to the out-of-band JTAG link management module 10, the system can also set a jumper module (Jumper Setting) to achieve the above functions.

[0133] The present disclosure also provides a control and management method, which is applied to the out-of-band JTAG link management module in an ARM server. The out-of-band JTAG link management module is respectively communicatively connected to the system-on-chip of the ARM processor and the baseboard management controller BMC, as Figure 4 shown, the method includes:

[0134] Step 401: After the ARM server is powered on, monitor multiple JTAG signals output by the system-on-chip of the ARM processor. The multiple JTAG signals carry the startup information and running information of the system-on-chip of the ARM processor;

[0135] Step 402: According to the multiple JTAG signals, identify the fault information during the startup and running processes of the system-on-chip of the ARM processor;

[0136] Step 403: Send the fault information to the BMC, so that the BMC records the fault information and sends it to the remote operation and maintenance end.

[0137] In one example, the out-of-band JTAG link management module is implemented by a complex programmable logic device CPLD or a field programmable gate array FPGA.

[0138] In one example, the system-on-chip of the ARM processor includes a main CPU processor and a slave CPU processor. The main CPU processor and the slave CPU processor are respectively provided with a first general-purpose input / output GPIO and multiple JTAG ports. The method further includes:

[0139] Generate a JTAG link routing control signal and send it to the first GPIO of the system-on-chip of the ARM processor to switch the topology mode of the JTAG link;

[0140] The multiple JTAG ports at least include: a debug access port, a peripheral management port, a power management port, and a system-on-chip port.

[0141] In one example, the monitoring of multiple JTAG signals output by the system-on-chip of the ARM processor includes:

[0142] Monitor multiple JTAG ports of the System on Chip (SoC) of the ARM processor to obtain corresponding multiple JTAG signals;

[0143] Identify fault information of the ARM processor SoC during startup and operation according to the JTAG signals, including:

[0144] Parallelly analyze the multiple JTAG signals through the CPLD or FPGA to obtain the fault information;

[0145] Send the fault information to the BMC, including:

[0146] Use a multiplexer to send the fault information to the BMC.

[0147] In one example, the parallelly analyzing the multiple JTAG signals through the CPLD or FPGA to obtain the fault information includes:

[0148] When a JTAG signal fault is identified, detect whether the power-on completion indication signal of the ARM processor SoC is normally sent;

[0149] If the power-on completion indication signal is not normally sent, determine the first fault information;

[0150] If the power-on completion indication signal is normally sent, start a detection process for the CPU management core in the ARM processor SoC to obtain a detection result.

[0151] In one example, the starting a detection process for the CPU management core in the ARM processor SoC includes:

[0152] If the startup completion signal of the CPU management core is not detected within a preset time, determine the second fault information;

[0153] If the startup completion signal of the CPU management core is detected within a preset time, determine that the ARM server is running normally.

[0154] In one example, the method further includes:

[0155] Receive an in-position output signal sent from the in-position signal output port of the CPU processor to detect whether the slave CPU processor is in position;

[0156] If the slave CPU processor is in position, read the JTAG signal of the slave CPU processor and send a corresponding JTAG link routing control signal;

[0157] If the slave CPU processor is not present, stop reading the JTAG signal of the slave CPU processor and stop sending the JTAG link routing control signal to the slave CPU processor.

[0158] In one example, the method further includes:

[0159] Receiving a firmware upgrade instruction or an information acquisition instruction from the BMC through a multiplexer;

[0160] Executing the firmware upgrade instruction to update the logic code of the CPLD or FPGA, or responding to the information acquisition instruction to feedback status information.

[0161] In one example, the method further includes:

[0162] Connecting to an external debugging terminal through a local interface module to obtain the fault information or receive the JTAG link routing control signal sent by the external debugging terminal;

[0163] The external debugging terminal is hardware or software connected to the ARM server.

[0164] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0165] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement the embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely exemplary and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0166] As Figure 5 shown, the electronic device 500 includes a computing unit 501, which can execute various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0167] Multiple components in device 500 are connected to I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a disk, an optical disc, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0168] Computing unit 501 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Computing unit 501 executes the various methods and processes described above, such as the control management method. For example, in some embodiments, the control management method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 500 via ROM 502 and / or communication unit 509. When the computer program is loaded into RAM 503 and executed by computing unit 501, one or more steps of the control management method described above can be executed. Alternatively, in other embodiments, computing unit 501 can be configured to execute the control management method in any other suitable way (e.g., by means of firmware).

[0169] The various embodiments of the systems and technologies described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs, which can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special or general-purpose programmable processor, receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0170] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing devices, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as an independent software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0171] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0172] In order to provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0173] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0174] A computer system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

[0175] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. No limitation is imposed herein.

[0176] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0177] As described above, the above are only specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by this disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be subject to the protection scope of the claims.

Claims

1. A control and management system, characterized in that, The system is applied to an ARM server, and the system includes: an out-of-band JTAG link management module, an ARM processor system-on-chip, and a baseboard management controller BMC; the out-of-band JTAG link management module is communicatively connected to the ARM processor system-on-chip and the BMC respectively; The out-of-band JTAG link management module is used for, after the ARM server is powered on, monitoring multiple JTAG signals output by the ARM processor system-on-chip, identifying fault information during the startup and operation of the ARM processor system-on-chip, and sending the fault information to the BMC; and is also used for generating JTAG link routing control signals and sending them to the ARM processor system-on-chip; The ARM processor system-on-chip is used for, after the ARM server is powered on, sending multiple JTAG signals to the out-of-band JTAG link management module, where the multiple JTAG signals carry startup information and operation information of the ARM processor system-on-chip; and is also used for receiving and responding to the JTAG link routing control signals to switch the topology mode of the JTAG link; The BMC is used for receiving and recording the fault information and sending the fault information to a remote operation and maintenance end; The out-of-band JTAG link management module is implemented by a complex programmable logic device CPLD or a field-programmable gate array FPGA, and includes: a JTAG control module and a JTAG slave device module; The JTAG control module is used for monitoring multiple JTAG ports on the ARM processor system-on-chip to obtain corresponding multiple JTAG signals, parallelly analyzing the multiple JTAG signals through the CPLD or FPGA to obtain the fault information, and sending the fault information to the JTAG slave device module; The JTAG slave device module is used for receiving the fault information and sending it to the BMC through a multiplexer.

2. The system according to claim 1, wherein The JTAG control module includes a monitoring unit and a fault judgment unit: The monitoring unit is used for monitoring multiple JTAG ports of the ARM processor system-on-chip to obtain multiple JTAG signals; The fault judgment unit is used for, when it identifies a JTAG signal fault, detecting whether a power-on completion indication signal of the ARM processor system-on-chip is normally sent; If the power-on completion indication signal is not normally sent, determining first fault information; If the power-on completion indication signal is normally sent, starting a detection process for the CPU management core in the ARM processor system-on-chip and obtaining a detection result.

3. The system according to claim 2, wherein When the fault judgment unit starts a detection process for the CPU management core and obtains a detection result, it is specifically used for: If the startup completion signal of the CPU management core is not detected within a preset time, determining second fault information; If the startup completion signal of the CPU management core is detected within a preset time, determining that the ARM server is operating normally.

4. The system according to claim 1, wherein The ARM processor system-on-chip includes a main CPU processor and a slave CPU processor; A first general-purpose input / output (GPIO) and a plurality of Joint Test Action Group (JTAG) ports are respectively provided in the main CPU processor and the slave CPU processor; The first GPIO is used to receive the JTAG link routing control signal; The plurality of JTAG ports at least include: a debug access port, a peripheral management port, a power management port, and a system-on-chip port.

5. The system according to claim 4, wherein An in-position signal output port is provided on the slave CPU processor, and is used to send an in-position output signal to the main CPU processor, the BMC, the CPLD or the FPGA to detect whether the slave CPU processor is in position; If the slave CPU processor is in position, the JTAG control module reads the JTAG signal of the slave CPU processor and sends a JTAG link routing control signal; If the slave CPU processor is not in position, the JTAG control module stops reading the JTAG signal of the slave CPU processor and stops sending the JTAG link routing control signal to the slave CPU processor.

6. The system according to claim 1, wherein The BMC includes a JTAG master device module, which is used to receive the fault information of the JTAG master device module, and record the fault information in a time record table through the BMC; The BMC is also used to generate an alarm message according to the fault information and feedback it to the remote operation and maintenance end.

7. The system according to claim 6, wherein The JTAG master device module is also used to send a firmware upgrade instruction or an information acquisition instruction to the CPLD or the FPGA through the multiplexer.

8. The system according to claim 1, characterized in that, The system further includes a local end interface module, which is used for an external debugging terminal to connect to the out-of-band JTAG link management module through the local end interface module to obtain the fault information; and is also used for the external debugging terminal to send a JTAG link routing control signal to the out-of-band JTAG link management module through the local end interface module; the external debugging terminal is hardware or software connected to the ARM server.

9. A control and management method, characterized in that, An out-of-band JTAG link management module applied to an ARM server, the out-of-band JTAG link management module is respectively communicatively connected to an ARM processor system-on-chip and a baseboard management controller (BMC), and the method includes: After the ARM server is powered on, monitor a plurality of JTAG signals output by the ARM processor system-on-chip, and the plurality of JTAG signals carry the startup information and operation information of the ARM processor system-on-chip; According to the plurality of JTAG signals, identify the fault information of the ARM processor system-on-chip during startup and operation; Send the fault information to the BMC, so that the BMC records the fault information and sends it to the remote operation and maintenance end; The out-of-band JTAG link management module is implemented by a complex programmable logic device (CPLD) or a field-programmable gate array (FPGA); The ARM processor system-on-chip includes a main CPU processor and a slave CPU processor, and a first general-purpose input / output (GPIO) and a plurality of JTAG ports are respectively provided in the main CPU processor and the slave CPU processor, and the method further includes: Generate a JTAG link routing control signal and send it to the first GPIO of the ARM processor system-on-chip to switch the topology mode of the JTAG link; The multiple JTAG ports at least include: a debug access port, a peripheral management port, a power management port, and a system-on-chip port; Monitoring multiple JTAG signals output by the ARM processor system-on-chip, including: Monitoring the multiple JTAG ports of the ARM processor system-on-chip to obtain corresponding multiple JTAG signals; According to the JTAG signals, identifying fault information during the startup and operation of the ARM processor system-on-chip, including: Parallelly parsing the multiple JTAG signals through the CPLD or FPGA to obtain the fault information; Sending the fault information to the BMC, including: Using a multiplexer to send the fault information to the BMC.

10. The method according to claim 9, wherein The parallelly parsing the multiple JTAG signals through the CPLD or FPGA to obtain the fault information includes: When a JTAG signal fault is identified, detecting whether the power-on completion indication signal of the ARM processor system-on-chip is normally issued; If the power-on completion indication signal is not normally issued, determining the first fault information; If the power-on completion indication signal is normally issued, starting a detection process for the CPU management core in the ARM processor system-on-chip to obtain a detection result.

11. The method according to claim 10, characterized in that The starting a detection process for the CPU management core in the ARM processor system-on-chip includes: If the startup completion signal of the CPU management core is not detected within a preset time, determining the second fault information; If the startup completion signal of the CPU management core is detected within a preset time, determining that the ARM server is running normally.

12. The method according to claim 9, wherein The method further includes: Receiving an in-position output signal sent from the in-position signal output port of the CPU processor to detect whether the slave CPU processor is in position; If the slave CPU processor is in position, reading the JTAG signal of the slave CPU processor and sending a corresponding JTAG link routing control signal; If the slave CPU processor is not in position, stopping reading the JTAG signal of the slave CPU processor and stopping sending the JTAG link routing control signal to the slave CPU processor.

13. The method according to claim 9, wherein The method further includes: Receiving a firmware upgrade instruction or an information acquisition instruction from the BMC through a multiplexer; Executing the firmware upgrade instruction to update the logic code of the CPLD or FPGA, or responding to the information acquisition instruction to feedback status information.

14. The method according to claim 9, wherein The method further includes: Connecting to an external debug terminal through a local interface module to obtain the fault information or receive a JTAG link routing control signal sent by the external debug terminal; The external debug terminal is hardware or software connected to the ARM server.

15. An electronic device, characterized in that, Including: At least one processor; And a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to any one of claims 9-14.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are for causing a computer to execute the method according to any one of claims 9-14.

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