A distributed memory configuration method, device, equipment, medium and product

Abstract

The application relates to a distributed memory configuration method, device, equipment, medium and product. The method is applied to a multi-core micro control unit (MCU) system. The multi-core MCU system comprises a global memory, a plurality of local memories and a plurality of cores. One local memory corresponds to one core. The method comprises the following steps: acquiring access information of each target data segment in at least one target data segment; the target data segment is a data segment of at least one intermediate file after a first service is compiled; the access information is used for representing the frequency of the target data segment accessing the plurality of cores during runtime; the first service is any service to be run in the MCU system; and based on the access information of each target data segment, a target memory for storing each target data segment is configured in the global memory and the plurality of local memories. The scheme is used for memory allocation of the data segment of at least one intermediate file after the first service is compiled, and the access information during the runtime of each data segment is considered, so that reasonable allocation is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of vehicles, in particular to a distributed memory configuration method and device, equipment, medium and product. BACKGROUND

[0002] With the development of multi-core microcontroller technology, the architecture of random access memory (RAM) has also undergone great changes, gradually evolving from the previous centralized RAM to a distributed RAM architecture. The distributed RAM architecture consists of a local RAM corresponding to each CPU core and a global RAM shared by multiple cores.

[0003] When the CPU accesses the two types of RAM, the following characteristics are observed: when the CPU core accesses the local RAM, it does not pass through the system bus, and the speed is very fast, but the capacity of the local RAM is generally small. When the CPU accesses the global RAM, it needs to pass through the bus, and the speed is slightly slower, but the space of the global RAM is generally larger. Therefore, it is particularly important to effectively manage the allocation of local RAM and global RAM resources.

[0004] Currently, the compiler or manual memory segment allocation method often cannot fully utilize the speed advantage of the local RAM, and cannot effectively cope with the access delay of the global RAM, thereby affecting the overall system performance. SUMMARY

[0005] The present application provides a distributed memory configuration method, device, equipment, medium and product, which is used for memory allocation of data segments of at least one intermediate file compiled by a first service, and considers the access information of each data segment at runtime, to achieve reasonable allocation.

[0006] The technical solution adopted by the present application is as follows:

[0007] In a first aspect, the present application provides a distributed memory configuration method, which is applied to a multi-core microcontroller unit (MCU) system. The multi-core MCU system includes a global memory, a plurality of local memories, and a plurality of cores. One local memory corresponds to one core. The method includes: obtaining access information of each target data segment in at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by a first service; the access information is used to represent the frequency of accessing the plurality of cores by the target data segment at runtime; and the first service is any service to be run in the MCU system.

[0008] Based on the access information of the at least one target data segment, a target memory for storing each target data segment is configured in the global memory and the plurality of local memories.

[0009] Based on the above means, the multi-core micro control unit MCU system includes a global memory, a plurality of local memories, and a plurality of cores, one local memory corresponds to one core, and the memory configuration scheme of the related art is generally used to configure the core with the kernel. The scheme of the present application is used to allocate memory to the target data segment of the at least one intermediate file compiled by the first service, and when the memory is allocated to the target data segment, the access information of each data segment at runtime is considered, the reasonable allocation is realized, and the running efficiency of the first service is improved, and the running effect of the multi-core micro control unit MCU system is improved.

[0010] In some implementations, based on the access information of the at least one target data segment, target memories for storing each target data segment are configured in the global memory and the plurality of local memories, including: in the access information of each target data segment, determining a total access frequency of each target data segment; the total access frequency is used to represent the sum of the frequency of the target data segment accessing each core in the plurality of cores; based on the total access frequency of each target data segment, determining a priority of each target data segment; and in order of the priority of each target data segment, based on the access information of each target data segment, configuring the target memory for storing each target data segment in the global memory and the plurality of local memories.

[0011] Based on the above means, the priority is configured when the plurality of target data segments are allocated memory, and the allocation is performed based on the order of the priority. Since the priority is determined based on the total access frequency of the target data segment, the target data segment with high access frequency can be allocated memory in priority, which can ensure the rationality of the memory configuration of the frequently used target data segment. For example, when the memory is insufficient, the priority-based configuration method can ensure that the frequently used target data segment is used in priority, and the impact on the first service is small, thereby improving the running efficiency of the first service.

[0012] In some implementations, based on the access information of the at least one target data segment, target memories for storing each target data segment are configured in the global memory and the plurality of local memories, including: based on the access information of each target data segment, determining an analysis result of each target data segment; based on the analysis result of each target data segment, configuring the target memory of the target data segment in the global memory and the plurality of local memories; and the analysis result includes at least one of the following: a hot type, a core type, a shared type, and a size type of the target data segment.

[0013] Based on the above means, when the memory is allocated, the hot type, the core type, the shared type, and the size type of the target data segment are considered, and the allocation of the memory is more in line with the actual demand, so that the memory configuration is more reasonable, the first service runs efficiently, and the multi-core micro control unit MCU system runs efficiently.

[0014] In some implementations, the analysis results for each target data segment are determined based on the access information of each target data segment, including: determining the total access frequency of the target data segment in the access information of the target data segment; if the access frequency is greater than or equal to a first threshold, the hot / cold type is determined to be hot; if the total access frequency is less than the first threshold, the hot / cold type is determined to be cold.

[0015] And / or, in the access information of the target data segment, determine the single-core access frequency of the target data segment, and determine the kernel with the highest single-core access frequency as the core-friendly type;

[0016] And / or, in the access information of the target data segment, determine the single-core access frequency of the target data segment. If there are multiple single-core access frequencies with non-zero values, then determine the sharing type as inter-core sharing; if there is only one single-core access frequency with a non-zero value, then determine the sharing type as non-inter-core sharing.

[0017] And / or, in the access information of the target data segment, determine the data size of the target data segment; if the data size is greater than or equal to the second threshold, determine the size type as large block; if the data size is less than the second threshold, determine the size type as small block.

[0018] Based on the above methods, the process of determining the analysis results (hot / cold type, nucleus type, shared type, and size type) of each target data segment based on its access information is described. It can be seen that this implementation process is convenient, reliable, and flexible in its selection.

[0019] In some implementations, when the analysis results include hot / cold types and nucleus-friendly types, the target memory of the target data segment is configured in global memory and multiple local memory locations based on the analysis results of each target data segment. This includes: if the hot type of the analysis result is hot, then the target memory is determined to be the local memory corresponding to the kernel pointed to by the nucleus-friendly type among multiple local memory locations; if the hot / cold type of the analysis result is cold, then the target memory is determined to be global memory.

[0020] Based on the above methods, for hot target data segments, due to their high access frequency, they are configured in layout memory. Since local memory is directly connected to the kernel, the data response rate is improved in the time dimension. Specifically, they can be configured in the local memory corresponding to the kernel with the highest access frequency of the target data segment to ensure the speed of most accesses. For cold target data segments, due to their low access frequency, they are configured in global memory to reduce the occupation of local memory and improve memory utilization efficiency in the space dimension.

[0021] In some implementations, when the analysis results include shared types, the target memory of the target data segment is configured in global memory and multiple local memory based on the analysis results of each target data segment. This includes: if the shared type of the analysis results is inter-core shared, then the target memory is determined to be global memory; if the shared type of the analysis results is not inter-core shared, then the target memory is determined to be one of the multiple local memory segments.

[0022] Based on the above methods, for shared target data segments, since these segments typically access multiple kernels, allocating them to global RAM facilitates interaction between kernels, optimizes memory usage efficiency, and reduces unnecessary data copying and synchronization. For non-shared target data segments, they can be allocated to a single local memory location within multiple local memory locations. It can be seen that this allocation is reasonable and efficient.

[0023] In some implementations, when the analysis results include size types, the target memory for each target data segment is configured in global memory and multiple local memory locations based on the analysis results for each target data segment. This includes: if the size type of the analysis result is large, then the target memory is determined to be global memory; if the size type of the analysis result is small, then the target memory is determined to be one of the multiple local memory locations.

[0024] Based on the above methods, large target data segments, due to their large memory footprint and the large global memory capacity, can be configured in global memory. Small target data segments, due to their small memory footprint, can be configured in one of multiple local memory locations. It can be seen that the allocation is reasonable and efficient.

[0025] In some implementations, obtaining access information for at least one target data segment includes: running a first service in a multi-core MCU system; collecting the frequency of each target data segment accessing multiple cores during the operation of the first service within a first time period, thereby obtaining access information for at least one target data segment.

[0026] Based on the above methods, the access information of each target data segment is actually collected during the operation of the first service, which has the characteristics of high accuracy and high reliability.

[0027] In some implementations, the target data segment includes: a first data segment, a second data segment, and a third data segment; wherein, the first data segment includes initialized global variables and static variables; the second data segment includes uninitialized global variables and static variables; and the third data segment includes local variables and function calls.

[0028] Based on the above methods, the target data segment was further segmented, which enabled reasonable memory allocation for the segmented initialized global and static variables, uninitialized global and static variables, local variables, and function call data, thereby improving the efficiency of data usage.

[0029] Secondly, this application provides a distributed memory configuration device, which is deployed in a multi-core microcontroller unit (MCU) system. The multi-core MCU system includes global memory, multiple local memories, and multiple cores, with one local memory corresponding to one core. The device includes:

[0030] The acquisition unit is used to acquire access information for each target data segment in at least one target data segment; the target data segment is the data segment of at least one intermediate file after the first service is compiled; the access information is used to characterize the frequency of the target data segment accessing multiple kernels during runtime; the first service is any service to be run in the MCU system;

[0031] A configuration unit is used to configure the target memory for storing each target data segment in global memory and multiple local memories based on access information of at least one target data segment.

[0032] Thirdly, this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program or instructions, and when the computer program or instructions are executed by the processor, they implement the method provided in the first aspect above.

[0033] Fourthly, this application also provides a storage medium storing a computer program or instructions that, when executed by a processor, implement the method provided in the first aspect above.

[0034] Fifthly, this application also provides a computer program product, which includes a computer program or instructions that, when executed by a processor, implement the method provided in the first aspect.

[0035] It should be noted that the technical effects of the second to fifth aspects can be referred to in the detailed description of the first aspect above, and will not be repeated here. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of an optional structure of a multi-core MCU system provided in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram of a first optional process for configuring distributed memory according to an embodiment of this application;

[0038] Figure 3A schematic diagram of a second optional process for configuring distributed memory provided in an embodiment of this application;

[0039] Figure 4 A schematic diagram of a third optional process for configuring distributed memory provided in an embodiment of this application;

[0040] Figure 5 A schematic diagram of a fourth optional process for configuring distributed memory provided in an embodiment of this application;

[0041] Figure 6 This is a schematic diagram of another optional structure of the multi-core MCU system provided in the embodiments of this application;

[0042] Figure 7 This is a schematic diagram of an optional structure of the performance analysis and processing structure provided in the embodiments of this application;

[0043] Figure 8 This is an optional flowchart illustrating the configuration process of distributed memory provided in an embodiment of this application.

[0044] Figure 9 An optional schematic diagram illustrating the allocation and linking of various object files provided in the embodiments of this application;

[0045] Figure 10 A schematic diagram of an optional RAM allocation process provided in an embodiment of this application;

[0046] Figure 11 A schematic diagram of an optional structure of a distributed memory configuration device provided in an embodiment of this application;

[0047] Figure 12 This is a schematic diagram of an optional structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0049] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0050] In the following description, the terms "first," "second," and "third" are used only to distinguish different objects and do not represent a specific order of objects, nor are they constituting a chronological order. It is understood that "first," "second," and "third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0052] This application provides a method, apparatus, device, storage medium, and program product for configuring distributed memory. It is applied to multi-core MCU systems.

[0053] To facilitate understanding, the multi-core MCU system provided in the embodiments of this application will be described first.

[0054] refer to Figure 1 As shown, the multi-core MCU system 10 includes a global memory 101, multiple local memories 102, and multiple cores 103, with one local memory 102 corresponding to one core 103.

[0055] The embodiments of this application do not limit the number of local memory 102 and kernel 103, and can be configured according to actual needs.

[0056] Kernel 103 refers to the Central Processing Unit (CPU) core.

[0057] Global memory 101 refers to the RAM space that can be accessed by all cores of a multi-core MCU system. It needs to be accessed through the data bus, so the access speed is slightly slower, but the capacity is large.

[0058] Local memory 102 refers to RAM directly connected to a CPU core. This core can access it without crossing a bus, resulting in fast access speed, but its capacity is limited.

[0059] The following describes various embodiments of the distributed memory configuration method, apparatus, device, storage medium, and program product provided in this application. The distributed memory configuration method can be implemented using a distributed memory configuration apparatus, which can be deployed in an electronic device including a memory and a processor.

[0060] In one possible implementation, the electronic device can be deployed in a multi-core MCU system.

[0061] In another possible implementation, a multi-core MCU system can be deployed in an electronic device.

[0062] Firstly, embodiments of this application provide a method for configuring distributed memory, referring to... Figure 2 The content shown, taking an electronic device as the executing entity, may include, but is not limited to, the following S201 and S202.

[0063] S201, The electronic device obtains access information for at least one target data segment.

[0064] The target data segment is the data segment of at least one intermediate file compiled from the first service. The first service is any service to be run in the MCU system.

[0065] Here, one intermediate file corresponds to one data segment, and one or more intermediate files can be obtained after compiling a service.

[0066] This application does not limit the type of intermediate files, and can be configured according to actual needs. For example, the intermediate files here can be .o files.

[0067] The target data segment stores the data of the compiled intermediate files.

[0068] Access information is used to characterize the frequency with which the target data segment accesses multiple kernels during runtime. Frequency refers to the number of accesses per unit of time.

[0069] Access information may include the frequency with which the target data segment accesses each of the multiple kernels during runtime.

[0070] Access information may also include the total frequency of the target data segment accessing all kernels at runtime.

[0071] Access information may also include other information (e.g., the size of the target data segment, the timestamp of the collection, etc.), which will not be listed here.

[0072] In one possible implementation, S201 can be implemented as follows: the electronic device receives access information for each target data segment in at least one target data segment sent by another device.

[0073] In another possible implementation, S201 can be implemented as follows: the electronic device collects data on the first service operation process to obtain access information for each target data segment in a target data segment.

[0074] S202. The electronic device configures target memory for storing each target data segment in global memory and multiple local memories based on access information of at least one target data segment.

[0075] Here, a target data segment has its own target memory segment.

[0076] The electronic device configures a target memory (global memory or a local memory) for each target data segment in global memory and multiple local memory. The specific configuration method is determined based on the access information in the target data segment.

[0077] In this embodiment, based on the above-mentioned methods, a multi-core microcontroller unit (MCU) system is provided. The multi-core MCU system includes global memory, multiple local memories, and multiple kernels. Each local memory corresponds to one kernel. The memory configuration schemes of related technologies are generally used to configure kernels. The scheme of this application is used to allocate memory for the target data segment of at least one intermediate file after the first service is compiled. When configuring memory for the target data segment, the access information of each data segment during runtime is considered to achieve reasonable allocation, improve the running efficiency of the first service, and improve the running effect of the multi-core microcontroller unit (MCU) system.

[0078] The target data segment will be described below.

[0079] In one possible implementation, the target data segment includes: a first data segment, a second data segment, and a third data segment; wherein, the first data segment includes initialized global variables and static variables; the second data segment includes: uninitialized global variables and static variables; and the third data segment includes: local variables and function calls.

[0080] Of course, the target data segment may also include more content, or parts of the first, second, or third data segments mentioned above, which will not be listed here.

[0081] Based on the above methods, the target data segment was further segmented, which enabled reasonable memory allocation for the segmented initialized global and static variables, uninitialized global and static variables, local variables, and function call data, thereby improving the efficiency of data usage.

[0082] The following describes the process by which the electronic device in S202 configures target memory in global memory and multiple local memories to store each target data segment based on access information of at least one target data segment.

[0083] refer to Figure 3 The process may include, but is not limited to, S301 to S303 described below.

[0084] S301. The electronic device determines the total access frequency of each target data segment from the access information of each target data segment.

[0085] Total access frequency is used to characterize the sum of the frequency of the target data segment accessing each of the multiple kernels.

[0086] In one possible implementation, the access information includes the total access frequency, so that the electronic device can directly obtain the total access frequency of each target data segment from the access information.

[0087] In another possible implementation, the access information does not include the total access frequency, but it does include the access frequency of each kernel. In this way, the electronic device can sum the access frequencies of all kernels to obtain the total access frequency of each target data segment.

[0088] S302. The electronic device determines the priority of each target data segment based on the total access frequency of each target data segment.

[0089] The higher the total access frequency, the higher the corresponding priority, and the higher the priority, the faster it is processed.

[0090] In practice, you can configure a corresponding priority for each total access frequency; or you can configure a priority for a range of total access frequencies.

[0091] S303. The electronic device, according to the priority of each target data segment, configures target memory in global memory and multiple local memories to store each target data segment based on the access information of each target data segment.

[0092] Assume there are four target data segments: target data segment 1, target data segment 2, target data segment 3, and target data segment 4. The total access frequency of target data segment 1 is 90, target data segment 2 is 25, target data segment 3 is 54, and target data segment 4 is 1. The priority of target data segment 1, target data segment 3, target data segment 2, and target data segment 4 decreases in that order. The electronic device first allocates target memory to target data segment 1, then to target data segment 3, then to target data segment 2, and finally to target data segment 4.

[0093] In this embodiment, based on the above-mentioned methods, a priority is configured when allocating memory to multiple target data segments. The allocation is performed in order of priority. Since the priority is determined based on the total access frequency of the target data segments, it can be ensured that target data segments with high access frequency are allocated memory first. This can ensure the rationality of memory configuration for frequently used target data segments. For example, when memory is insufficient, the priority-based configuration method can ensure that the use of frequently used target data segments is prioritized, which has a smaller impact on the first service and improves the operating efficiency of the first service.

[0094] The following describes the process by which the electronic device in S202 or S303 configures target memory in global memory and multiple local memories to store each target data segment based on the access information of each target data segment. The process of processing one target data segment will be used as an example; the processing of other target data segments is similar and will not be described in detail here.

[0095] refer to Figure 4 The process may include, but is not limited to, S401 and S402 described below.

[0096] S401. The electronic device determines the analysis result of each target data segment based on the access information of each target data segment.

[0097] The analysis results include at least one of the following: the cold / hot type, nucleophilic type, shared type, and size type of the target data segment.

[0098] The types of analysis results can be configured according to actual needs, and they are not listed here.

[0099] The target data segment is categorized into cold and hot types: cold type and hot type. The cold type is used to indicate that the data is accessed less frequently, while the hot type is used to indicate that the data is accessed frequently, i.e., accessed very often.

[0100] The kernel-friendly type is used to characterize the kernel with the highest single-core access frequency for this target data segment.

[0101] Sharing types include inter-kernel sharing and non-inter-kernel sharing. Inter-kernel sharing indicates that the target data segment can access multiple kernels. Non-inter-kernel sharing indicates that the target data segment accesses only one kernel.

[0102] Size types include large and small types. Large types are used to indicate that the target data segment has a large data volume, while small types are used to indicate that the target data segment has a small data volume.

[0103] S402. Based on the analysis results of each target data segment, the electronic device configures the target memory of the target data segment in global memory and multiple local memories.

[0104] The configuration process is related to the values ​​of the target data segment's hot / cold type, core type, shared type, and size type.

[0105] In this embodiment, based on the above-mentioned methods, factors such as the hot / cold type, core affinity type, shared type, and size type of the target data segment are considered when allocating memory. This makes the memory allocation more in line with actual needs, so as to make the memory configuration more reasonable, and to make the first service run efficiently and the multi-core microcontroller unit (MCU) system run efficiently.

[0106] The following describes the process by which the electronic device in S401 determines the analysis result of each target data segment based on the access information of each target data segment.

[0107] The process may include, but is not limited to, at least one of the following methods 1 to 4.

[0108] Method 1: Determine the total access frequency of the target data segment from the access information of the target data segment; if the access frequency is greater than or equal to the first threshold, the hot / cold type is determined to be hot; if the total access frequency is less than the first threshold, the hot / cold type is determined to be cold.

[0109] The embodiments of this application do not limit the value of the first threshold, and can be configured according to actual needs. For example, the first threshold can be an empirical value or the average of the total access frequency of all target data segments.

[0110] Method 2: Determine the single-core access frequency of the target data segment from the access information, and identify the kernel with the highest single-core access frequency as the core-friendly type.

[0111] If there are two largest kernels, then the parent kernel type of the target data segment is determined to be one or both of those kernels.

[0112] Method 3: In the access information of the target data segment, determine the single-core access frequency of the target data segment. If there are multiple single-core access frequencies with non-zero values, then determine the sharing type as inter-core sharing; if there is only one single-core access frequency with a non-zero value, then determine the sharing type as non-inter-core sharing.

[0113] In other words, if a target data segment accesses only one kernel, then the sharing type of the target data segment is determined to be non-inter-kernel sharing; if a target data segment accesses multiple kernels, then the sharing type of the target data segment is determined to be inter-kernel sharing.

[0114] Method 4: Determine the size of the target data segment from the access information of the target data segment; if the data size is greater than or equal to the second threshold, determine the size type as large block; if the data size is less than the second threshold, determine the size type as small block.

[0115] The embodiments of this application do not limit the size of the second threshold, which can be determined according to actual needs. The second threshold here can be a fixed empirical value or an adjustable value.

[0116] In this embodiment, based on the aforementioned methods, the process of determining the analysis results (hot / cold type, nucleophilic type, shared type, and size type) of each target data segment based on its access information is described. It can be seen that this implementation process is convenient, reliable, and flexible in its selection.

[0117] The following describes the process by which the electronic device in S402 configures the target memory of the target data segment in the global memory and multiple local memories based on the analysis results of each target data segment.

[0118] This process may include, but is not limited to, implementations 1 through 6 described below.

[0119] 1. How to determine the target memory for the target data segment when the analysis results include hot and cold types.

[0120] Implementation 2: How to determine the target memory of the target data segment when the analysis results include nucleophilic types.

[0121] 3. When the analysis results include shared types, how to determine the target memory of the target data segment.

[0122] 4. How to determine the target memory for the target data segment when the analysis results include size and type.

[0123] 5. How to determine the target memory for the target data segment when the analysis results include both hot / cold and nucleophilic types.

[0124] 6. Given that the analysis results include hot / cold type, nucleophilic type, shared type, and size type, how to determine the target memory of the target data segment.

[0125] The following explains how to determine the target memory of the target data segment when the analysis results include hot and cold types in Implementation 1.

[0126] If the target data segment is a hot type, in order to facilitate efficient access to the target data segment, the target memory of the target data segment is determined to be a local memory (the specific local memory can be determined in conjunction with the core type, or it can be randomly determined directly). If the target data segment is a cold type, in order to save storage space, the target type of the target data segment is determined to be global memory.

[0127] The following explains how to determine the target memory of the target data segment in Implementation 2 when the analysis results include the nucleus type.

[0128] The target memory of the target data segment is determined to be the local memory corresponding to the kernel pointed to by the parent kernel type.

[0129] This nucleophilic type can generally be used in combination with other types to select a local memory as the target memory from multiple local memory locations.

[0130] The following explains how to determine the target memory of the target data segment when the analysis results include shared types in implementation 3.

[0131] If the sharing type of the analysis results is inter-core sharing, then the target memory is determined to be global memory; if the sharing type of the analysis results is not inter-core sharing, then the target memory is determined to be one of multiple local memory locations.

[0132] The specific implementation of a local memory that is one of multiple local memory locations can be determined in conjunction with the kernel type, or a local memory location can be randomly determined.

[0133] Based on the above methods, for shared target data segments, since these segments typically access multiple kernels, allocating them to global RAM facilitates interaction between kernels, optimizes memory usage efficiency, and reduces unnecessary data copying and synchronization. For non-shared target data segments, they can be allocated to a single local memory location within multiple local memory locations. It can be seen that this allocation is reasonable and efficient.

[0134] The following explains how to determine the target memory of the target data segment when the analysis results include size and type, as described in implementation 4.

[0135] If the size type of the analysis result is large, then the target memory is determined to be global memory; if the size type of the analysis result is small, then the target memory is determined to be one of multiple local memory locations.

[0136] Based on the above methods, large target data segments, due to their large memory footprint and the large global memory capacity, can be configured in global memory. Small target data segments, due to their small memory footprint, can be configured in one of multiple local memory locations. It can be seen that the allocation is reasonable and efficient.

[0137] The following explains how to determine the target memory of the target data segment when the analysis results include both hot and cold types and nucleophilic types in implementation 5.

[0138] If the analysis result indicates a hot type, the target memory is determined to be the local memory corresponding to the kernel pointed to by the nucleus type among multiple local memory locations; if the analysis result indicates a cold type, the target memory is determined to be global memory.

[0139] Based on the above methods, for hot target data segments, due to their high access frequency, they are configured in layout memory. Since local memory is directly connected to the kernel, the data response rate is improved in the time dimension. Specifically, they can be configured in the local memory corresponding to the kernel with the highest access frequency of the target data segment to ensure the speed of most accesses. For cold target data segments, due to their low access frequency, they are configured in global memory to reduce the occupation of local memory and improve memory utilization efficiency in the space dimension.

[0140] The following explains how to determine the target memory of the target data segment when the analysis results include hot / cold type, nucleophilic type, shared type, and size type in implementation 6.

[0141] If the dataset includes hot / cold type, core-friendly type, shared type, and size type, then multiple target memory locations are determined for each type. These target memory locations are then merged. If there are no contradictions during merging, then both conditions are satisfied simultaneously. If there are contradictions during merging, the target memory is determined according to the priority of each type. The priority order from highest to lowest is: hot / cold type, core-friendly type, shared type, and size type.

[0142] It should be noted that various combinations of the above four types can be used to determine the target memory. For specific implementation details, please refer to the description in Implementation 6. That is, if the results are consistent, the target memory is determined based on the results of multiple types; if the results are contradictory, the target memory is determined according to the priority of each type. The priority order from highest to lowest is: hot / cold type, core-friendly type, shared type, and size type.

[0143] The process of the electronic device in S201 obtaining access information for each target data segment in at least one target data segment will be described below.

[0144] refer to Figure 5 The process may include, but is not limited to, S501 and S502 described below.

[0145] S501, the electronic device runs the first service in the multi-core MCU system.

[0146] Electronic devices compile and run the first service in a multi-core MCU system so that the intermediate files in the first service can access multiple kernels according to the original rules.

[0147] S502. The electronic device collects the frequency of each target data segment accessing multiple kernels during the operation of at least one target data segment in the first time period, and obtains access information of at least one target data segment.

[0148] The duration of the first time period can be configured according to actual needs and is not limited here.

[0149] Electronic devices collect data on each data segment's access to each kernel (access time, access count, etc.) to obtain access information for each target data segment.

[0150] Based on the above methods, the access information of each target data segment is actually collected during the operation of the first service, which has the characteristics of high accuracy and high reliability.

[0151] The following example illustrates the configuration process of distributed memory provided in this application.

[0152] This embodiment belongs to embedded system memory management technology, and involves a method for statically allocating resources of random access memory (RAM) (equivalent to the memory mentioned above) in a multi-core microcontroller unit (MCU).

[0153] With the development of multi-core microcontroller technology, the architecture of RAM has also undergone significant changes, evolving from centralized RAM to distributed RAM architecture. Distributed RAM architecture consists of local RAM corresponding to the central processing unit (CPU) core and global RAM shared by multiple cores (hereinafter referred to as local RAM and global RAM).

[0154] refer to Figure 6 The multi-core MCU system shown includes: Global RAM 1 (601), Global RAM 2 (602), Core 0 (COR0) (603), Core 1 (COR1) (604), Core 2 (COR2) (605), Core 3 (COR3) (606), Local RAM 0 (607), Local RAM 1 (608), Local RAM 2 (609), Local RAM 3 (610), and Data Bus (611).

[0155] The CPU has the following characteristics when accessing the two types of RAM: When the CPU core accesses local RAM, it does not go through the system bus, resulting in very high speed, but the capacity of local RAM is generally small. When the CPU accesses global RAM, it needs to go through the bus, resulting in slightly slower speed, but global RAM space is generally larger. Therefore, effectively managing the allocation of local RAM and global RAM resources becomes particularly important.

[0156] Currently, memory segment allocation methods, whether implemented by compilers or manually, often fail to fully utilize the speed advantage of local RAM or effectively address the access latency of global RAM, thus impacting the overall system performance.

[0157] For example, related technical solutions include: obtaining multiple memory segments corresponding to the task to be processed, determining the multiple running cores contained in the running platform executing the task; and determining the first and second capacity memory segments among the multiple memory segments based on the multiple running cores. This method does not solve the problem of low access efficiency when accessing memory data across cores.

[0158] In contrast, the method proposed in this embodiment can solve the memory allocation problem in multi-core systems and distributed memory architectures. It optimizes the linker script's linking operations on data segments by modifying the link addresses of data segments, stack, and BSS segments in the code, based on performance analysis results from actual runtime on the target platform. This improves the memory access efficiency of multi-core programs during runtime.

[0159] The address space that needs to be allocated for the data segment during the code compilation stage. The data segment is divided into the data segment, the stack segment, and the bss segment. Here, the data segment, the stack segment, and the bss segment are collectively referred to as the data segment.

[0160] RAM segment: Divide the physical RAM space into several segments to store the data segment, stack, and bss segment.

[0161] This embodiment provides a RAM segment allocation method based on performance analysis in a multi-core MCU system, which aims to optimize memory resource allocation during the code linking stage. By optimizing the data segment allocation of locally bound RAM (equivalent to the local memory corresponding to the kernel mentioned above) and global RAM, the system's operating efficiency and response speed can be improved.

[0162] 1. Performance Analysis:

[0163] refer to Figure 7 The performance analysis and processing structure shown includes: MCU target board 701, data recording module 702, performance analysis module 703, and development and compilation environment 704.

[0164] In a typical application scenario running on a multi-core MCU system, the MCU target board is connected to the data logging module. The data logging module is then activated to collect memory access data over a period of time and save it as a log file. The log file contains information primarily including the frequency of access to a particular data item, the specific core that accessed these data items, and the timestamp information of the access.

[0165] The performance analysis module is used to analyze the collected recorded data. The performance analysis outputs two metrics: the frequency of a specific data point being accessed by a single core (A_avg); and the total number of times a specific data point is accessed across all cores (A_all).

[0166] 2. Data classification.

[0167] refer to Figure 8 The configuration process for distributed memory, as shown, may include:

[0168] S801, code compilation;

[0169] S802, Generate intermediate .o files;

[0170] S803, link into a hex file;

[0171] S804, running on the target platform;

[0172] S805. Perform performance analysis using performance analysis tools;

[0173] S806. Output the analysis results file;

[0174] S807. Classify data segments according to the performance analysis results file;

[0175] S808, Classified according to hot data and cold data;

[0176] S809. Allocate data segments to RAM segments according to their priority based on popularity.

[0177] S810, Modify the linking script.

[0178] Based on the performance analysis results, the data segments are classified as follows:

[0179] Data Priority: Sort the data in descending order based on access frequency A_all. The sorting result is used to determine the allocation order of data segments; the higher the data's popularity, the higher its allocation priority, and vice versa. The purpose is to ensure that highly popular data receives priority allocation.

[0180] Data hot / cold classification: Based on the data frequency A_all, a median access frequency is selected as a threshold point A_thod. This threshold A_thod is then used to classify A_all in the performance analysis results. Data above this threshold is classified as hot data, and data below it is classified as cold data.

[0181] Based on the core affinity of the data: the core affinity of the data is classified, and a histogram of core-data segment access frequency is drawn. The horizontal axis is the core identifier (coreID) of the core, and the vertical axis is the access frequency of each core to the data segment. The data is sorted according to the frequency and the core with the highest access frequency to the data segment is found to determine the core affinity of the data. The purpose is to ensure that core affinity data is allocated to the local RAM bound to the core as much as possible.

[0182] 3. Memory allocation:

[0183] RAM Segment Planning: Based on the MCU's physical memory structure, the starting address and size of the local RAM and global RAM bound to each core are planned, referred to as memory segments. In this embodiment, the local RAM bound to each core is divided into 3 segments, and the global RAM is divided into 3 segments. The specific segmentation rules can be modified according to the actual scenario.

[0184] Data segment division: The intermediate result src.o file after code compilation is divided into several data segments according to each file, namely code segment (code, text, string constants), data segment (initialized global variables, static variables), bss segment (uninitialized global variables, static variables), and stack segment (local variables, function calls).

[0185] Data allocation: A code project consists of many files. During the compilation phase, each file is compiled into an independent intermediate file with a .o extension. This intermediate file mainly contains the address and size allocation of variables and symbols in the code segment, data segment, BSS segment, stack, and heap. The purpose of this method is to record memory access data and perform performance analysis based on a runnable initial version of the program, in order to optimize the linking and allocation of the code's data segment content in the RAM segment.

[0186] When linking compiled data, the following metrics need to be considered: hot / cold data type, data affinity, whether it is shared data, and whether it is a large data block.

[0187] Based on the above metrics, the RAM segment to which each data segment in the target file should be allocated is determined. The specific allocation details are as follows: Based on the overall popularity of the data, RAM segments are allocated from high to low priority, using the following method:

[0188] Hot data is allocated to local RAM: Based on the data's affinity to the core, priority is given to allocating hot data (such as local variables of core functions and frequently used global variables) to the local RAM bound to that core. For example:

[0189] Step 1: Assume there are 5 global data instances (equivalent to the target data segment instances mentioned above): InstanceA, InstanceB, InstanceC, InstanceD, and InstanceE, and their memory layout. First, following the performance analysis steps above, obtain the analysis results and find the overall access frequency (Facc) of each data instance (InstanceA, InstanceB, InstanceC, InstanceD, and InstanceE) per unit time, as well as the frequency (Fcorex) of a specific data instance accessed by a single core. Based on the data hotness threshold calculation method, the median of the total data access frequencies is used as the threshold; data above or equal to the threshold is considered hot data.

[0190] As shown in Table 1, the frequency of Instance A and Instance B is greater than or equal to the threshold. Therefore, Instance A and Instance B are called hot data, and other instance data (Instance C, Instance D, Instance E) are called cold data.

[0191] Table 1 Statistical Results of Data Examples

[0192]

[0193] Step 2: Based on the performance analysis results, calculate the access frequency of data instances InstanceA, InstanceB, InstanceC, InstanceD, and InstanceE on each core. The core with the highest access frequency is selected as the parent core of the data instance. The data instance allocation results can be found in Table 2.

[0194] Table 2 shows the data allocation results.

[0195]

[0196] Step 3: Determine whether the data instance needs to be bound to a kernel based on a comprehensive assessment of the data's popularity and nucleophilicity.

[0197] For example, if InstanceA and InstanceB are classified as hot data, exhibit core affinity, and are neither inter-core shared data nor large data blocks, then based on the aforementioned four sub-indicators, data instances InstanceA and InstanceB are allocated to their respective core's RAM segment. This minimizes access latency and bus load, improving memory access efficiency over time.

[0198] The allocation and linking of each target file can be found in [reference]. Figure 9 The content shown includes target files src1.o901, src2.o902, and src3.o903. Target file src1.o901 includes code segment 1, data segment 1 (hot data, core1 core-friendly), bss segment 1 (hot data, core1 core-friendly), and stack1 (hot data, core1 core-friendly); target file src2.o902 includes code segment 2, data segment 2 (cold data, non-core-friendly data), bss segment 2 (cold data, non-core-friendly data), and stack2 (cold data, non-core-friendly data); target file src3.o903 includes code segment 3, data segment 3 (large data block), bss segment 3 (shared data block), and stack3 (large data block).

[0199] The target file src1.o901 is linked to the local RAM 904 of core1, the target file src2.o902 is linked to the global RAM 905, and the target file src3.o903 is linked to the global RAM 905.

[0200] refer to Figure 9 As shown, the data segments in the src1.o object file are classified as hot data and are core1 native data, so they are allocated to the local RAM of Core1.

[0201] Cold data is allocated to global RAM: Infrequently accessed (cold) data is allocated to global RAM. For example, instance E is typical cold data and is allocated to a global RAM segment. This reduces local RAM usage and improves memory utilization efficiency in terms of space.

[0202] refer to Figure 9 As shown, the data segments in the src2.o object file are classified as cold data and are non-nucleus-friendly data, so they are allocated to global RAM.

[0203] Shared data is allocated to global RAM: Allocating data that needs to be shared across cores to global RAM helps optimize memory usage efficiency and reduces unnecessary data copying and synchronization. For example, InstanceC is a typical example of inter-core shared data used for cross-core communication, and this data is allocated in the global RAM segment.

[0204] refer to Figure 9 As shown, the BSS segment in the src3.o object file is shared data and is accessed by multiple cores, so it is allocated to global RAM.

[0205] Large data allocation: For large blocks of memory data in a data segment, it is necessary to balance the data's frequency of use and its locality. Priority should be given to ensuring that the entire data segment can be placed in the kernel-bound local RAM. If the local RAM space is insufficient, it should be placed in global RAM. For example, the data instance InstanceD is a typical large block of data and is allocated in the global RAM segment, which can save limited local RAM space.

[0206] refer to Figure 9 As shown, the data and stack segments in the src3.o object file are shared data, accessed by multiple cores, and therefore allocated to global RAM.

[0207] The RAM allocation process can be found in [reference]. Figure 10 The contents shown include, but are not limited to, S1001 to S1010 below.

[0208] S1001, Performance Analysis;

[0209] S1002, Data Classification;

[0210] S1003, Data allocation priority sorting;

[0211] S1004, Data affinity sorting;

[0212] S1005. Allocate RAM according to data priority;

[0213] S1006. Determine whether the data is nucleophilic;

[0214] If yes, proceed to S1008 below; if no, proceed to S1007 below.

[0215] S1007, move to global RAM;

[0216] S1008. Determine if the local RAM can accommodate the data.

[0217] If yes, proceed to S1009 below; if no, proceed to S1010 below.

[0218] S1009, Place in local RAM;

[0219] S1010, put it into global RAM.

[0220] 4. Performance Evaluation: Repeat the above rules until all data segments in the target file have been allocated. Obtain a new linker file, and then recompile and link an executable program based on the new linker file. Run the new executable code on the target board, and then perform data logging and performance analysis again to evaluate the effectiveness of this RAM allocation.

[0221] Secondly, embodiments of this application provide a distributed memory configuration device, which is deployed in a multi-core microcontroller unit (MCU) system. The multi-core MCU system includes global memory, multiple local memories, and multiple cores, with one local memory corresponding to one core. (See reference...) Figure 11 As shown, the distributed memory configuration device 110 includes an acquisition unit 1101 and a configuration unit 1102.

[0222] The acquisition unit 1101 is used to acquire access information of at least one target data segment; the target data segment is the data segment of at least one intermediate file after the first service is compiled; the access information is used to characterize the frequency of the target data segment accessing multiple kernels during runtime; the first service is any service to be run in the MCU system;

[0223] Configuration unit 1102 is used to configure target memory for storing each target data segment in global memory and multiple local memories based on access information of at least one target data segment.

[0224] In some embodiments, the configuration unit 1102 is further configured to: determine the total access frequency of each target data segment in the access information of each target data segment; the total access frequency is used to characterize the sum of the frequencies of the target data segment accessing each of the multiple kernels; determine the priority of each target data segment based on the total access frequency of each target data segment; and configure target memory for storing each target data segment in global memory and multiple local memories in accordance with the priority of each target data segment and based on the access information of each target data segment.

[0225] In some embodiments, the configuration unit 1102 is further configured to: determine the analysis result of each target data segment based on the access information of each target data segment; configure the target memory of the target data segment in global memory and multiple local memory based on the analysis result of each target data segment; the analysis result includes at least one of the following: the cold / hot type, nucleus-friendly type, shared type, and size type of the target data segment.

[0226] In some embodiments, the configuration unit 1102 is further configured to: determine the total access frequency of the target data segment in the access information of the target data segment; if the access frequency is greater than or equal to a first threshold, determine the hot / cold type as hot; if the total access frequency is less than the first threshold, determine the hot / cold type as cold; and / or, determine the single-core access frequency of the target data segment in the access information of the target data segment, and determine the kernel with the highest single-core access frequency as the core-friendly type; and / or, determine the single-core access frequency of the target data segment in the access information of the target data segment, if there are multiple single-core access frequencies with non-zero values, determine the sharing type as inter-core sharing; if there is only one single-core access frequency with a non-zero value, determine the sharing type as non-inter-core sharing; and / or, determine the data size of the target data segment in the access information of the target data segment; if the data size is greater than or equal to a second threshold, determine the size type as large block; if the data size is less than the second threshold, determine the size type as small block.

[0227] In some embodiments, when the analysis results include hot / cold type and nucleophilic type, the configuration unit 1102 is further configured to: if the hot type of the analysis result is hot, then determine the target memory as the local memory corresponding to the kernel pointed to by the nucleophilic type among a plurality of local memories; if the hot / cold type of the analysis result is cold, then determine the target memory as global memory.

[0228] In some embodiments, when the analysis result includes a sharing type, the configuration unit 1102 is further configured to: if the sharing type of the analysis result is inter-core sharing, then determine the target memory as global memory; if the sharing type of the analysis result is non-inter-core sharing, then determine the target memory as a local memory among multiple local memories.

[0229] In some embodiments, when the analysis result includes a size type, the configuration unit 1102 is further configured to: if the size type of the analysis result is large block, then determine the target memory as global memory; if the size type of the analysis result is small block, then determine the target memory as one of a plurality of local memories.

[0230] In some embodiments, the acquisition unit 1101 is further configured to: run a first service in a multi-core MCU system; collect the frequency of each target data segment accessing multiple cores during the operation of at least one target data segment in a first time period, and obtain access information of at least one target data segment.

[0231] In some embodiments, the target data segment includes: a first data segment, a second data segment, and a third data segment; wherein, the first data segment includes initialized global variables and static variables; the second data segment includes: uninitialized global variables and static variables; and the third data segment includes: local variables and function calls.

[0232] Thirdly, an embodiment provides an electronic device, which includes a memory and a processor. The memory stores a computer program or instructions, and when the computer program or instructions are executed by the processor, the method provided in the first aspect is implemented.

[0233] In one example, reference Figure 12 As shown, the electronic device 120 includes: a processor 1201, at least one communication bus 1202, a user interface 1203, at least one external communication interface 1204, and a memory 1205. The communication bus 1202 is configured to enable communication between these components. The user interface 1203 may include features for receiving user input, and the external communication interface 1204 may include standard wired and wireless interfaces.

[0234] The memory 1205 is configured to store instructions and applications executable by the processor 1201, and can also cache data to be processed or already processed by the processor 1201 and various modules in the electronic device (e.g., image data, audio data, voice communication data and video communication data), which can be implemented by flash memory or random access memory (RAM).

[0235] Fourthly, the embodiments provide a storage medium, namely a computer-readable storage medium, on which a computer program or instructions are stored, which, when executed by a processor, implement the method provided in the first aspect above.

[0236] Fifthly, an embodiment provides a computer program product, which includes a computer program or instructions that, when executed by a processor, implement the method provided in the first aspect.

[0237] It should be noted that the descriptions of the above embodiments of storage media, devices, apparatuses, and program products are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of storage media, devices, apparatuses, and program products, please refer to the descriptions of the method embodiments for understanding.

[0238] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment. The above embodiment numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0239] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0240] In the several embodiments provided in this example, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0241] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0242] In addition, in each embodiment, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0243] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0244] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments, or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0245] The above are merely embodiments of [the invention], but the scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the disclosed technology should be included within the scope of protection of [the invention]. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for configuring distributed memory, characterized in that, The method is applied to a multi-core microcontroller unit (MCU) system, wherein the multi-core MCU system includes global memory, multiple local memories, and multiple cores, wherein one local memory corresponds to one core, and the method includes: Obtain access information for at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by the first service; the access information is used to characterize the frequency with which the target data segment accesses the multiple kernels during runtime; the first service is any service to be run in the MCU system; Based on the access information of the at least one target data segment, target memory for storing each target data segment is configured in the global memory and the plurality of local memories; The step of configuring target memory for storing each target data segment in the global memory and the plurality of local memories based on the access information of the at least one target data segment includes: determining the total access frequency of each target data segment in the access information of each target data segment; the total access frequency is used to characterize the sum of the frequencies of the target data segment accessing each of the plurality of kernels; determining the priority of each target data segment based on the total access frequency of each target data segment; and configuring target memory for storing each target data segment in the global memory and the plurality of local memories according to the priority of each target data segment and based on the access information of each target data segment.

2. The method according to claim 1, characterized in that, The step of configuring target memory for storing each target data segment in the global memory and the plurality of local memories based on the access information of the at least one target data segment includes: Based on the access information of each target data segment, determine the analysis result of each target data segment; Based on the analysis results of each of the target data segments, the target memory of the target data segment is configured in the global memory and the plurality of local memory. The analysis results include at least one of the following: the hot / cold type, nucleophilic type, shared type, and size type of the target data segment.

3. The method according to claim 2, characterized in that, The step of determining the analysis result for each target data segment based on the access information of each target data segment includes: The total access frequency of the target data segment is determined from the access information of the target data segment. If the total access frequency is greater than or equal to the first threshold, the hot / cold type is determined to be hot; if the total access frequency is less than the first threshold, the hot / cold type is determined to be cold. And / or, In the access information of the target data segment, the single-core access frequency of the target data segment is determined, and the kernel with the highest single-core access frequency is determined as the nucleus-friendly type; And / or, In the access information of the target data segment, the single-core access frequency of the target data segment is determined. If there are multiple single-core access frequencies with non-zero values, the sharing type is determined to be inter-core sharing; if there is only one single-core access frequency with a non-zero value, the sharing type is determined to be non-inter-core sharing. And / or, In the access information of the target data segment, the data size of the target data segment is determined; if the data size is greater than or equal to a second threshold, the size type is determined to be large; if the data size is less than the second threshold, the size type is determined to be small.

4. The method according to claim 2, characterized in that, When the analysis results include hot / cold type and nucleophilic type, configuring the target memory of the target data segment in the global memory and the plurality of local memories based on the analysis results of each target data segment includes: If the analysis result is of the hot type, then the target memory is determined to be the local memory among the plurality of local memories that corresponds to the kernel pointed to by the nucleophile type; If the analysis result indicates that the hot / cold type is cold, then the target memory is determined to be the global memory.

5. The method according to claim 2, characterized in that, When the analysis results include shared types, configuring the target memory of the target data segment in the global memory and the plurality of local memories based on the analysis results of each target data segment includes: If the sharing type of the analysis results is inter-core sharing, then the target memory is determined to be the global memory; If the sharing type of the analysis result is non-inter-kernel sharing, then the target memory is determined to be one of multiple local memories.

6. The method according to claim 2, characterized in that, When the analysis results include size type, configuring the target memory for the target data segment in the global memory and the plurality of local memory based on the analysis results for each target data segment includes: If the size type of the analysis result is large, then the target memory is determined to be the global memory; If the size type of the analysis result is small block, then the target memory is determined to be one of the multiple local memories.

7. The method according to any one of claims 1 to 6, characterized in that, The acquisition of access information for at least one target data segment includes: The first service runs in the multi-core MCU system; During a first time period, the frequency of each target data segment accessing the multiple kernels in the at least one target data segment during the operation of the first service is collected to obtain the access information of the at least one target data segment.

8. The method according to any one of claims 1 to 6, characterized in that, The target data segment includes: a first data segment, a second data segment, and a third data segment; The first data segment includes initialized global variables and static variables; The second data segment includes: uninitialized global variables and static variables; The third data segment includes local variables and function calls.

9. A distributed memory configuration device, characterized in that, The device is deployed in a multi-core microcontroller unit (MCU) system, which includes global memory, multiple local memories, and multiple cores, with one local memory corresponding to one core. The device includes: An acquisition unit is used to acquire access information of at least one target data segment; the target data segment is a data segment of at least one intermediate file compiled by the first service; the access information is used to characterize the frequency of the target data segment accessing the multiple kernels during runtime; the first service is any service to be run in the MCU system; A configuration unit is configured, based on the access information of the at least one target data segment, to configure target memory for storing each target data segment in the global memory and the plurality of local memories; The configuration unit is further configured to determine the total access frequency of each target data segment from the access information of each target data segment; the total access frequency is used to characterize the sum of the frequencies at which the target data segment accesses each of the plurality of kernels; determine the priority of each target data segment based on the total access frequency of each target data segment; and configure target memory for storing each target data segment in the global memory and the plurality of local memories according to the priority of each target data segment and based on the access information of each target data segment.

10. An electronic device, characterized in that, The electronic device includes a memory and a processor. The memory stores a computer program or instructions. When the processor executes the computer program or instructions, it implements the method described in any one of claims 1-8.

11. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, and when the processor executes the computer program or instructions, it implements the method described in any one of claims 1-8.

12. A computer program product, characterized in that, The computer program product includes a computer program or instructions, and when the processor executes the computer program or instructions, it implements the method described in any one of claims 1-8.

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