Address space fast switching method of ARM platform based on domain space management

Abstract

The invention discloses a domain space management-based address space rapid switching method for an ARM platform. The method comprises the following steps of: defining a group of page base address management structures; when domain switching is needed during operation of an operating system, if a target domain number to be switched in is equal to the ASID value in the TTBR0 register, domain switching operation does not need to be executed; and if the target domain number to be cut in is not equal to the ASID value in the TTBR0 register, obtaining a page table base address of the corresponding domain from the page base address management structure according to the target domain number, and writing the domain number and the page table base address into the TTBR0 register according to a format to complete domain cutting operation. Under the condition that the original page table structure is not changed, domain switching does not need invalid TLB table items, the performance loss caused by TLB miss and Cache miss is reduced, and the overall performance of a system is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of computer architecture, and in particular relates to an address space fast switching method based on domain space management of an ARM platform. Background Art

[0002] Integrated and modular avionics systems (IMA) integrate multiple application systems into computers with high-speed processing capabilities. Partition operating systems are the main embedded real-time operating systems used by IMA. In order to ensure determinism and robustness, the partitions in the partition operating system are isolated from each other in space. This spatial isolation is ensured by the different page tables corresponding to each partition. When scheduling partitions, the partition operating system needs to switch to the page table corresponding to the target partition at the same time. The traditional implementation method only writes the corresponding page table base address into the page table base address register. After the domain is cut, all TLB table entries must be invalidated to ensure correct page search. This method is used when the new partition faces a blank TLB, and there will be serious TLB misses and cache misses at the beginning of execution, resulting in reduced operation or execution performance of the embedded operating system. Summary of the invention

[0003] In view of this, the address space fast switching method based on domain space management of the ARM platform of the present invention solves the technical problem that the existing technical method causes the operation or execution performance of the embedded operating system to be low.

[0004] An address space fast switching method based on domain space management on an ARM platform is used for switching between partition address spaces of an onboard embedded operating system. The embedded operating system includes a storage management function module, and the storage management function is completed by operating the register of the CPU processor. The embedded operating system sets multiple domains for the storage space, and each domain corresponds to a base address and domain number of a page table space. The method includes the following steps:

[0005] S1: specifying a set of page table base address management structures in the embedded operating system, wherein the page table base address management structure is used to store all the base addresses and includes a plurality of storage items, each of which stores a page table base address;

[0006] S2: when the storage management function module is initialized, a page table structure of the system domain of the embedded operating system is constructed, the base address of the page table structure is stored in the first storage item of the page table base address management structure, and the system domain number of the system domain and the corresponding page table base address are written into the TTBR0 register of the CPU processor in a format;

[0007] S3: When the embedded operating system creates a new partition in a human-computer interactive manner, a domain number is allocated to the new partition and a page table structure corresponding to the new partition is constructed, and a base address of the page table structure corresponding to the new partition is stored in a storage item specified in the page table base address management structure;

[0008] S4: There are multiple spatial isolation partitions in the embedded operating system. All the spatial isolation partitions are switched through a time slice rotation algorithm. Each time the partition is switched, the domain is switched to achieve switching from the current domain to the target domain.

[0009] Determine whether the domain number of the target domain is equal to the AS ID value in the TTBR0 register. If so, there is no need to perform a domain cut operation from the current domain to the target domain. If not, obtain the page table base address of the target domain from the specified storage item according to the domain number of the target domain, and write the obtained page table base address of the target domain and the domain number of the target domain into the TTBR0 register in a preset format to complete the domain cut operation.

[0010] The technical beneficial effects of the present invention are:

[0011] Without changing the original page table structure, there is no need to invalidate TLB entries when switching domains, which reduces TLB misses and cache misses and improves the overall performance of the system. Compared with the current leading domain switching method in the aviation field, the present invention obtains the page table base address of the target domain and the domain number of the target domain in a preset format and writes them into the TTBR0 register, without invalidating all TLB entries, which can greatly improve the execution or running performance of the embedded operating system. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 This is a schematic diagram of the format of the page table base address register TTBR0;

[0014] Figure 2 It is a flowchart of the method for fast switching of address space. DETAILED DESCRIPTION

[0015] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0016] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0017] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0018] like Figure 1 to Figure 2 The ARM platform shown in the figure is based on the domain space management address space fast switching method, which is used for the onboard embedded operating system to switch between the partition address spaces. The embedded operating system includes a storage management function module, which completes the storage management function by operating the relevant registers of the CPU processor. The embedded operating system sets multiple domains for the storage space, and each domain corresponds to the base address and domain number of a page table space. Generally, the domain includes multiple types, such as system domain and sub-region, etc. The method includes the following steps:

[0019] S1: specifying a set of page table base address management structures in the embedded operating system, the page table base address management structure is used to store all base addresses and includes multiple storage items, each storage item stores a page table base address;

[0020] S2: When the storage management function module is initialized, the page table structure of the system domain of the embedded operating system is constructed, the base address of the page table structure is stored in the first storage item of the page table base address management structure, and the system domain number of the system domain and the corresponding page table base address are written into the TTBR0 register of the CPU processor in a format;

[0021] S3: When the embedded operating system creates a new partition, it allocates a domain number to the new partition and constructs a page table structure corresponding to the new partition, and stores the base address of the page table structure corresponding to the new partition in a storage item specified in the page table base address management structure, wherein the storage item specified as a preset allocation or identification is used to store the base address of the page table structure corresponding to the new partition;

[0022] S4: There are multiple spatially isolated partitions in the embedded operating system. All spatially isolated partitions are switched through a time slice rotation algorithm. Each time a partition is switched, the domain is switched at the same time to achieve switching from the current domain to the target domain. It is determined whether the domain number of the target domain is equal to the AS ID value in the TTBR0 register. If so, there is no need to perform a domain switching operation from the current domain to the target domain. If not, the page table base address of the target domain is obtained from the specified storage item according to the domain number of the target domain, and the page table base address of the target domain and the domain number of the target domain are written into the TTBR0 register in a preset format to complete the domain switching operation.

[0023] The present invention does not change the original page table structure, so that there is no need to invalidate TLB entries when switching domains, reduces TLB misses and cache misses, and improves the overall performance of the system. Compared with the current leading domain switching method in the aviation field, the present invention obtains the page table base address of the target domain and the domain number of the target domain in a preset format and writes them into the TTBR0 register, without invalidating all TLB entries, which can greatly improve the execution or operation performance of the embedded operating system.

[0024] 2. According to the ARM platform domain space management-based address space fast switching method of claim 1, it is characterized in that the domain number corresponds to the partition number of the partition in the embedded operating system.

[0025] 3. According to the ARM platform domain space management based address space fast switching method of claim 1, it is characterized in that the maximum number of page table base address management structure storage items is equal to the maximum value of the AS ID domain in the TTBR0 register, that is, the maximum number of partitions that can be supported in the embedded operating system does not exceed the maximum number of page table base address management structure storage items.

[0026] 4. According to the address space fast switching method based on domain space management of the ARM platform of claim 1, it is characterized in that the page table structure of the system domain of the embedded operating system is in the long descriptor page table format under the 32-bit execution state.

[0027] 5. The method for fast address space switching based on domain space management of the ARM platform according to claim 1, characterized in that the domain includes a system domain and a sub-region.

[0028] For example, Figure 1The following is a schematic diagram of the format of the page table base address register TTBR0. Bit [47:0] of this register is used to store the page table base address; Bit [55:48] is used to store the domain number, which supports a maximum of 256 domain numbers; Bit [63:56] is reserved, as follows:

[0029] 1. Define a global array with 256 elements (denoted as mmuContext

[256] ) as the page base address management structure. Each array element can store a page table base address.

[0030] 2. When the storage management function module is initialized, the EAE bit of the page table control register TTBCR is set to 1, and the A1 bit of the page table control register TTBCR is set to 0, so that the processor supports the long descriptor page table format under 32 bits, and TTBR0 supports the setting of the ASID field. After the setting is completed, the page table space is constructed for the core domain, and the base address of the constructed page space (recorded as addr0) is stored in the first storage item (mmuContext[0]) of the page base address management structure, and the core domain number 0 is written to the AS ID field of the TTBR0 register, and the core page table base address addr0 is written to the BADDR field of the TTBR0 register, and the memory barrier instruction is used to ensure that subsequent memory access operations are all after the TTBR0 register is updated.

[0031] 3. The operating system creates partition 1, builds a page table space for partition 1, and stores the page space base address (recorded as addr1) after the construction into the storage item (mmuContext[1]) corresponding to domain 1 in the page base address management structure;

[0032] 4. The operating system creates partition 2, builds a page table space for partition 2, and stores the page space base address (recorded as addr2) after the construction into the storage item (mmuContext[2]) corresponding to domain 2 in the page base address management structure;

[0033] 5. The operating system starts partition 1 and partition 2 and starts partition scheduling. There are several situations in the scheduling process:

[0034] The system is currently in the core running state. When the system scheduling process needs to switch from the core domain address space to the core domain address space, there is no need to perform the address space switching operation;

[0035] The system is currently in the core running state. When the system scheduling process needs to switch from the core domain address space to the partition 1 address space, the AS ID value in the TTBR0 register is 0, and a domain switching operation is required. The page table base address add1 of partition 1 is obtained from the page base address management structure and its value is written to the BADDR field of the TTBR0 register. The partition area number value 1 is written to the BADDR field of the TTBR0 register to complete the switch from the core domain address space to the partition 1 address space.

[0036] The system is currently in the core running state. When the system scheduling process needs to switch from the core domain address space to the partition 2 address space, the AS ID value in the TTBR0 register is 0, and a domain switching operation is required. The page table base address add2 of partition 2 is obtained from the page base address management structure and its value is written to the BADDR field of the TTBR0 register. The partition area number value 2 is written to the BADDR field of the TTBR0 register to complete the switch from the core domain address space to the partition 2 address space.

[0037] The system is currently in the partition 1 running state. When the system scheduling process needs to switch from the partition 1 address space to the core domain address space, the AS ID value in the TTBR0 register is 1, and a domain switching operation is required. The core page table base address add0 is obtained from the page base address management structure and its value is written to the BADDR field of the TTBR0 register. The core domain number value 0 is written to the BADDR field of the TTBR0 register to complete the switch from the partition 1 address space to the core domain address space.

[0038] The system is currently in the partition 1 running state. When the system scheduling process needs to switch from the partition 1 address space to the partition 1 address space, there is no need to perform the address space switching operation;

[0039] The system is currently in the partition 1 running state. When the system scheduling process needs to switch from the partition 1 address space to the partition 2 address space, the AS ID value in the TTBR0 register is 1, and a domain switching operation is required. The page table base address add2 of partition 2 is obtained from the page base address management structure and its value is written to the BADDR field of the TTBR0 register. The partition area number value 2 is written to the BADDR field of the TTBR0 register to complete the switch from the partition 1 address space to the partition 2 address space.

[0040] The system is currently in the partition 2 running state. When the system scheduling process needs to switch from the partition 2 address space to the core domain address space, the AS ID value in the TTBR0 register is 2, and a domain switching operation is required. The core page table base address add0 is obtained from the page base address management structure and its value is written to the BADDR field of the TTBR0 register. The core domain number value 0 is written to the BADDR field of the TTBR0 register to complete the switch from the partition 2 address space to the core domain address space.

[0041] The system is currently in the partition 2 running state. When the system scheduling process needs to switch from the partition 2 address space to the partition 1 address space, the AS ID value in the TTBR0 register is 2, and a domain switching operation is required. The page table base address add1 of partition 1 is obtained from the page base address management structure and its value is written to the BADDR field of the TTBR0 register. The partition area number value 1 is written to the BADDR field of the TTBR0 register to complete the switch from the partition 2 address space to the partition 1 address space.

[0042] The system is currently in the partition 2 running state. When the system scheduling process needs to switch from the partition 2 address space to the partition 2 address space, there is no need to perform the address space switching operation.

[0043] Compared with the prior art, the above technical solution adopted by the present invention can achieve at least the following beneficial effects: utilizing the fast address space switching technology, without changing the original page table structure, so that no invalid TLB table entries are required when switching domains, reducing TLB misses and cache misses, and improving the overall performance of the system;

[0044] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for fast address space switching based on domain space management on an ARM platform, which is used for switching between partition address spaces of an onboard embedded operating system, wherein the embedded operating system includes a storage management function module, and the storage management function is completed by operating the register of a CPU processor, and is characterized in that: The embedded operating system sets multiple domains for the storage space, and each domain corresponds to the base address and domain number of a page table space, including the following steps: S1: specifying a set of page table base address management structures in the embedded operating system, wherein the page table base address management structure is used to store all the base addresses and includes a plurality of storage items, each of which stores a page table base address; S2: when the storage management function module is initialized, a page table structure of the system domain of the embedded operating system is constructed, the base address of the page table structure is stored in the first storage item of the page table base address management structure, and the system domain number of the system domain and the corresponding page table base address are written into the TTBR0 register of the CPU processor in a format; S3: When the embedded operating system creates a new partition, it allocates a domain number to the new partition and constructs a page table structure corresponding to the new partition, and stores the base address of the page table structure corresponding to the new partition into a storage item specified in the page table base address management structure; S4: There are multiple spatial isolation partitions in the embedded operating system. All the spatial isolation partitions are switched through a time slice rotation algorithm. Each time the partition is switched, the domain is switched to achieve switching from the current domain to the target domain. Determine whether the domain number of the target domain is equal to the ASID value in the TTBR0 register. If so, there is no need to perform a domain cut operation from the current domain to the target domain. If not, obtain the page table base address of the target domain from the specified storage item according to the domain number of the target domain, and write the page table base address of the target domain and the domain number of the target domain into the TTBR0 register in a preset format to complete the domain cut operation.

2. The method for fast address space switching based on domain space management of the ARM platform according to claim 1, characterized in that: The domain numbers correspond one-to-one to the partition numbers of the partitions in the embedded operating system.

3. The method for fast address space switching based on domain space management of the ARM platform according to claim 1, characterized in that: The maximum number of storage items of the page table base address management structure is equal to the maximum value of the ASID field in the TTBR0 register.

4. The method for fast address space switching based on domain space management of the ARM platform according to claim 1, characterized in that: The page table structure of the system domain for building the embedded operating system is in the long descriptor page table format in the 32-bit execution state.

5. The method for fast address space switching based on domain space management of the ARM platform according to claim 1, characterized in that: The domain includes a system domain and sub-areas.

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