Access method and related device

Abstract

The embodiment of the invention provides an access method, the access method is applied to first nodes in a target system, and each first node in the target system comprises a processor and a first memory. If a first node (namely a local node) initiates an access request for a target address in a remote memory of a remote node, after a first operation is executed, a second operation is executed after a target time is delayed, the target time is randomly generated by the local node, or the target time corresponds to an associated node (the local node and the remote node), and the remote memory of the remote node is accessed to the associated node. Thus, through a mode of delaying the target time after the first operation, the position factor when different local nodes access the remote memory in the same remote node is weakened, the problem that the access success rate of the first node to the remote memory of a certain or some remote nodes is always low is avoided, and the access success rate of the first node to the remote memory of the remote node is improved. The fairness of atomic operations, i.e., the first operation and the second operation, is improved.

Description

Technical Field

[0001] The present specification relates to the field of computer application technology, and more specifically, to a memory access technology under a NUMA (Non-Uniform Memory Access) architecture under computer application technology, and more specifically, to an access method and related devices. Background Art

[0002] The NUMA (Non-Uniform Memory Access) architecture is a multi-processor architecture. There may be multiple nodes in the NUMA architecture, and each node includes one or a group of processors and its own local memory.

[0003] The memory in each node in the NUMA architecture can have two different and opposing properties, namely shared memory (Shareable Normal memory) and non-shared memory (Non-shareable Normal memory). Shared memory can be accessed by processors of other nodes in the NUMA architecture. In order to keep the shared data in the shared memory synchronized, atomic operations can be introduced to ensure that a thread will not be interrupted by other operations before the access to the shared memory is completed, thus avoiding the situation where multiple threads access the shared memory at the same time.

[0004] However, since the distribution areas of different nodes may be different, for the same shared memory, there may be a situation where the access success rate of some nodes to the shared memory is always low, resulting in unfairness of atomic operations. Summary of the invention

[0005] The embodiments of this specification provide an access method and related devices to solve the problem that the access success rate of a first node to a remote memory of one or some remote nodes is always low, and improve the fairness of atomic operations.

[0006] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions:

[0007] In a first aspect, an implementation of the present specification provides an access method, which is applied to a first node in a target system, wherein the target system includes a plurality of first nodes, and the first node includes a processor and a first memory; the access method includes:

[0008] In response to an access request for a target address, an access operation is performed, wherein the target address is located in a remote memory of a remote node, wherein the remote node includes a first node other than a local node, wherein the remote memory includes a first memory of the remote node; and wherein the local node includes a first node that performs the access operation;

[0009] The access operation includes:

[0010] Performing a first operation, the first operation being used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access tag corresponding to the processor of the local node;

[0011] After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

[0012] In a second aspect, an embodiment of the present specification provides a communication system, including a plurality of first nodes, wherein the first nodes include a processor and a first memory;

[0013] The first node is configured as:

[0014] In response to an access request for a target address, an access operation is performed, wherein the target address is located in a remote memory of a remote node, wherein the remote node includes a first node other than a local node, wherein the remote memory includes a first memory of the remote node; and wherein the local node includes a first node that performs the access operation;

[0015] The access operation includes:

[0016] Performing a first operation, the first operation being used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access tag corresponding to the processor of the local node;

[0017] After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

[0018] In a third aspect, an embodiment of the present specification further provides a computing device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the access method as described above when executing the computer program.

[0019] In a fourth aspect, an embodiment of the present specification further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the access method described above is implemented.

[0020] In a fifth aspect, an embodiment of the present specification provides a computer program product or a computer program, wherein the computer program product includes a computer program, and the computer program is stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and the processor implements the steps of the above-mentioned access method when executing the computer program.

[0021] It can be seen from the above technical scheme that the access method provided in the embodiment of this specification is applied to the first node in the target system, and each first node in the target system includes a processor and a first memory. When the access method is implemented, if a first node (i.e., a local node) initiates an access request for a target address in a remote memory of a remote node, then after executing the first operation, the second operation is executed after delaying the target time, and the target time is randomly generated by the local node, or the target time corresponds to the associated nodes (local node and remote node). In this way, by delaying the target time after the first operation, the location factor when different local nodes access the remote memory in the same remote node is weakened, thereby avoiding the problem of the first node's access success rate to the remote memory of one or some remote nodes being always low, and improving the fairness of atomic operations (i.e., the first operation and the second operation). BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the structure of a communication system provided in an embodiment of this specification;

[0024] Figure 2 A flowchart of an access method provided for one embodiment of this specification;

[0025] Figure 3 A schematic diagram of different local nodes accessing the same remote node provided by one embodiment of this specification;

[0026] Figure 4A schematic diagram of a display method of a first target matrix provided for one embodiment of this specification;

[0027] Figure 5 A schematic diagram of the structure of a computing device provided for one embodiment of the present specification. DETAILED DESCRIPTION

[0028] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this specification shall have the common meanings understood by persons with ordinary skills in the field to which this specification belongs. The words "first", "second" and similar words used in the embodiments of this specification do not indicate any order, quantity or importance, but are only used to avoid confusion of constituent elements.

[0029] Unless the context requires otherwise, throughout the specification, "plurality" means "at least two", and "including" is interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples", "specific examples" or "some examples" are intended to indicate that a particular feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the specification. The schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0030] The following will be combined with the drawings in the embodiments of this specification to clearly and completely describe the technical solutions in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0031] Overview

[0032] The traditional SMP (Symmetric Multi-Processor) architecture is a multi-processor architecture in which all processors share the same memory and bus resources, and each processor can access the memory space of the entire system. However, the SMP architecture has poor scalability. As the number of processors increases, the memory bandwidth may become a bottleneck, resulting in performance degradation. To solve this problem, the NUMA architecture, in which each processor or a group of processors has its own local memory, came into being. When the storage capacity or the number of processors needs to be expanded, it can be achieved by adding nodes, which has strong scalability. Figure 1 , Figure 1 A feasible NUMA architecture is shown in Figure 1In the present invention, different first nodes (first node 0 and first node 1) each include a processor and a first memory (Memory), the number of processors in each first node can be one or more, the number of processors in each first node can be the same or different, the number of processor cores (for example, CPU0 and CPU1) included in each processor can be one or more, the number of processor cores included in each processor can be the same or different, and this specification does not limit this.

[0033] In some implementations, the processor may further include a local monitor, the first node may further include a network-on-chip (NOC), and the interconnection bus may include a global monitor. As described above, in the NUMA architecture, the first memory in each first node may include a shared memory and a non-shared memory, wherein the shared memory may be accessed by processors in multiple first nodes, and the non-shared memory may be accessed by a processor local to the first node.

[0034] In order to distinguish the first node that issues an access request and the first node where the first memory requested for access is located, the first node that issues the access request can be called a local node, and the first node of the first memory where the target address requested for access is located can be called a remote node; the first memory in the remote node can be called a remote memory.

[0035] If the processor wants to exclusively access the non-shared memory of the local first memory, it only needs to operate the local monitor inside the local processor in the local node (i.e., the first node where the processor performing the specific access operation is located). If the processor wants to access the shared memory of the remote memory in other first nodes (i.e., the remote node), in addition to involving the local monitor inside the processor in the local node, since the shared memory can be accessed by processors in other first nodes in the system, it also needs to be coordinated by the global monitor.

[0036] In some embodiments, when the processor of the local node accesses the shared memory of the remote node, the processor can call the first operation to access a certain segment of shared memory. At this time, the global monitor will set an exclusive access mark for the processor. When the processor calls the second operation to access the segment of shared memory, if the exclusive access mark for the processor still exists, the shared memory can be accessed. After the access is completed, the global monitor will clear the exclusive access marks of all processors that apply for exclusive use of the segment of shared memory. If the exclusive access mark for the processor no longer exists when the processor calls the second operation to access the segment of shared memory, it indicates that other processors have performed access operations on the segment of shared memory between the processor calling the first operation and the second operation. At this time, the processor fails to call the second operation to access the segment of shared memory, and needs to re-call the first operation to set the exclusive access mark corresponding to the processor for the segment of shared memory.

[0037] The first operation mentioned above includes but is not limited to Load-Linked operation (LL operation for short), and the second operation mentioned above includes but is not limited to Store-Conditional operation (SC operation for short). The first operation and the second operation together implement atomic operations for shared memory. The LL operation can load a value from memory into a register and mark the corresponding memory location as "linked". The SC operation can try to store a value to a memory location previously loaded by the LL operation. If no other write operations have occurred on the memory location since the load, the SC operation succeeds and the memory location will be updated. Otherwise, the SC operation fails and may need to be retried.

[0038] In the NUMA architecture, the processors and first memories in the system are distributed between different first nodes (or areas). Each first node has its own local first memory. If a processor needs to access the remote memory in a remote node, a relatively high delay will occur. When different first nodes initiate access to the remote memory in the same remote node, due to the different distances from the remote memory, the access success rate of the processors in one or some first nodes to the remote memory may remain at a low level, resulting in unfairness in atomic operations.

[0039] In order to solve this problem, the inventors have found that for a target system including multiple first nodes (for example, Figure 1For a system based on the NUMA architecture shown in the figure, when a first node (local node) in the target system needs to access a remote memory in another first node (remote node) across nodes, the processor of the local node can delay the target time before executing the second operation after executing the first operation. The target time can be randomly generated by the local node. In this way, when each first node accesses the memory, it will delay the random length of time before actually accessing it, thereby avoiding the situation where the access success rate of a first node to the memory is continuously low, which is conducive to improving the fairness of atomic operations.

[0040] In addition, the target time can also correspond to an associated node, which includes a local node and a remote node. In this way, the target time can be adaptively adjusted according to the different associated nodes, so that the delay for different first nodes to access the remote memory of the remote node is basically the same, avoiding the situation where a certain first node has a continuously low access success rate to the memory, which is conducive to improving the fairness of atomic operations.

[0041] When the target time corresponds to the associated node, a first target matrix including access parameters of the corresponding relationship between each two first nodes and the access delay, and / or a second target matrix including the corresponding relationship between each first node and the success rate of accessing the remote memory can be collected in advance, and the first target matrix and / or the second target matrix can be queried based on the associated node to obtain the access parameter, which can include at least one of the first parameter and the second parameter, the first parameter including: the success rate of the local node accessing the remote memory, and the second parameter including: the access delay between the local node and the remote node; after obtaining the access parameter, a more accurate target time can be determined based on the access parameter to compensate for the delay of different first nodes accessing the remote memory, so as to ensure that the delay of different first nodes accessing the remote memory is basically consistent,

[0042] Based on the above concept, an access method is provided in the embodiment of this specification, and the access method will be exemplarily described below in conjunction with the accompanying drawings.

[0043] Exemplary Methods

[0044] To be applied to Figure 2 Taking the first node shown in the figure as an example, the implementation mode of this specification provides an access method. Figure 2 The target system in the embodiment includes a plurality of first nodes, each of which includes a processor and a first memory, and the access method includes:

[0045] S201: In response to an access request for a target address, performing an access operation, the target address is located in a remote memory of a remote node, the remote node includes another first node other than a local node, the remote memory includes a first memory of the remote node; the local node includes a first node that performs the access operation;

[0046] In this embodiment, the first node that needs to access the target address when performing the access operation is called a local node; the first node where the first memory where the target address is located is located, or the first node that the local node needs to access is called a remote node. As mentioned above, when a local node accesses a remote node, there may be a problem that the access success rate of one or some local nodes to the remote node is long-term low due to factors such as different distances between different local nodes and the remote node and different processor performance in different local nodes. Therefore, the access method provided in the embodiment of this specification is committed to solving the above problems. For the process of the processor in the first node accessing the local first memory, reference can be made to the process in the relevant technology.

[0047] The access operation includes:

[0048] S2011: Execute a first operation, wherein the first operation is used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access mark corresponding to the processor of the local node;

[0049] Optionally, as described above, the first operation may include an LL operation. Specifically, the LL operation may load a value from a memory into a register and mark the corresponding memory location as "linked" to achieve the purpose of registering an exclusive access intention for a target address with a remote node.

[0050] S2022: After delaying the target time, execute a second operation, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

[0051] After the first node executes the first operation, the second operation is executed after a delay of a target time. Optionally, the second operation may include an SC operation. The SC operation may attempt to store a value to a memory location previously loaded by an LL operation. If no other write operations have occurred at the memory location since the LL operation was loaded, the storage operation is successful and the memory location is updated (the update may be to clear the exclusive access flags corresponding to all processors). Otherwise, the storage operation fails and may need to be retried. In some embodiments, the LL operation may use an LDXR (Load-Exclusive) instruction and the SC operation may use an STXR (Store-Exclusive) instruction.

[0052] From the above description of LL operation and SC operation, it is not difficult to find that Figure 3 As shown in the figure, for the same remote node, if different local nodes (local node 1 and local node 2) initiate access to the remote memory in the remote node at the same time, since local node 1 is closer to the remote node, the data transmission delay between local node 1 and the remote node is usually smaller. Therefore, after local node 1 and local node 2 have performed LL operations, when local node 1 performs SC operation, local node 2 may not have started to perform SC operation (or the instruction to perform SC operation has not been received by the remote node). At this time, the exclusive access tag corresponding to the processor of local node 1 loaded by the LL operation of local node 1 in the remote memory exists, and the SC operation is successfully implemented to achieve access to the target address and clear all exclusive access tags; afterwards, when local node 2 performs SC operation, since local node 1 has cleared all exclusive access tags, local node 2 fails to perform SC operation and needs to re-perform LL operation, load the exclusive access tag corresponding to the processor in local node 2 to the target address and then perform SC operation. If the access requirements of local node 1 and local node 2 for the remote memory are highly consistent, it may cause local node 2 to be unable to access the remote memory for a long time.

[0053] Therefore, in this embodiment, after the first node executes the first operation, it delays the target time before executing the second operation. The target time can be randomly generated. In this way, when each first node accesses the memory, it will delay for a random period of time before making the actual access, thereby avoiding the situation where the access success rate of a first node to the memory is continuously low, which is beneficial to improving the fairness of atomic operations.

[0054] In addition, the target time can also correspond to an associated node, which includes a local node and a remote node. In this way, the target time can be adaptively adjusted according to the different associated nodes, so that the delay for different first nodes to access the remote memory of the remote node is basically the same, avoiding the situation where a certain first node has a continuously low access success rate to the memory, which is conducive to improving the fairness of atomic operations.

[0055] When the target time corresponds to the associated node, an embodiment of the present specification provides a process for determining the target time. Specifically, the process includes:

[0056] Determining the remote node according to the target address;

[0057] The target time is determined based on the access parameters corresponding to the associated node, the access parameters including at least one of a first parameter and a second parameter, the first parameter including: a success rate of the local node accessing the remote memory, the second parameter including: an access delay between the local node and the remote node.

[0058] In this embodiment, in order to accurately determine the target time so that for the same remote node, the total delay for different local nodes to access the remote node is basically the same, the target time can be determined based on the access parameters corresponding to the associated nodes, so that after delaying the target time, the total delay time for each local node to the same remote node is basically the same, thereby ensuring that the access success rates of different local nodes to the remote node are basically the same, avoiding the problem of a continuously low access success rate of one or some local nodes to a certain remote node.

[0059] The following is an exemplary description of how to determine the target time when the access parameters include different parameter types.

[0060] For example, in one embodiment, the access parameter includes the second parameter;

[0061] The determining the target time based on the access parameter corresponding to the associated node includes:

[0062] Based on the associated node, query the first target matrix to obtain the second parameter;

[0063] Based on the second parameter, determining the target time;

[0064] The first target matrix includes a corresponding relationship between every two of the first nodes and access delays.

[0065] In this embodiment, the corresponding relationship between every two first nodes and the access delay can be collected to obtain the following: Figure 4 The first target matrix is ​​shown, Figure 4 In the example, Numa0~n represents the 0th to nth first nodes, and Delay(ns) represents the access delay (expressed in nanoseconds) between each two first nodes. The access delay may refer to the delay caused by transmitting instructions or information through a communication link of a certain length, or the access delay may refer to the time required for instructions or information to be transmitted between different first nodes. The first target matrix can be obtained by testing each two first nodes using a memory delay test tool.

[0066] In actual application, the first target matrix can be queried based on the associated node to obtain the second parameter corresponding to the local node and the remote node. Specifically, assuming that the local node is Numa0 and the remote node is Numa1, the second parameter corresponding to when Numa0 accesses Numa1 can be obtained by looking up the table in the first target matrix.

[0067] After obtaining the second parameter, the second parameter may be determined as the target time, or the target time may be obtained after processing the second parameter. This specification does not limit this, and it depends on the actual situation.

[0068] In this embodiment, the second parameter is obtained by table lookup, and the target time is determined based on the second parameter, so that the determined target time can be associated with the second parameter, which is beneficial to compensate for the delay caused by the distance difference between different first nodes and remote nodes, and is beneficial to ensuring that the access success rate of different first nodes to the same remote node is basically the same.

[0069] Also for example, in another embodiment, the access parameter includes the first parameter;

[0070] The determining the target time based on the access parameter corresponding to the associated node includes:

[0071] Based on the associated node, query a second target matrix to obtain the first parameter;

[0072] Based on the first parameter, determining the target time, wherein the target time is positively correlated with a success rate of accessing the remote storage;

[0073] The second target matrix includes a corresponding relationship between each of the first nodes and a success rate of accessing the remote memory.

[0074] Similarly, in this embodiment, the second target matrix can be obtained by collecting the success rates of each first node accessing the same remote storage. Referring to Table 1, Table 1 shows a feasible presentation form of the second target matrix.

[0075] Table 1 Second target matrix

[0076] Numa0 Numa1 Numa2 …… Numan Numa0 Rate(%) Rate(%) Rate(%) Rate(%) Numa1 Rate(%) Rate(%) Rate(%) Rate(%) Numa2 Rate(%) Rate(%) Rate(%) Rate(%) …… Rate(%) Rate(%) Rate(%) Rate(%) Numan Rate(%) Rate(%) Rate(%) Rate(%)

[0077] In Table 1, Numa0~n represents the 0th to nth first nodes, and Rate (%) represents the success rate (expressed in %) of a first node accessing another first node, wherein the first node in the first row is a local node and the first node in the first column is a remote node. For example, for the second row and third column, Rate (%) represents the success rate of Numa1 accessing Numa0. The success rate can be equal to the proportion of the second operation successfully implemented to the total number of second operations. For example, assuming that within a period of time, the number of second operations implemented by Numa1 accessing the remote storage in Numa0 is 100 times, and the number of second operations successfully implemented is 30 times, then the success rate of Numa1 accessing Numa0 can be calculated as 30 / 100=30%. The second target matrix can be obtained by collecting historical data or testing by means of a test tool.

[0078] In actual application, the second target matrix can be queried based on the associated node to obtain the first parameters corresponding to the local node and the remote node. Specifically, assuming that the local node is Numa0 and the remote node is Numa1, the first parameter corresponding to when Numa0 accesses Numa1 can be obtained by looking up the table in the second target matrix.

[0079] After obtaining the first parameter, a target time positively correlated with the first parameter can be determined based on the first parameter. Specifically, assuming that the remote node is Numa0, and the success rates of Numa1 and Numa2 accessing Numa0 are 30% and 90% respectively, when Numa1 accesses Numa0, its target time can be positively correlated with 30%, for example, 30ns, and when Numa2 accesses Numa0, its target time can be positively correlated with 90%, for example, 90ns. In this way, by adding a longer delay time (90ns) when Numa2 accesses Numa0 and a shorter delay time (30ns) when Numa1 accesses Numa0, the success rates of Numa2 and Numa1 accessing Numa0 can be brought to basically the same level, thereby avoiding the situation where Numa1 cannot successfully access Numa0 for a long time when Numa2 and Numa1 access Numa0 at the same time.

[0080] For another example, in yet another embodiment, a method for determining a target time by comprehensively considering a first parameter and a second parameter is provided. Specifically, determining the target time based on the access parameter corresponding to the associated node includes:

[0081] Based on the first parameter, obtaining a first time corresponding to the first parameter;

[0082] Based on the second parameter, obtaining a second time corresponding to the second parameter;

[0083] The target time is obtained based on the first time, the second time, the weights corresponding to the first parameter and the second parameter.

[0084] In this embodiment, after obtaining the first parameter and the second parameter, the first time and the second time can be obtained based on the first parameter and the second parameter, respectively. The first parameter and the second parameter can also correspond to different weights respectively. Afterwards, the target time can be obtained by weighted summing based on the first time, the second time, the weights corresponding to the first parameter and the second parameter. In this way, different weights can be assigned to the first parameter and the second parameter respectively, so as to determine the target time by comprehensively considering the first parameter and the second parameter.

[0085] For example, assuming that the weights corresponding to the first parameter and the second parameter are 0.3 and 0.7 respectively, and the first time and the second time are 30ns and 20ns respectively, the target time obtained by weighted summation may be equal to 0.3×30ns+0.7×20ns=23ns.

[0086] In one embodiment, a feasible method for delaying a target time is provided. Specifically, the delaying the target time includes:

[0087] Determine an execution duration based on a target parameter of a processor of the local node, wherein the execution duration includes a duration required for the processor of the local node to execute a single target instruction;

[0088] Determine a target number of instructions based on the target time and the execution duration;

[0089] Based on the determined number of target instructions, a plurality of the target instructions are executed, the target instructions corresponding to no operations.

[0090] In this embodiment, the execution time is determined by the target parameters of the processor of the local node. The target parameters of the processor include but are not limited to the processor frequency. In this way, the accurate execution time can be determined based on the specific situation of each processor, and then the number of target instructions required to delay the target time can be determined based on the accurate execution time, so that the purpose of accurately delaying the target time can be achieved by executing multiple target instructions. The target instruction includes but is not limited to the NOP (No Operation) instruction. By executing the target instruction, the delay of the unit time (i.e., the execution time) can be achieved without affecting the instructions of other normal tasks of the processor. For example, assuming that for processor A, the execution time of its execution target instruction is 2ns, when the target time is 30ns, if you want to delay 30ns, you need to execute 30ns / 2ns=15 target instructions. For processor B, assuming that the execution time of its execution target instruction is 3ns, when the target time is 30ns, if you want to delay 30ns, you need to execute 30ns / 3ns=10 target instructions.

[0091] Exemplary Devices

[0092] In an exemplary embodiment of the present specification, an access device is further provided, which is applied to a first node in a target system, wherein the target system includes a plurality of first nodes, and the first node includes a processor and a first memory; the access device includes:

[0093] an operation delay module, configured to perform an access operation in response to an access request for a target address, wherein the target address is located in a remote memory of a remote node, wherein the remote node includes a first node other than a local node, wherein the remote memory includes a first memory of the remote node; and wherein the local node includes a first node for performing the access operation;

[0094] The access operation includes:

[0095] Performing a first operation, the first operation being used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access tag corresponding to the processor of the local node;

[0096] After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

[0097] For the specific definition of the access device, please refer to the definition of the access method above, which will not be repeated here. Each module in the above access device can be implemented in whole or in part by software, hardware and their combination. The above modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0098] Exemplary Devices

[0099] An embodiment of the present specification also provides a communication system, referring to Figure 1 , comprising a plurality of first nodes, wherein the first nodes comprise a processor and a first memory;

[0100] The first node is configured as:

[0101] In response to an access request for a target address, an access operation is performed, wherein the target address is located in a remote memory of a remote node, wherein the remote node includes a first node other than a local node, wherein the remote memory includes a first memory of the remote node; and wherein the local node includes a first node that performs the access operation;

[0102] The access operation includes:

[0103] Performing a first operation, the first operation being used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access tag corresponding to the processor of the local node;

[0104] After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

[0105] Optionally, the first node further includes: a global monitor;

[0106] The global monitor is configured to: in response to the first operation, set a corresponding exclusive access tag for the processor executing the first operation; in response to an access operation to the target address, clear the exclusive access tags of all the processors to the target address.

[0107] For the relevant limitations on the access method implemented by the first node in the communication system, please refer to the relevant description above, and this specification will not elaborate on it here.

[0108] Another embodiment of the present application further provides a computing device, see Figure 5 As shown, an exemplary embodiment of the present specification also provides a computing device, including: a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the access method according to various embodiments of the present specification described in the above embodiments of the present specification are executed.

[0109] The internal structure of the computing device can be as follows Figure 5 As shown, the computing device includes a processor, a memory, a network interface and an input device connected through a system bus. Among them, the processor of the computing device is used to provide computing and control capabilities. The memory of the computing device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computing device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the access method according to various embodiments of the present specification described in the above embodiments of the present specification are performed.

[0110] The processor may include a main processor and may also include a baseband chip, a modem, etc.

[0111] The memory stores a program for executing the technical solution of the present invention, and may also store an operating system and other key services. Specifically, the program may include a program code, and the program code includes computer operation instructions. More specifically, the memory may include a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM), other types of dynamic storage devices that can store information and instructions, a disk storage, a flash, and the like.

[0112] The processor may be a general-purpose processor, such as a general-purpose central processing unit (CPU), a microprocessor, etc., or an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the scheme of the present invention. It may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0113] The input device may include a device for receiving data and information input by a user, such as a keyboard, a mouse, a camera, a scanner, a light pen, a voice input device, a touch screen, a pedometer, or a gravity sensor.

[0114] Output devices may include means that allow information to be output to a user, such as display screens, printers, speakers, etc.

[0115] The communication interface may include using any transceiver or the like to communicate with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0116] The processor executes the program stored in the memory and calls other devices, which can be used to implement each step of any access method provided in the above embodiments of the present application.

[0117] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display or an electronic ink display. The input device of the computing device may be a touch layer covered on the display component, or a button, trackball or touchpad provided on the housing of the computing device, or an external keyboard, touchpad or mouse.

[0118] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of this specification, and does not constitute a limitation on the computing device to which the scheme of this specification is applied. The specific computing device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0119] Exemplary computer program products and storage media

[0120] In addition to the above-mentioned methods and devices, the access method provided in the embodiments of this specification may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the access method according to various embodiments of this specification described in the above "Exemplary Method" section of this specification.

[0121] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the embodiments of the present specification, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0122] In addition, an embodiment of the present specification also provides a computer-readable storage medium on which a computer program is stored, and the computer program is executed by a processor to execute the steps of the access method according to various embodiments of the present specification described in the above "Exemplary Method" section of the present specification.

[0123] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0124] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The above-mentioned embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the solutions provided by the embodiments of this specification. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.

Claims

1. An access method, characterized in that: Applied to a first node in a target system, the target system includes a plurality of first nodes, the first node includes a processor and a first memory; the access method includes: In response to an access request for a target address, an access operation is performed, wherein the target address is located in a remote memory of a remote node, wherein the remote node includes a first node other than a local node, wherein the remote memory includes a first memory of the remote node; and wherein the local node includes a first node that performs the access operation; The access operation includes: Performing a first operation, the first operation being used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access tag corresponding to the processor of the local node; After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

2. The method according to claim 1, characterized in that The process of determining the target time includes: Determining the remote node according to the target address; The target time is determined based on the access parameters corresponding to the associated node, the access parameters including at least one of a first parameter and a second parameter, the first parameter including: a success rate of the local node accessing the remote memory, the second parameter including: an access delay between the local node and the remote node.

3. The method according to claim 2, characterized in that: The access parameters include the second parameter; The determining the target time based on the access parameter corresponding to the associated node includes: Based on the associated node, query the first target matrix to obtain the second parameter; Based on the second parameter, determining the target time; The first target matrix includes a corresponding relationship between every two of the first nodes and access delays.

4. The method according to claim 2, characterized in that: The access parameters include the first parameter; The determining the target time based on the access parameter corresponding to the associated node includes: Based on the associated node, query a second target matrix to obtain the first parameter; Based on the first parameter, determining the target time, wherein the target time is positively correlated with a success rate of accessing the remote storage; The second target matrix includes a corresponding relationship between each of the first nodes and a success rate of accessing the remote memory.

5. The method according to claim 2, characterized in that: The determining the target time based on the access parameter corresponding to the associated node includes: Based on the first parameter, obtaining a first time corresponding to the first parameter; Based on the second parameter, obtaining a second time corresponding to the second parameter; The target time is obtained based on the first time, the second time, the weights corresponding to the first parameter and the second parameter.

6. The method according to any one of claims 1 to 5, characterized in that: The delay target time includes: Determine an execution duration based on a target parameter of a processor of the local node, wherein the execution duration includes a duration required for the processor of the local node to execute a single target instruction; Determine a target number of instructions based on the target time and the execution duration; Based on the determined number of target instructions, a plurality of the target instructions are executed, the target instructions corresponding to no operations.

7. A communication system, characterized in that: The method comprises a plurality of first nodes, wherein the first nodes comprise a processor and a first memory; The first node is configured as: In response to an access request for a target address, performing an access operation, the target address being located in a remote memory of a remote node, the remote node comprising a first node other than the local node, the remote memory comprising a first memory of the remote node; The local node includes a first node that performs the access operation; The access operation includes: Performing a first operation, the first operation being used to register an exclusive access intention for the target address with the remote node, so that the remote node sets an exclusive access tag corresponding to the processor of the local node; After delaying the target time, a second operation is performed, wherein the second operation is used to access the target address when there is an exclusive access tag corresponding to the processor of the local node; the target time is randomly generated by the local node, or the target time corresponds to an associated node, and the associated node includes the local node and the remote node.

8. The system according to claim 7, characterized in that The first node also includes: a global monitor; The global monitor is configured to: in response to the first operation, set a corresponding exclusive access tag for the processor executing the first operation; in response to an access operation to the target address, clear the exclusive access tags of all the processors to the target address.

9. A computing device, characterized in that The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the access method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the access method according to any one of claims 1 to 6 is implemented.

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