System and method for interface management

Abstract

Systems and methods for interface management are provided. The system comprises a main processor, a switcher and a first secondary circuit. The main processor comprises a universal asynchronous receiver / transmitter interface and a control interface. The switcher is coupled to the universal asynchronous receiver / transmitter interface and the control interface. The first sub-circuit includes a first sub-interface. The first interface is coupled to the switcher. The switcher conducts a transmission path between the universal asynchronous receiver / transmitter interface and the first interface according to a control signal received by the control interface. Thus, a single universal asynchronous receiver / transmitter interface can be used for connecting a plurality of secondary circuits with universal asynchronous receiver / transmitter interfaces.

Description

Technical Field

[0001] The present invention relates to a communication interface technology, and in particular, to a system and method for interface management. Background Art

[0002] The Universal Asynchronous Receiver / Transmitter (UART) interface is a commonly used communication interface in embedded systems. The UART interface can be used to connect additional modules (e.g., satellite positioning modules, or Bluetooth modules) or provide a debug port. Generally speaking, if there are multiple application requirements (e.g., debug and data transmission), a corresponding number of UART interfaces are required. For a system with a single UART interface, even if an additional Universal Serial Bus (USB) interface or Ethernet interface is provided, the debug port may still occupy the only UART interface and prevent other modules from using the UART interface. Summary of the invention

[0003] The present invention is directed to a system and method for interface management, which can use a single UART interface to complete multiple application requirements.

[0004] According to an embodiment of the present invention, a system for interface management includes (but is not limited to) a main processor, a switch and a first circuit. The main processor includes a Universal Asynchronous Receiver / Transmitter (UART) interface and a control interface. The switch is coupled to the UART interface and the control interface. The first circuit includes a first interface. The first interface is coupled to the switch. The switch conducts a transmission path between the UART interface and the first interface according to a control signal received via the control interface.

[0005] According to an embodiment of the present invention, the method for interface management includes (but is not limited to) the following steps: providing a main processor, wherein the main processor includes a UART interface; transmitting a control signal through the main processor; providing a switch and a first circuit, wherein the first circuit includes a first interface; and connecting the transmission path between the UART interface and the first interface according to the control signal through the switch.

[0006] According to an embodiment of the present invention, a system for interface management includes a UART interface, a switching circuit, a first circuit and a second circuit. The switching circuit is coupled to the UART interface. The first circuit is coupled to the switching circuit, and the first circuit includes the first interface. The second circuit is coupled to the switching circuit, and the second circuit includes the second interface. The switching circuit conducts a first transmission path between the UART interface and the first interface, or conducts a second transmission path between the UART interface and the second interface according to a first control signal.

[0007] Based on the above, the system and method for interface management according to the embodiment of the present invention can conduct the transmission path through the UART interface through the switch, thereby allowing the main processor to connect one or more sub-circuits with UART interfaces through a UART interface and conduct the transmission path connected to a specific sub-circuit according to application requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0009] Figure 1 is a block diagram of components of a system according to an embodiment of the present invention;

[0010] Figure 2 is a block diagram of components of a system according to another embodiment of the present invention;

[0011] Figure 3 is a state diagram according to an embodiment of the present invention;

[0012] Figure 4 is a flow chart of the operation according to an embodiment of the present invention;

[0013] Figure 5A is a schematic diagram illustrating a transmission path in an initial stage according to an embodiment of the present invention;

[0014] Figure 5B is a schematic diagram illustrating a transmission path leaving an initial stage according to an embodiment of the present invention;

[0015] Figure 5C is a schematic diagram illustrating a transmission path for data transmission requirements according to an embodiment of the present invention;

[0016] Figure 6 is a block diagram of components of a system according to another embodiment of the present invention;

[0017] Figure 7 is a flow chart of a method according to an embodiment of the present invention.

[0018] Description of Figure Numbers

[0019] 1, 1', 1": system;

[0020] 10: main processor;

[0021] 11:UART interface;

[0022] 12-15: control interface;

[0023] 31-34: switch;

[0024] 51-55: secondary circuit;

[0025] 511-551: secondary interface;

[0026] 71, 72, 73, 74: voltage level conversion circuit;

[0027] S1: first state;

[0028] S2: second state;

[0029] S3: the third state;

[0030] S401-S420, S710-S740: steps;

[0031] P1~P5: path. DETAILED DESCRIPTION

[0032] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0033] Figure 1 is a block diagram of components of a system 1 according to an embodiment of the present invention. Figure 1 , the system 1 includes (but is not limited to) a main processor 10, a switch 31 and a sub-circuit 51.

[0034] In one embodiment, the system 1 is an embedded system. The embedded system may be applied to the fields of communication, industry, automation, commerce or military, but the embodiment of the present invention does not limit its application field. In other embodiments, the system 1 may also be other computer systems.

[0035] The main processor 10 may be a central processing unit (CPU), a graphics processing unit (GPU), a programmable general-purpose or special-purpose microprocessor, a digital signal processor (DSP), a programmable controller, a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a neural network accelerator, or other similar components or a combination of the above components. In one embodiment, the main processor 10 is used to execute all or part of the operations of the system 1. For example, the main processor 10 executes a bootloader, loads or executes an operating system, a kernel, a driver, firmware, and / or a file system.

[0036] The main processor 10 includes one or more Universal Asynchronous Receiver / Transmitter (UART) interfaces 11 and one or more control interfaces 12 .

[0037] The UART interface 11 includes (but is not limited to) a chip / controller / processor / control circuit, a circuit board, and a connector (e.g., a pin) that supports the UART protocol. In one embodiment, the UART interface 11 is integrated into the main processor 10. In another embodiment, the UART interface 11 is a modular control board or device, and is communicatively connected to the main processor 10.

[0038] The control interface 12 may be a general-purpose input / output (GPIO), a serial bus interface, a network interface, or other transmission interface. In one embodiment, the control interface 12 is integrated into the main processor 10. In another embodiment, the control interface 12 is a modular control board or device (including a chip / controller / processor / control circuit, circuit board, and connector supporting a corresponding communication protocol), and is communicatively connected to the main processor 10.

[0039] The switch 31 is coupled to the UART interface 11, the control interface 12 and the sub-circuit 51. Hereinafter, the switch 31 or other switches may also be referred to as a switching circuit.

[0040] The secondary circuit 51 may be a satellite positioning circuit, a Bluetooth transceiver circuit, a USB connector, an Internet of Things (IoT) device, an Ethernet connector, or other circuits / modules / devices. The satellite positioning circuit may be a receiver supporting the Global Positioning System (GPS), the Global Navigation Satellite System (GLONASS), the BeiDou Satellite Navigation System, or the Galileo Positioning System (GALILEO). IoT devices are, for example, sensors, household appliances, automation equipment, or vehicle-mounted systems, but are not limited thereto.

[0041] The sub-circuit 51 includes a sub-interface 511. The sub-interface 511 is coupled to the switch 31. In one embodiment, the sub-interface 511 is an interface supporting or compatible with UART, and can be directly or indirectly connected to the UART interface 11.

[0042] Figure 2 is a block diagram of components of a system 1' according to another embodiment of the present invention. Figure 2 , compared to Figure 1 The system 1′ further includes switches 32 and 33 and sub-circuits 52 and 53. In addition, the main processor 10 further includes control interfaces 13 and 14 and an auxiliary interface 15.

[0043] The functions and implementation methods of the control interfaces 13 and 14 can refer to the aforementioned Figure 1 The description of the control interface 12 is not repeated here.

[0044] The auxiliary interface 15 may be a USB interface or an Ethernet interface (for example, providing an RJ45 port). The secondary circuit 51 may be a connector / device / module / circuit having a USB port or an Ethernet port. That is, the secondary interface 511 is a USB interface or an Ethernet interface.

[0045] The switch 32 is coupled to the switch 31 , the auxiliary interface 15 , and the secondary interface 511 of the secondary circuit 51 .

[0046] The switch 33 couples the switch 31 and the sub-circuits 52 and 53. The switch 33 includes a first port coupled to the UART interface 11, a control port coupled to the control interface 14, and a plurality of second ports coupled to the sub-circuits 52 and 53 respectively.

[0047] The functions and implementation of the sub-circuits 52 and 53 can be referred to above. Figure 1 The description of the sub-circuit 51 is not repeated here.

[0048] The sub-circuit 52 includes a sub-interface 521, and the sub-circuit 53 includes a sub-interface 531. The sub-interface 521 is coupled to the switch 33, and the sub-interface 531 is coupled to the switch 33. The functions and implementations of the sub-interfaces 521 and 531 can refer to the above Figure 1 The description of the secondary interface 511 is not repeated here. For example, the secondary interfaces 521 and 531 are UART interfaces.

[0049] In one embodiment, the system 1 ′ further includes voltage level conversion circuits 71 ˜ 74 .

[0050] The voltage level conversion circuit 71 is coupled between the UART interface 11 and the switch 31 , the voltage level conversion circuit 72 is coupled between the auxiliary interface 15 and the switch 32 , and the voltage level conversion circuit 73 is coupled between the switch 33 and the sub-circuit 52 .

[0051] In one embodiment, the voltage level conversion circuits 71-74 output the same level. For example, the voltage level of the output signal includes a first level and a second level. The voltage level of the first level output by the voltage level conversion circuits 71-74 is consistent, and / or the voltage level of the second level output by the voltage level conversion circuits 71-74 is consistent.

[0052] It should be noted that the number of control interfaces 12 to 14 corresponds to the number of switches 31 to 33. For example, a one-to-one connection. However, in other embodiments, the number and connection method of the control interfaces and switches are not limited to Figure 2 For example, one-to-many connection. In addition, the number and connection mode of the input ports and output ports of the switch can also be adjusted according to actual needs, and the embodiment of the present invention is not limited thereto.

[0053] Figure 3 is a schematic diagram of the state according to an embodiment of the present invention. Figure 3 ,by Figure 2 Take system 1' as an example ( Figure 1 The operating state of the main processor 10 includes a first state S1, a second state S2 or a third state S3. The first state S1: In the initial stage of the system 1' (e.g., the boot or initialization stage), the main processor 10 can use the UART interface 11 to connect to the secondary interface 511 for debugging requirements (e.g., the application of the debugging port). The debugging requirements may be predefined or triggered by an operation.

[0054] Second state S2: When the initial stage is completed / left, the main processor 10 may use the auxiliary interface 15 to connect to the secondary interface 511 for debugging requirements, and at the same time provide the UART interface 11 to the secondary circuit 52 or 53 for use.

[0055] Third state S3: If there is a need to use the auxiliary interface 15 for a path for data transmission requirements, the main processor 10 can use the UART interface 11 to connect one of the sub-circuits 52 or 53 for debugging requirements. The data transmission requirement may be predefined or triggered by an operation. At this time, the other of the sub-circuits 52 or 53 is disconnected from the UART interface 11 (for example, the transmission path from the UART interface 11 to the other is interrupted). In some embodiments, the sub-circuit 52 or 53 is used as a satellite positioning circuit or other circuit, and its hold over function can continue to provide the clock source required to maintain synchronization without being affected by the path interruption. If there is no data transmission requirement using the auxiliary interface 15, the main processor 10 can return from the third state S3 to the second state S2.

[0056] It is worth noting that the sub-circuits 51-53 are connected to the UART interface 11 via the switches 31-33 respectively. In other words, the sub-circuits 51-53 share the UART interface 11. In one embodiment, the switch 31, 32 or 33 can conduct the transmission path between the UART interface 11 and the sub-interface 511, 521 or 531 according to the control signal via the control interface 12, 13 or 14.

[0057] Figure 4 This is a flowchart of the operation according to an embodiment of the present invention (the order of the steps can still be adjusted according to actual needs and is not limited to the order shown in the figure). Please refer to Figure 4 , the power of the system 1' is turned on (step S401) (the main processor 10 can be coupled to a power supply). The main processor 10 performs the relevant operations of the initial stage (step S402). For example, the bootloader or other boot loader is executed. The main processor 10 sets the path (step S403). Please refer to Figure 3 When the main processor 10 is in the initial stage, the main processor 10 is in the first state S1.

[0058] Figure 5A is a schematic diagram illustrating a transmission path in the initial stage according to an embodiment of the present invention. Figure 5AIn response to the main processor 10 being in the initial stage, the main processor 10 generates a control signal for conduction, and conducts the transmission path (e.g., path P1) from the UART interface 11 to the secondary interface 511. This path P1 is used for debugging requirements. More specifically, in the first state S1, the UART interface 11 is used for debugging requirements. For example, the (initial) information of the initial stage is transmitted to the UART interface 11 via the debugging port. The main processor 10 generates a control signal. Assume that the secondary circuit 51 has a USB port or an Ethernet port. This USB port or Ethernet port can be used as a debugging port. The main processor 10 can set the path P1 to be the UART interface 11, the switch 31, the switch 32 and the secondary interface 511 in sequence (step S403). This control signal indicates the aforementioned path P1 or conducts this path P1, and is transmitted to the switches 31 and 32 via the control interfaces 12 and 13. Then, the switches 31 and 32 conduct the path P1 of the UART interface 11 and the secondary interface 511 according to this control signal.

[0059] In addition, the main processor 10 may also set this control signal to interrupt the path from the UART interface 11 to the secondary interfaces 521 , 531 .

[0060] In one embodiment, the control signal includes two voltage levels / potentials: a first level and a second level. For example, the first level is a high level, and the second level is a low level. Alternatively, the first level is a low level, and the second level is a high level. The conduction of the transmission path is related to the voltage level of the control signal.

[0061] In one embodiment, in response to the control signal being at the first level, the switch turns on the transmission path. Figure 5A For example, the control signals via the control interfaces 12 to 14 are at the second level (eg, low level) by default. In the first state S1 , the control signal via the control interface 13 is at the first level (eg, high level). Therefore, the path P1 via the switch 32 is turned on.

[0062] In one embodiment, in response to the control signal being at the second level, the switch interrupts the transmission path. Figure 5A For example, the control signal via the control interface 12-14 is at the second level (e.g., low level) by default. Therefore, the path P1 via the switches 31 and 32 is interrupted. In the first state S1, the control signal via the control interface 13 is at the first level (e.g., high level), but the control signal via the control interface 14 is still at the second level. Therefore, the path via the switch 33 is interrupted.

[0063] In other embodiments, the control signal may be in other encoding forms.

[0064] Please refer to Figure 4, the main processor 10 performs a hardware initialization procedure (step S404). The main processor 10 sets the UART interface 11 for debugging requests (step S405). For example, debugging information can be received or transmitted via the UART interface 11. The main processor 10 can set the USB connector (for example, Figure 5A The sub-circuit 511 is used to debug the input / output of the port (step S406). Then, the main processor 10 loads the kernel and the file system (step S407).

[0065] The main processor 10 determines whether the core and image files have been downloaded (step S408 ) to determine whether to complete / leave the initial stage.

[0066] Figure 5B is a schematic diagram of a transmission path leaving the initial stage according to an embodiment of the present invention. Figure 5B In response to the main processor 10 leaving the initial stage, the main processor 10 generates a control signal for conduction and conducts the transmission path (e.g., path P2) from the UART interface 11 to the secondary interface 521. This transmission path is used for data transmission requirements. More specifically, in the second state S2, the auxiliary interface 15 can be used for debugging requirements. For example, debugging information is transmitted to the auxiliary interface 15 via the debugging port. The main processor 10 sets the auxiliary interface 15 (e.g., USB interface or Ethernet interface) for debugging requirements (step S409). Therefore, the UART interface 11 can be used for data transmission requirements by the secondary circuit 52 or 53. The main processor 10 generates a control signal. Assume that the secondary circuit 52 is a satellite positioning circuit. The main processor 10 can set the path P2 to be the UART interface 11, the switch 31, the switch 33 and the secondary interface 521 in sequence (step S410). This control signal indicates the aforementioned path P2 or conducts this path P2, and is transmitted to the switches 31 and 33 via the control interfaces 12 and 14. Then, the switches 31 and 33 conduct the path P2 between the UART interface 11 and the secondary interface 521 according to the control signal. In addition, the main processor 10 can also set the control signal to interrupt the path from the UART interface 11 to the secondary interface 511 (such as Figure 5A path P1).

[0067] On the other hand, in response to the main processor 10 leaving the initial stage, the auxiliary interface 15 is used for debugging requests. Therefore, the main processor 10 can switch the interface used for debugging requests from the UART interface 11 to the auxiliary interface 15 (step S411). Figure 5BFor example, when the transmission path (e.g., path P2) between the UART interface 11 and the secondary interface 521 is turned on, the switch 32 also turns on another transmission path (e.g., path P3) between the auxiliary interface 15 and the secondary interface 511 according to another control signal from the control interface 13. More specifically, the main processor 10 generates a control signal. The main processor 10 can set the path P3 to be the auxiliary interface 15, the switch 32, and the secondary interface 511 in sequence. This control signal indicates the aforementioned path P3 or turns on this path P3, and is transmitted to the switch 32 via the control interface 13. Then, the switch 32 turns on the path P3 of the auxiliary interface 15 and the secondary interface 511 according to this control signal, for receiving or transmitting a debugging signal. In addition, since the path P2 is turned on, the main processor 10 can connect the UART interface 11 to the secondary circuit 52 (step S412). For example, the satellite positioning circuit (i.e., the secondary circuit 52) ​​performs time synchronization via the UART interface 11.

[0068] The main processor 10 determines whether to set the auxiliary interface 15 (eg, USB interface or Ethernet interface) for data transmission requirements (step S413).

[0069] In one embodiment, in response to detecting a data transmission request, the main processor 10 generates a control signal for conducting and conducts the transmission path. This transmission path is used for debugging requests. If the auxiliary interface 15 is to be used for data transmission, the main processor 10 can switch the interface used for debugging requests to the UART interface 11 (step S414). Figure 5C is a schematic diagram illustrating a transmission path for data transmission requirements according to an embodiment of the present invention. Figure 5C In the third state S3, the auxiliary interface 15 can be used for data transmission requirements, and the UART interface 11 can be used for debugging requirements. For example, debugging information is transmitted to the UART interface 11 via the debugging port. In response to detecting the data transmission requirement, the main processor 10 can set the auxiliary interface 15 (for example, a USB interface or an Ethernet interface) to be used for data transmission requirements. Therefore, the auxiliary interface 15 can be used by the secondary circuit 51 for data transmission requirements. The main processor 10 generates a control signal. The main processor 10 can set the path P4 to be the auxiliary interface 15, the switch 32 and the secondary interface 511 in sequence (step S415). This control signal indicates the aforementioned path P4 or turns on this path P4, and is transmitted to the switch 32 via the control interface 13. Then, the switch 32 turns on the path P4 of the auxiliary interface 15 and the secondary interface 511 according to the control signal.

[0070] On the other hand, the main processor 10 converts the interface for debugging requirements from the auxiliary interface 15 to the UART interface 11. Figure 5CFor example, when the transmission path (e.g., path P5) between the UART interface 11 and the secondary interface 531 is turned on, the switch 32 also turns on another transmission path (e.g., path P4) between the auxiliary interface 15 and the secondary interface 511 according to another control signal from the control interface 13. More specifically, the main processor 10 generates a control signal. The main processor 10 can set the path P5 to be the UART interface 11, the switch 31, the switch 33 and the secondary interface 531 in sequence (step S416). This control signal indicates the aforementioned path P5 or turns on this path P5, and is transmitted to the switches 31 and 33 via the control interfaces 12 and 14. Then, the switches 31 and 33 turn on the path P5 of the UART interface 11 and the secondary interface 531 according to this control signal, so as to receive or transmit the debugging signal. For example, the Bluetooth transceiver circuit (i.e., the secondary circuit 53) transmits the debugging information via the UART interface 11. In addition, the main processor 10 also sets a control signal for interruption to the control interface 14 to interrupt. Figure 5B Path P2 is shown. Assuming that the subcircuit 52 uses the holdover function, it can continue to provide the clock source required to maintain synchronization and receive satellite signals without being affected by path interruption.

[0071] Next, the main processor 10 determines whether to set the auxiliary interface 15 (e.g., USB interface or Ethernet interface) for data transmission request (step S417). If the auxiliary interface 15 is not required for data transmission request, the main processor 10 switches the interface used for debugging request from UART interface 11 to auxiliary interface 15 (step S418) and returns to the second state S2.

[0072] by Figure 5B For example, the main processor 10 may set the auxiliary interface 15 (e.g., a USB interface or an Ethernet interface) for debugging requests. Therefore, the UART interface 11 may be used by the sub-circuit 52 or 53 for data transmission requests. The main processor 10 generates a control signal. Assume that the sub-circuit 52 is a satellite positioning circuit. The main processor 10 may set the path P2 to be the UART interface 11, the switch 31, the switch 33 and the sub-interface 521 in sequence (step S419). This control signal indicates the aforementioned path P2 or turns on this path P2, and is transmitted to the switches 31 and 33 via the control interfaces 12 and 14. Then, the switches 31 and 33 turn on the path P2 of the UART interface 11 and the sub-interface 521 according to this control signal.

[0073] On the other hand, the main processor 10 generates another control signal. Figure 5BFor example, the main processor 10 can set the path P3 to be the auxiliary interface 15, the switch 32 and the secondary interface 511 in sequence (step S419). This control signal indicates the aforementioned path P3 or turns on this path P3, and is transmitted to the switch 32 via the control interface 13. Then, the switch 32 turns on the path P3 of the auxiliary interface 15 and the secondary interface 511 according to the control signal, so as to receive or transmit the debugging signal. In addition, since the path P2 is turned on, the main processor 10 can connect the UART interface 11 to the secondary circuit 52.

[0074] Next, the main processor 10 determines whether to set the auxiliary interface 15 (e.g., USB interface or Ethernet interface) for data transmission request (step S420). If the auxiliary interface 15 is used for data transmission request, the main processor 10 changes the interface used for debugging request from the auxiliary interface 15 to the UART interface 11 and returns to the third state S3 (returning to step S415).

[0075] In one embodiment, the main processor 10 further generates a data transmission enable signal to confirm whether to use the auxiliary interface 15 to perform a data transmission function.

[0076] Depend on Figures 4 to 5C It can be seen that even if the system 1' only provides one UART interface 11 for multiple sub-circuits 51-53, some paths can still be turned on according to the phase and / or required trigger. In addition, the embodiment of the present invention can also switch the interface used by the debugging port.

[0077] Figure 6 is a block diagram of components of a system 1" according to another embodiment of the present invention. Please refer to Figure 6 , compared to Figure 1 The system 1 ″ also includes a switch 34 and sub-circuits 54 , 55 . In addition, the main processor 10 also includes a control interface 13 and an auxiliary interface 15 .

[0078] The functions and implementation methods of the control interface 13 can refer to the aforementioned Figure 1 The description of the control interface 12 is omitted here. The function and implementation of the auxiliary interface 15 can be referred to in the above Figure 2 The description of the auxiliary interface 15 is not repeated here.

[0079] The switch 31 is coupled to the UART interface 11, the control interface 12, the switch 34 and a plurality of sub-circuits 55. The switch 31 includes a first port coupled to the UART interface 11, a control port coupled to the control interface 12 and a plurality of second ports coupled to the sub-circuits 55 respectively.

[0080] The switch 31 is a one-to-many switch. In one embodiment, the switch 31 can be formed by a single circuit device. In another embodiment, the switch 31 can be formed by a combination of multiple switches.

[0081] The switch 34 is coupled to the auxiliary interface 15, the control interface 13, the switch 31 and the sub-circuit 54. In one embodiment, the switch 34 is used to switch between signals via the UART interface 11 and signals via the auxiliary interface 15.

[0082] The switch 34 is a 1 to 2 switch. In one embodiment, the switch 34 can be formed by a single circuit device. In another embodiment, the switch 34 can be formed by a combination of multiple switches.

[0083] The functions and implementation of the sub-circuits 54 and 55 can be referred to above. Figure 1 The description of the sub-circuit 51 is not repeated here.

[0084] The sub-circuit 54 includes a sub-interface 541, and the sub-circuit 55 includes a sub-interface 551. The sub-interface 541 is coupled to the switch 34, and the sub-interface 551 is coupled to the switch 31. The functions and implementations of the sub-interfaces 541 and 551 may refer to the aforementioned Figure 1 or Figure 2 The description of the secondary interface 511 is not repeated here. For example, the secondary interface 541 is a USB or Ethernet interface, and the secondary interface 551 is a UART interface.

[0085] In one embodiment, the system 1" is an extension module board designed for a micro single-board computer (e.g., Raspberry Pi). Multiple sub-circuits 55 are IoT devices and share the UART interface 11 through a switch 31. That is, the transmission path is turned on or off according to the control signal introduced in the aforementioned embodiment. For example, the transmission path between the UART interface 11 and a sub-interface 551 is turned on, or the transmission path between the UART interface 11 and the sub-interface 541 is interrupted. However, the system 1" can still be applied to other computer systems.

[0086] Figure 7 is a flow chart of a method according to an embodiment of the present invention. Figure 7 , providing a main processor (step S710). For example, Figure 1 , Figure 2 , Figure 6 The main processor 10 shown. The main processor includes a UART interface. For example, Figure 1 , Figure 2 , Figure 6 The UART interface 11 shown in FIG. 10 transmits a control signal through the main processor (step S720). For example, via Figure 1 Control interface 12, Figure 2 Control interface 12~13 or Figure 6 The control interfaces 12, 13, and 15 transmit control signals. Provide a switch and a first circuit (step S730). For example, Figure 1 Switch 31, Figure 2 Switches 31 to 33 or Figure 6 Switches 31, 34; Figure 1 Subcircuit 51, Figure 2 Subcircuit 51-53 or Figure 6 The first circuit includes a first interface. For example, Figure 1 The secondary interface 511, Figure 2 Secondary interfaces 511 to 531 or Figure 6 The switch conducts the transmission path between the UART interface and the first interface according to the control signal (step S740). Figure 5A Path P1, Figure 5B Path P2, P3 or Figure 5C Paths P4 and P5.

[0087] about Figure 7 The implementation details of each step in the above-mentioned embodiments and implementation methods are fully described and will not be repeated here.

[0088] In summary, in the system and method for interface management of the embodiment of the present invention, one or more sub-circuits and the UART interface are connected through a switch, and the transmission path of the UART interface to the sub-interface of some sub-circuits is turned on according to the control signal. Thus, a single UART interface can be used to meet the design requirements of sub-circuits that need to connect multiple UART interfaces. In addition, the embodiment of the present invention combines an auxiliary interface, and switches the UART interface and the auxiliary interface for debugging according to requirements and stages.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A system for interface management, characterized in that: include: Main processor, including: Universal Asynchronous Receiver / Transmitter Interface; and Control interface; a switch, coupling the UART interface and the control interface; and The first circuit includes: A first interface is coupled to the switch, wherein The switch conducts a transmission path between the UART interface and the first sub-interface according to a control signal received via the control interface.

2. The system for interface management according to claim 1, wherein In response to the main processor being in an initial stage, generating the control signal for turning on by the main processor, and turning on the transmission path, wherein the transmission path is used for debugging requirements; or In response to the main processor leaving the initial stage, generating the control signal for turning on by the main processor, and turning on the transmission path, wherein the transmission path is used for data transmission requirements; or In response to detecting the data transmission requirement, the control signal for turning on is generated by the main processor, and the transmission path is turned on, wherein the transmission path is used for the error detection requirement.

3. The system for interface management according to claim 2, further comprising: Auxiliary interface, wherein the auxiliary interface is a universal serial bus interface or an Ethernet interface, and is coupled to the switch, wherein In response to the main processor leaving the initialization phase, the auxiliary interface is used for the debugging request; or In response to detecting the data transmission request, the auxiliary interface is used to provide the data transmission request.

4. The system for interface management according to claim 1, wherein In response to the control signal being at a first level, the switch turns on the transmission path; and In response to the control signal being at a second level, the switch interrupts the transmission path.

5. The system for interface management according to claim 1, further comprising: The second circuit includes: The second interface is coupled to another switch, where The another switch conducts another transmission path between the UART interface and the secondary interface according to the control signal received via another control interface of the main processor, and the another switch is coupled to the another control interface.

6. The system for interface management according to claim 1, wherein the switch comprises: A first port coupled to the universal asynchronous receiver-transmitter interface; A control port coupled to the control interface; as well as A plurality of second ports, one of which is coupled to the first circuit, and another of which is coupled to the second circuit.

7. The system for interface management according to any one of claims 1 to 6, wherein the first circuit is a satellite positioning circuit, a Bluetooth transceiver circuit, a USB connector or an Internet of Things device.

8. A method for interface management, characterized in that: include: providing a host processor, wherein the host processor includes a universal asynchronous receiver-transmitter interface; transmitting a control signal via the main processor; Providing a switch and a first subcircuit, wherein the first subcircuit includes a first subinterface; and The switch conducts a transmission path between the UART interface and the first sub-interface according to the control signal.

9. The method for interface management according to claim 8, wherein the step of conducting the transmission path between the UART interface and the first sub-interface according to the control signal comprises: In response to the main processor being in an initial stage, generating the control signal for turning on by the main processor, and turning on the transmission path, wherein the transmission path is used for debugging requirements; or In response to the main processor leaving the initial stage, generating the control signal for turning on by the main processor, and turning on the transmission path, wherein the transmission path is used for data transmission requirements; or In response to detecting the data transmission requirement, the control signal for turning on is generated by the main processor, and the transmission path is turned on, wherein the transmission path is used for the error detection requirement.

10. The method for interface management according to claim 9, wherein the main processor further comprises an auxiliary interface, and the method further comprises: In response to the main processor leaving the initial stage, the auxiliary interface is used for providing the debugging request; or In response to detecting the data transmission request, the auxiliary interface is used to provide the data transmission request.

11. The method for interface management according to claim 9, further comprising: In response to the control signal being at a first level, conducting the transmission path through the switch; as well as In response to the control signal being at a second level, the transmission path is interrupted by the switch.

12. The method for interface management according to claim 9, further comprising: providing a second circuit and another switch, wherein the second circuit includes a second interface; and Another transmission path between the UART interface and the secondary interface is turned on by the another switch according to another control signal via the main processor.

13. A system for interface management, characterized in that: include: Universal Asynchronous Receiver / Transmitter Interface; A switching circuit coupled to the universal asynchronous receiver-transmitter interface; A first subcircuit, coupled to the switching circuit, the first subcircuit comprising a first subinterface; as well as A second circuit is coupled to the switching circuit, and the second circuit includes a second interface, wherein The switching circuit conducts a first transmission path between the UART interface and the first interface, or conducts a second transmission path between the UART interface and the second interface according to a first control signal.

14. The system for interface management according to claim 13, further comprising: An auxiliary interface is coupled to the switching circuit, wherein the auxiliary interface is a non-Universal Asynchronous Receiver / Transmitter interface, wherein When the first transmission path between the UART interface and the first secondary interface is turned on, the switching circuit turns on the transmission path between the auxiliary interface and the second secondary interface according to a second control signal.

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