Data transmission method and system in PCIE (Peripheral Component Interface Express)

Abstract

The invention relates to the technical field of serial interfaces, and discloses a data transmission method and system in PCIE (Peripheral Component Interface Express), and the method comprises the steps: obtaining a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used for indicating the priority of each interface in the PCIE; determining the scheduling time of each interface in the PCIE according to the target arbitration strategy; and for a target interface of the PCIE, if the input data of the target interface is valid within the scheduling time of the target interface, setting an output enable signal corresponding to the target interface so as to directly output data through the target interface or transmit data read from a cache corresponding to the target interface through the target interface. According to the scheme, when multiple interfaces perform receiving work at the same time, the scheduling time of each interface can be arranged according to the priority, and the data is directly output or read from the cache within the scheduling time, so that the utilization rate of the link bandwidth is improved.

Description

Technical Field

[0001] The present application relates to the technical field of serial interface, and in particular to a data transmission method and system in PCIE. Background Art

[0002] The main components of PCIe are RC (Root Complex), SW (Switch), and EP (Endpoint). RC refers to the device that connects the CPU and memory subsystem as well as the PCIe structure. Since it needs to communicate with all devices, it needs to support one or more PCIe Ports.

[0003] At present, the traditional implementation of PCIe controller RC components mostly adopts a design method that uses multiple controllers for independent transmission and reception, and performs aggregation processing on the receiving side. In order to enable the entire RC to operate at the maximum bandwidth, the scheduling strategy adopted needs to be more flexible and the link bandwidth utilization rate needs to be higher, so the arbitration scheduling design on the receiving end is particularly important. Therefore, a data transmission method that improves the link bandwidth utilization rate in PCIE is urgently needed. Summary of the invention

[0004] In view of this, the present application provides a data transmission method and system in PCIE to improve link bandwidth utilization.

[0005] In a first aspect, the present application provides a data transmission method in a PCIE, wherein the PCIE has multiple interfaces, and the method includes:

[0006] Obtaining a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used to indicate the priority of each interface in the PCIE;

[0007] Determine the scheduling time of each interface in the PCIE according to the target arbitration strategy;

[0008] For the target interface of the PCIE, within the scheduling time of the target interface, if the input data of the target interface is valid, the output enable signal corresponding to the target interface is set to directly output data through the target interface, or to transmit data read from the cache corresponding to the target interface through the target interface.

[0009] In a possible implementation, when the target arbitration strategy indicates that the priorities of the interfaces in the PCIE are the same, determining the scheduling time of the interfaces in the PCIE according to the target arbitration strategy includes:

[0010] Each interface in the PCIE is polled according to a specified period, and a specified time after each interface is polled is determined as a scheduling time for each interface in the PCIE.

[0011] In a possible implementation, the method further includes:

[0012] When polling the target interface, if the input data of the target interface is invalid, then poll the next interface of the target interface.

[0013] In a possible implementation, obtaining the target arbitration strategy corresponding to the PCIE includes:

[0014] Obtain the number of physical transmission channels of each interface in the PCIE;

[0015] According to the number of physical transmission channels of each interface, the priority corresponding to each interface is generated to obtain the target arbitration strategy.

[0016] In a second aspect, a data transmission system in a PCIE is provided, the system comprising an arbitration transmission module and a cache receiving module corresponding to each interface;

[0017] The arbitration transmission module is used to obtain a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used to indicate the priority of each interface in the PCIE;

[0018] The arbitration transmission module is further used to determine the scheduling time of each interface in the PCIE according to the target arbitration strategy; for the target interface of the PCIE, within the scheduling time of the target interface, if the input data of the target interface is valid, then set the output enable signal corresponding to the target interface;

[0019] The cache receiving module is used to directly output the data transmitted by the target interface or transmit the data read from the cache corresponding to the target interface through the target interface after the output enable signal corresponding to the target interface is set.

[0020] In a possible implementation, the system further includes a data receiving module;

[0021] The data receiving module is used to convert the data received by the PCIE physical layer into a specified format and output the data to the cache receiving module.

[0022] In a possible implementation, the cache receiving module includes a data transmission unit, a data cache unit, and a data output unit;

[0023] The data transmission unit is used to transmit the data of the corresponding interface to the data output unit or write it into the data cache unit;

[0024] The data cache unit is used to obtain the data written by the data transmission unit or send the data to the data output unit.

[0025] In a possible implementation, the data cache unit is also used to send a cache status signal to the data transmission unit and the data output unit; the cache status signal is used to indicate whether the status of the data cache unit is empty; when the cache status signal indicates that the cache unit is not empty, the cache data is read.

[0026] In a possible implementation, the data transmission unit is further configured to, when receiving an output enable signal of a corresponding interface, determine whether the cache status signal is empty;

[0027] If the cache status signal is empty, the data of the corresponding interface is directly output to the data output unit.

[0028] In a possible implementation manner, the data output unit is further configured to read cache data when the cache status signal indicates that the cache unit is not empty.

[0029] The technical solution provided by this application may have the following beneficial effects:

[0030] The data transmission system in PCIE can first obtain the target arbitration strategy corresponding to PCIE to obtain the priority of each interface in PCIE; then determine the scheduling time of each interface in PCIE according to the priority of each interface in PCIE; after determining the scheduling time of each interface in PCIE, for the target interface, data can be directly output through the target interface within the scheduling time of the target interface, or data read from the cache corresponding to the target interface can be input through the target interface. The above scheme enables multiple interfaces to arrange the scheduling time of each interface according to priority when receiving work at the same time, and directly output data or read data from the cache within the scheduling time, thereby improving the utilization rate of the link bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A data transmission system in PCIE involved in an embodiment of the present application is shown.

[0033] Figure 2A schematic diagram of a module structure and signal transmission involved in an embodiment of the present application is shown.

[0034] Figure 3 A logical block diagram of a data transmission module involved in an embodiment of the present application is shown.

[0035] Figure 4 A logic block diagram of a data output unit involved in an embodiment of the present application is shown.

[0036] Figure 5 A logic block diagram of a data cache unit involved in an embodiment of the present application is shown.

[0037] Figure 6 A fifo read and write timing diagram involved in an embodiment of the present application is shown.

[0038] Figure 7 A diagram showing the time division of each port scheduling for an adaptive configuration involved in an embodiment of the present application is shown.

[0039] Figure 8 A timing diagram of a polling scheduling strategy involved in an embodiment of the present application is shown.

[0040] Fig. 9 A timing diagram of an adaptive configuration scheduling method involved in an embodiment of the present application is shown.

[0041] Fig.10 A data transmission method in PCIE involved in an embodiment of the present application is shown.

[0042] Fig.11 It is a structural schematic diagram of a computer device provided in an optional embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of this application.

[0044] In the description of the embodiments of the present application, the term "corresponding" may indicate a direct or indirect correspondence between two items, or an association relationship between the two items, or a relationship between indication and being indicated, configuration and being configured, and the like.

[0045] At present, the traditional implementation of PCIe controller RC components mostly adopts the design method of using multiple controllers for independent transmission and reception, and performing aggregation processing on the receiving side. In order to enable the entire RC to operate at the maximum bandwidth, the scheduling strategy adopted needs to be more flexible and the link bandwidth utilization rate needs to be higher, so the arbitration scheduling design on the receiving end is particularly important.

[0046] Although the traditional design can realize the basic transmission and reception convergence functions, it has the following disadvantages and shortcomings:

[0047] 1. When multiple port controllers are receiving data at the same time, the link bandwidth utilization is not high;

[0048] 2. The receiving arbitration scheduling strategy is single and has low flexibility.

[0049] Based on the above analysis, please refer to Figure 1 The embodiment of the present application shows a data transmission system in PCIE. The data transmission system includes an arbitration transmission module MAC_RX_ARB and a cache receiving module MAC_RX_BUF corresponding to each interface. The cache receiving module MAC_RX_BUF has MNP, and MNP is the number of ports.

[0050] In the embodiment of the present application, the number of cache receiving modules corresponds to the number of PCIE ports (interfaces), that is, each cache receiving module has a corresponding port, and the cache receiving module is used to receive or cache data of the corresponding port.

[0051] The arbitration transmission module MAC_RX_ARB is used to obtain the target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used to indicate the priority of each interface in the PCIE;

[0052] The arbitration transmission module MAC_RX_ARB is also used to determine the scheduling time of each interface in the PCIE according to the target arbitration strategy; for the target interface of the PCIE, within the scheduling time of the target interface, if the input data of the target interface is valid, then the output enable signal corresponding to the target interface is set;

[0053] The buffer receiving module MAC_RX_BUF is also used to output the data transmitted by the target interface through direct output, or transmit the data read from the buffer corresponding to the target interface through the target interface after the output enable signal corresponding to the target interface is set.

[0054] Optional, such as Figure 1 As shown, the system also includes a data receiving module MAC_RX_PKT; wherein, the number of the data receiving modules MAC_RX_PKT is also MNP, corresponding to the number of PCIE interfaces.

[0055] The data receiving module MAC_RX_PKT is used to convert the data received by the PCIE physical layer into a specified format and output the data to the cache receiving module. Specifically, the data receiving module MAC_RX_PKT can realize the packaging of PIPE received data into TLP and DLLP formats for output, and the data bit width is expanded to (PIPE data bit width * maximum link width, taking pipe data = 32bit, MNL = 8 as an example, the pkt_data bit width is 32*8 = 256bit).

[0056] The cache receiving module MAC_RX_BUF can cache multi-port data transmitted on the receiving path, and the interactive control with the arbitration transmission module MAC_RX_ARB adopts a low-latency design to output the received data of each port to the upstream in order. The unit consists of mac_rx_buf_sel, mac_rx_buf_out and mac_rx_buf_fifo units, among which the mac_rx_buf_sel unit determines whether the current valid received data is directly output or written into mac_rx_buf_fifo, and the mac_rx_buf_out unit selects the current output data source from the mac_rx_buf_sel unit directly or mac_rx_buf_fifo.

[0057] The arbitration transmission module MAC_RX_ARB can provide an internal arbitration mechanism to control the MAC_RX_BUF module of each port to output the received data, output the arbitrated data to the upstream and provide a Port number tag.

[0058] See also Figure 2 , which shows a module structure and signal transmission schematic diagram involved in the embodiment of the present application. Figure 2 As shown, the buffer receiving module MAC_RX_BUF includes a data transmission unit mac_rx_buf_sel, a data buffer unit mac_rx_buf_fifo and a data output unit mac_rx_buf_out;

[0059] First, the function of the data transmission unit mac_rx_buf_sel is introduced:

[0060] The data transmission unit mac_rx_buf_sel is used to transmit the data of the corresponding interface to the data output unit mac_rx_buf_out or write it into the data cache unit mac_rx_buf_fifo.

[0061] Specifically, when the data transmission unit mac_rx_buf_sel receives the output enable signal (pkt_grant=1) of the corresponding interface, it can determine whether the cache status signal is empty; if the cache status signal is empty, the data of the corresponding interface is directly output to the data output unit mac_rx_buf_out.

[0062] Whether the buffer status signal is empty can be determined based on buf_empty. If buf_empty=1, it means that the buffer status signal is empty (and the current fifo status is empty).

[0063] See also Figure 3 , which shows a logical block diagram of a data transmission module involved in an embodiment of the present application. Figure 3 As shown, if pkt_grant=1 (controlled by the MAC_RX_ARB module) and buf_empty=1 (the current fifo state is empty), when the current Port input signal pkt_dv_p is valid (indicating that the input data is valid), the data is directly output by the mac_rx_buf_sel unit (i.e., the data transmission unit mac_rx_buf_sel) to the mac_rx_buf_out unit (data output unit mac_rx_buf_out), without writing to the mac_rx_buf_fifo unit (i.e., the data cache unit mac_rx_buf_fifo), thereby ensuring that the receiving delay is minimized in this scenario.

[0064] In other cases, when pkt_dv_p is valid, data is written to the mac_rx_buf_fifo unit by the mac_rx_buf_sel unit.

[0065] Secondly, the function of the data output unit mac_rx_buf_out is introduced:

[0066] In addition to receiving the through data of the above-mentioned data transmission unit mac_rx_buf_sel, the data output unit mac_rx_buf_out can also determine whether the cache status signal is empty (that is, determine the value of buf_empty) when receiving the output enable signal of the corresponding interface (pkt_grant=1); if buf_empty=0, that is, the cache status signal is not empty, then the status of the cache unit fifo is not empty, and the data output unit mac_rx_buf_out reads the cached data in the cache unit fifo.

[0067] See also Figure 4 , which shows a logic block diagram of a data output unit involved in an embodiment of the present application. Figure 4As shown, for the mac_rx_buf_out unit:

[0068] If pkt_grant=1 and buf_empty=1, the data of mac_rx_buf_sel unit is directly output;

[0069] If pkt_grant=1 and buf_empty=0, after reading the data of the mac_rx_buf_fifo unit, wait for the next arbitration output;

[0070] If buf_empty=0, pre-fetch mac_rx_buf_fifo data once and wait for the next arbitration output;

[0071] If pkt_grant=0, the corresponding data when pkt_rdy is valid is output and maintained.

[0072] Furthermore, the function of the data cache unit mac_rx_buf_fifo is introduced:

[0073] The data cache unit mac_rx_buf_fifo is used to obtain the written data of the data transmission unit or send the data to the data output unit mac_rx_buf_out.

[0074] Specifically, the data cache unit mac_rx_buf_fifo is also used to send a cache status signal buf_empty to the data transmission unit mac_rx_buf_sel and the data output unit mac_rx_buf_out; the cache status signal buf_empty is used to indicate whether the state of the data cache unit is empty; when the cache status signal buf_empty indicates that the cache unit is not empty, the cache data is read.

[0075] See also Figure 5 , which shows a logic block diagram of a data cache unit involved in an embodiment of the present application. Figure 5 As shown, for the mac_rx_buf_fifo unit:

[0076] If pkt_grant=1 and buf_empty=0, a read fifo operation is performed and pkt_data is obtained in the next cycle;

[0077] If pkt_grant=0 and buf_empty=0, a pre-read fifo operation is performed to obtain pkt_data in the next cycle;

[0078] If pkt_grant=1 and buf_empty=1 of the current cycle, no operation is performed;

[0079] If buf_empty=0, or (buf_empty=1 and pkt_dv=1), pkt_rdy is set valid, indicating that pkt_data is ready to be output.

[0080] In the embodiment of the present application, the cache unit fifo in the MAC_RX_BUF module (i.e., the cache receiving module) of the present application uses pkt_dv_p* as a write enable, concatenates the received data of the current port and caches it, uses the pkt_grant signal corresponding to the current port controlled by the MAC_RX_ARB module as the fifo read enable, sets the read data and the pkt_dv_p* signal, and outputs them to the MAC_RX_ARB module together. The corresponding fifo read and write timing design is as follows: Figure 6 As shown, the transmission delay is minimized.

[0081] Figure 6 The timing diagram is as follows:

[0082] Time T1: The current port receives the upstream data 1st_data and writes it into the fifo. In the next cycle, the fifoempty flag is set to non-empty, and the pre-read data operation is performed. The pkt_rdy_p bit is set to indicate to the arbitration module that the data is ready and waiting for arbitration.

[0083] At T2: fifo puts 1st_data on the data line;

[0084] Time T3: The current port receives the upstream data 2nd_data and writes it into the fifo operation. The pkt_rdy_p is continuously set to indicate that the data is ready and continues to wait for arbitration.

[0085] Time T4: The current port gets the pkt_grant_p from the arbitration module, and the arbitration module samples the 1st_data on the data line. At this time, the fifo is not empty, and the read operation is performed;

[0086] At T5: fifo puts 2nd_data on the data line;

[0087] Time T6: The current port gets the pkt_grant_p of the arbitration module, and the arbitration module samples the 2nd_data on the data line. At this time, the fifo is not empty, and the read operation is performed. The read pointer jumps in the next cycle;

[0088] Time T7: The read pointer jumps to the write pointer position. At this time, the fifo is empty and the data line contains invalid data.

[0089] Furthermore, in the embodiment of the present application, since there are multiple ports in the PCIE, a polling scheduling method involving the ports is required.

[0090] In a possible implementation, the priority of each port is the same. In this case, each interface in the PCIE may be polled according to a specified period, and a specified time after polling each interface is determined as the scheduling time of each interface in the PCIE.

[0091] If the input data of the target interface is invalid when polling the target interface, the next interface of the target interface is polled;

[0092] Specifically, the scheduling pointer is incremented by one after the currently pointed Port (interface) is scheduled, that is, it points to the next Port: first, wait for the corresponding pkt_rdy of any Port to be valid, then record the current Port number (if multiple pkt_rdy are valid, select the minimum value in the order of Port0 to 7) as the scheduling start, and poll the corresponding pkt_rdy of the remaining Ports in ascending order; then output the pkt_data of the selected Port in the current cycle, and set the pkt_grant signal of this Port for 1 cycle, and the pkt_grant signals of the remaining Ports remain low (the default pkt_grant is low level), the selected Port will read the fifo data once (read enable is valid, and the data is output in the next cycle), and can be directly output when it is selected next time; ③ Repeat the polling process MNP (number of Ports) times until all Ports are completed, and wait for the next start.

[0093] In another possible implementation, the target arbitration strategy corresponding to the PCIE can also be set to adaptively configure the weight according to the actual Lane width. In this case, the number of physical transmission channels of each interface in the PCIE can be obtained; according to the number of physical transmission channels of each interface, the priority corresponding to each interface is generated to obtain the target arbitration strategy.

[0094] Specifically, the link width of each port is obtained according to the Bifurcation configuration, and then the hardware adaptively determines the scheduling time allocation, initializes the current polling start point and sequence table, and polls the corresponding pkt_rdy of each port according to the sequence table. The implementation method is as follows:

[0095] During the polling period, if pkt_rdy is detected to be valid, the pkt_data of the corresponding port is output, and the pkt_grant signal of this port is set for 1 cycle (as a fifo pre-read enable), and the pkt_grant signals of other ports remain low;

[0096] If the port data to be selected is not ready, skip it and check the next port data. The number of times it is scheduled in the entire cycle cannot exceed its weight setting value, otherwise the weight initialization operation is performed and then polling is performed;

[0097] Polling continues according to the assigned weights until reconfigured.

[0098] For the above-mentioned adaptive configuration weight method according to the actual Lane width, the embodiment of the present application can generate an adaptive configuration according to the link width of each Port, that is, the scheduling weight is determined according to the Lane width of each Port configured by Bifurcation, and the larger the Lane width, the higher the priority of the Port scheduling, as shown in Table 1 below. This scheduling strategy that uses the actual Lane width to adaptively generate the configuration can usually achieve the maximum bandwidth utilization. The reason is that the scheduling process can ensure that the number of times each Port is scheduled in a round of scheduling cycle is proportional to the actual Lane width, that is, the larger the Lane width, the more frequently it is scheduled. Taking the PIPE data bit width of 32bit as an example, the upstream module will output to the MAC_RX_BUF module only after the current Port is full of MNL*32bit data. Therefore, even if the current Port is full of MNL*32bit data and is not scheduled, resulting in the data being cached in MAC_RX_BUF, but before the data is full of MNL*32bit again in the entire scheduling cycle, this Port will definitely be scheduled, thereby ensuring that MAC_RX_BUF does not overflow during the entire receiving operation. In this way, the received data of all Lanes can be output without packet loss during the entire scheduling cycle, achieving maximum bandwidth utilization.

[0099] Table 1. Schedule allocation table using actual lane width adaptive generation configuration

[0100] Maximum supported lane width in a port Weight 16 16 8 8 4 4 2 2 1 1

[0101] The above weighted scheduling method based on the actual Lane width adaptive configuration is the default working mode of this application. Taking MNL=8 as an example, the adaptive configuration of each port scheduling time is divided as follows: Figure 7 As shown:

[0102] Bifurcation column: enumerates all the combinations of multiple ports multiplexing 8 lanes;

[0103] Cycle column: divided into 0~7 cycles, each cycle selects the current port data, if the current port data does not apply for arbitration, then query the next port. If the number of times a port is scheduled has reached its weight setting value within the entire 8 cycle period, all port weights are initialized, and then the polling operation is restarted.

[0104] In another possible implementation, the weight (or priority) of each interface in the embodiment of the present application can be dynamically controlled according to the upstream hardware, which is similar to the above-mentioned method of adaptively configuring weights according to the actual Lane width, but its weight distribution is changed from adaptive generation to dynamic control distribution by upstream hardware. The scheme shown in the embodiment of the present application supports dynamic weight control of upstream hardware, and the advantage is that the upstream hardware can dynamically adjust and distribute the scheduling weights of this design according to the actual business data volume to achieve the best system performance.

[0105] In another possible implementation, the weight (or priority) of each interface in the embodiment of the present application can also be customized according to the software. This method is similar to the above-mentioned method of adaptively configuring the weight according to the actual Lane width, but supports the user to customize the weight of each Port, that is, the software rewrites the current scheduling weight configuration, providing a more flexible usage scenario.

[0106] In the embodiment of the present application, the MAC_RX_ARB unit selects the Port polling scheduling strategy by taking 4 Ports and 8 Lanes as an example. Figure 8 , which shows a timing diagram of a polling scheduling strategy involved in an embodiment of the present application. Figure 8 As shown:

[0107] At T1: The pkt_data data of the MAC_RX_BUF module corresponding to Port0~3 is ready, and the data (pkt_data_p*) is placed on the output interface, and the respective pkt_rdy_p* is set. The MAC_RX_ARB module adopts the Port polling arbitration strategy, selects the output Port0 data (pkt_data_p0.1st_data) and sets the corresponding pkt_grant_p0, keeping the other pkt_grants low.

[0108] At T2: the MAC_RX_ARB module checks that the pkt_rdy_p1 corresponding to Port1 is set according to the Port polling arbitration strategy, then outputs the data pkt_data_p1.1st_data and sets the corresponding pkt_grant_p1.

[0109] Time T3: Similar to T2, check that the pkt_rdy_p2 corresponding to Port2 is set, then output the data pkt_data_p2.1st_data, and set the corresponding pkt_grant_p2.

[0110] Time T4: Similar to T3, check that the corresponding pkt_rdy_p3 of Port3 is set, then output the data pkt_data_p3.1st_data, and set the corresponding pkt_grant_p3.

[0111] At T5: In the current cycle, only the pkt data corresponding to Port1 and Port2 are ready. According to the Port polling arbitration strategy, the data (blue) pkt_data_p1.1st_data is output and the corresponding pkt_grant_p1 is set.

[0112] At T6: the pkt_data_p3 data corresponding to Port3 of the current cycle is also ready, but according to the Port polling arbitration strategy, the data (blue) pkt_data_p2.1st_data is output and the corresponding pkt_grant_p2 is set.

[0113] At T7: According to the Port polling arbitration strategy, it is checked that the corresponding pkt_rdy_p3 of Port3 is valid, so the data (blue) pkt_data_p3.1st_data is output and the corresponding pkt_grant_p3 is set.

[0114] At T8: The pkt_data_p0 data corresponding to the current cycle Port0 is ready, so the data (blue) pkt_data_p0.1st_data is output and the corresponding pkt_grant_p0 is set.

[0115] The MAC_RX_ARB unit of this application uses 4 ports and 8 lanes working in 1x4, 1x2, and 2x1 modes, and selects the scheduling method according to the actual Lane width adaptive configuration as an example. The scheduling strategy of the aforementioned Bifurcation number 4 is selected, and Port0: x4, Port1: x2, Port2: x1, Port3: x1 is set. Please refer to Fig. 9 , which shows a timing diagram of an adaptive configuration scheduling method involved in an embodiment of the present application. Fig. 9 As shown:

[0116] At T1: The pkt data of the MAC_RX_BUF module corresponding to Port0~3 is ready, and the data (pkt_data_p*) is placed on the output interface, and the respective pkt_rdy_p* is set. The MAC_RX_ARB module adopts the arbitration strategy according to the actual Lane width scheduling, selects the output data of Port0 (pkt_data_p0.1st_data) as shown in the above table, and sets the corresponding pkt_grant_p0, keeping the other pkt_grant low. If the fifo corresponding to Port0 is not empty, it will be pre-read once, so that pkt_data_p0 is updated to the new data in the next cycle (such as pkt_data_p0.2nd_data at T2 in the left figure).

[0117] At T2: According to the current scheduling strategy, check that pkt_rdy_p1 is valid, output data (pkt_data_p1.1st_data) and set the corresponding pkt_grant_p1, and keep the remaining pkt_grant low.

[0118] Time T3: According to the current scheduling strategy, check that pkt_rdy_p0 is valid, output data (pkt_data_p0.2nd_data) and set the corresponding pkt_grant_p0, and keep the remaining pkt_grant low.

[0119] Time T4: According to the current scheduling strategy, check that pkt_rdy_p2 is valid, output data (pkt_data_p2.1st_data) and set the corresponding pkt_grant_p2, and keep the remaining pkt_grant low.

[0120] Time T5: According to the current scheduling strategy, check that pkt_rdy_p0 is valid, output data (pkt_data_p0.3rd_data) and set the corresponding pkt_grant_p0, and keep the remaining pkt_grant low.

[0121] Time T6: According to the current scheduling strategy, check that pkt_rdy_p1 is valid, output data (pkt_data_p1.2nd_data) and set the corresponding pkt_grant_p1, and keep the remaining pkt_grant low.

[0122] Time T7: According to the current scheduling strategy, check that pkt_rdy_p0 is valid, output data (pkt_data_p0.4th_data) and set the corresponding pkt_grant_p0, and keep the remaining pkt_grants low.

[0123] At T8: According to the current scheduling strategy, check that pkt_rdy_p3 is valid, output data (pkt_data_p3.1st_data) and set the corresponding pkt_grant_p3, and keep the remaining pkt_grant low.

[0124] The present application provides a PCIe MAC layer multi-port receive arbitration scheduling design method, which solves the problem that the link bandwidth utilization is not high and the receive arbitration scheduling strategy is not flexible when the traditional multi-port controller design is performing simultaneous receiving work. The application can maximize the link bandwidth utilization and can also adapt to a variety of scheduling strategy application scenarios.

[0125] Advantages of using this application design:

[0126] 1) The bandwidth utilization of the multi-port receiving link reaches the theoretical upper limit of all lane widths;

[0127] 2) The multi-port receive buffer and arbitration logic interaction adopts a low-latency design, which helps improve the overall receive path performance;

[0128] 3) Supports four arbitration strategies: port polling, adaptive configuration of scheduling weight according to the current actual Lane width, dynamic control weight of upstream hardware, and software customized weight, which can be flexibly configured to meet various usage scenarios;

[0129] 4) The number of ports and lanes is parameterized to support a variety of Bifurcation configuration combination scenarios;

[0130] 5) The design code has strong maintainability and scalability;

[0131] 6) The internal fifo cache implements adaptive minimization design according to the scheduling weight allocation to reduce the waste of design resources;

[0132] 7) Standard customized design effectively reduces the difficulty of verification coverage convergence and shortens product development time.

[0133] In summary, the data transmission system in PCIE can first obtain the target arbitration strategy corresponding to PCIE to obtain the priority of each interface in PCIE; then determine the scheduling time of each interface in PCIE according to the priority of each interface in PCIE; after determining the scheduling time of each interface in PCIE, for the target interface, data can be directly output through the target interface within the scheduling time of the target interface, or data read from the cache corresponding to the target interface can be input through the target interface. The above scheme enables multiple interfaces to arrange the scheduling time of each interface according to priority when receiving work at the same time, and directly output data or read data from the cache within the scheduling time, thereby improving the utilization rate of the link bandwidth.

[0134] See also Fig.10 , which shows a data transmission method in a PCIE involved in an embodiment of the present application, the method comprises: Figure 1 The data transmission system in the PCIE shown is executed, and the method includes:

[0135] Step 1001, obtaining a target arbitration policy corresponding to the PCIE; the target arbitration policy is used to indicate the priority of each interface in the PCIE.

[0136] Step 1002, determining the scheduling time of each interface in the PCIE according to the target arbitration strategy;

[0137] Step 1003, for the target interface of the PCIE, within the scheduling time of the target interface, if the input data of the target interface is valid, set the output enable signal corresponding to the target interface to directly output data through the target interface, or transmit data read from the cache corresponding to the target interface through the target interface.

[0138] The specific execution method of the above steps is as follows Figure 1 The logic in the embodiment corresponding to the PCIE data transmission system shown is the same and will not be repeated here.

[0139] In summary, the data transmission system in PCIE can first obtain the target arbitration strategy corresponding to PCIE to obtain the priority of each interface in PCIE; then determine the scheduling time of each interface in PCIE according to the priority of each interface in PCIE; after determining the scheduling time of each interface in PCIE, for the target interface, data can be directly output through the target interface within the scheduling time of the target interface, or data read from the cache corresponding to the target interface can be input through the target interface. The above scheme enables multiple interfaces to arrange the scheduling time of each interface according to priority when receiving work at the same time, and directly output data or read data from the cache within the scheduling time, thereby improving the utilization rate of the link bandwidth.

[0140] The data transmission system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0141] The present application also provides a computer device, which can implement PCIE-based data transmission through the system shown in the present application. Fig.11 , Fig.11 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present application, such as Fig.11 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphic information in a graphical user interface on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.11 A processor 10 is taken as an example.

[0142] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0143] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0144] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0145] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0146] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0147] The embodiment of the present application also provides a computer-readable storage medium. The above method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or is implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0148] Part of the present application may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present application through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes but is not limited to source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0149] Although the embodiments of the present application are described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A data transmission method in PCIE, characterized in that: The PCIE has multiple interfaces, and the method includes: Obtaining a target arbitration strategy corresponding to the PCIE; the target arbitration strategy is used to indicate the priority of each interface in the PCIE; Determine the scheduling time of each interface in the PCIE according to the target arbitration strategy; For the target interface of the PCIE, within the scheduling time of the target interface, if the input data of the target interface is valid, the output enable signal corresponding to the target interface is set to directly output data through the target interface, or to transmit data read from the cache corresponding to the target interface through the target interface.

2. The data transmission method according to claim 1, characterized in that: When the target arbitration strategy indicates that the priorities of the interfaces in the PCIE are the same, determining the scheduling time of the interfaces in the PCIE according to the target arbitration strategy includes: Each interface in the PCIE is polled according to a specified period, and a specified time after each interface is polled is determined as a scheduling time for each interface in the PCIE.

3. The data transmission method according to claim 2, characterized in that: The method further comprises: When polling the target interface, if the input data of the target interface is invalid, then poll the next interface of the target interface.

4. The data transmission method according to claim 1, characterized in that: The obtaining of the target arbitration strategy corresponding to the PCIE includes: Obtain the number of physical transmission channels of each interface in the PCIE; According to the number of physical transmission channels of each interface, the priority corresponding to each interface is generated to obtain the target arbitration strategy.

5. A data transmission system in PCIE, characterized in that: The system includes an arbitration transmission module and a cache receiving module corresponding to each interface; The arbitration transmission module is used to obtain the target arbitration strategy corresponding to the PCIE; The target arbitration strategy is used to indicate the priority of each interface in the PCIE; The arbitration transmission module is further used to determine the scheduling time of each interface in the PCIE according to the target arbitration strategy; For the target interface of the PCIE, within the scheduling time of the target interface, if the input data of the target interface is valid, setting the output enable signal corresponding to the target interface; The cache receiving module is used to directly output the data transmitted by the target interface or transmit the data read from the cache corresponding to the target interface through the target interface after the output enable signal corresponding to the target interface is set.

6. The data transmission system according to claim 5, characterized in that: The system also includes a data receiving module; The data receiving module is used to convert the data received by the PCIE physical layer into a specified format and output the data to the cache receiving module.

7. The data transmission system according to claim 6, characterized in that: The cache receiving module includes a data transmission unit, a data cache unit and a data output unit; The data transmission unit is used to transmit the data of the corresponding interface to the data output unit or write it into the data cache unit; The data cache unit is used to obtain the data written by the data transmission unit or send the data to the data output unit.

8. The data transmission system according to claim 7, characterized in that: The data cache unit is also used to send a cache status signal to the data transmission unit and the data output unit; the cache status signal is used to indicate whether the state of the data cache unit is empty; when the cache status signal indicates that the cache unit is not empty, the cache data is read.

9. The data transmission system according to claim 8, characterized in that: The data transmission unit is further used to determine whether the cache status signal is empty when receiving an output enable signal of the corresponding interface; If the cache status signal is empty, the data of the corresponding interface is directly output to the data output unit.

10. The data transmission system according to claim 8, characterized in that: The data output unit is further configured to read cache data when the cache status signal indicates that the cache unit is not empty.

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