Serial port debugging system, device and method
By using the complex programmable logic chip CPLD in the mainframe to realize serial port switching, the durability and limitations of serial port multiplexing design in the existing technology are solved, and flexible switching and efficient debugging of the serial port are realized.
Patent Information
- Application Number
- CN202411973713.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-04-25
AI Technical Summary
The prior art serial port multiplexing design in mainframes has problems such as low durability, dependence on CPU systems, and disconnection of debugging interfaces.
The complex programmable logic chip CPLD is used to replace the serial switch chip, and is deployed on the master and slave disks. The received serial port signal is automatically controlled to connect or close the channel, and the flexible switch of the serial port is realized.
It improves the flexibility and durability of serial port switching, avoids the limitations of relying on the CPU system, can debug when the system is not started, and enhances the visibility of power-on information on the board.
Smart Images
Figure CN119883982A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication equipment and serial port debugging, and in particular to a serial port debugging system, equipment and method. Background Art
[0002] In the communication network, the commonly used communication equipment cards need to have a debugging serial port for debugging and configuration of equipment installation. However, in large-scale chassis applications, there are many cards with dense ports, and each card needs to use a serial port to implement certain configurations. If each card has a serial port interface on the panel, it will waste a lot of space.
[0003] Existing designs usually use backplane switching chips to achieve switching, which is similar to a serial port multiplexer, but has obvious defects. First, adding a serial port switching chip to the backplane greatly reduces the durability of the backplane. Once the chip is damaged or fails, the entire frame cannot be used normally; second, when the main control panel debugs other boards, it relies on the CPU of the main control panel to forward signals and control switching. The system needs to be started before debugging, and the information when the board is powered on cannot be viewed, which has limitations; in addition, the switching action under the dual-main control system depends on the CPU of the main control panel to control the switching chip. When the debug port is switched to other boards on the backplane, the debug port is disconnected from the CPU of the main control panel, and the debugger can no longer send commands to the CPU of the main control panel through the debug interface to switch back. Summary of the invention
[0004] The embodiment of the present invention provides a serial port debugging system, device and method, which adopts CPLD (Complex Programming Logic Device) to replace the serial port switching chip in the prior art and is deployed in the master control disk and the slave disk. The CPLD controls the connection or closing of the corresponding channel through the received serial port signal, automatically determines to switch, does not need to rely on the traditional CPU system, and can flexibly switch the serial port to the board that needs to be configured.
[0005] In a first aspect, an embodiment of the present application provides a serial port debugging system, the system comprising a master control disk, at least one slave disk, and a backplane channel respectively connecting the master control disk and each slave disk, wherein:
[0006] The main control disk includes a first CPLD and a first CPU, wherein the first CPLD is connected to the debugging interface and the backplane channel respectively, and is used to connect the first channel between the debugging interface and the first CPU or the second channel between the debugging interface and the backplane channel;
[0007] Each slave disk includes a second CPLD and a second CPU, wherein the second CPLD is used to connect or close a third channel between the backplane channel and the second CPU;
[0008] The first channel is used for debugging the first CPU through the debugging interface, and the connected second channel and third channel are used for debugging the second CPU of the slave disk to be debugged through the debugging interface.
[0009] In some possible embodiments, the first CPLD is further used for:
[0010] receiving a serial port signal from the debugging interface, and when determining that the serial port signal carries a first character string corresponding to the main control disk, connecting a first channel between the debugging interface and the first CPU, and closing a second channel between the debugging interface and the backplane channel;
[0011] When it is determined that the serial port signal carries a second character string corresponding to the slave disk to be debugged, the first channel between the debugging interface and the first CPU is closed, and the second channel between the debugging interface and the backplane channel is connected.
[0012] In some possible embodiments, the second CPLD is further used for:
[0013] When receiving a serial port signal through a backplane channel and determining that a second character string carried by the serial port signal corresponds to the slave disk where the slave disk is located, connecting the backplane channel to a third channel between the second CPU;
[0014] When it is determined that the second character string carried by the serial port signal does not correspond to the slave disk where the slave disk is located, the third channel between the backplane channel and the second CPU is closed.
[0015] In some possible embodiments, the main control disk includes an active main control disk and a standby main control disk, wherein:
[0016] When the first CPLD of any main control disk receives a serial port signal from the debugging interface, it is used to connect the first channel between the debugging interface and the first CPU or to connect the second channel between the debugging interface and the backplane channel. The third CPLD of the other main control disk is used to connect or close the fourth channel between the backplane channel and the third CPU according to the serial port signal received from the backplane channel.
[0017] In some possible embodiments, the first CPLD connects the first channel between the debug interface and the first CPU, and connects the second channel between the debug interface and the backplane channel in a default state; the second CPLD closes the third channel between the backplane channel and the second CPU in a default state.
[0018] In a second aspect, an embodiment of the present application provides a serial port debugging device, the serial port debugging device serving as a main control disk, comprising:
[0019] A first complex programmable logic chip CPLD and a first CPU, wherein the first CPLD is connected to a debugging interface and a backplane channel respectively, wherein the backplane channel is connected to each slave disk;
[0020] The first CPLD is used to connect the first channel between the debugging interface and the first CPU, or to connect the second channel between the debugging interface and the backplane channel;
[0021] The first channel is used for debugging the first CPU through the debugging interface; the second channel is connected to the third channel for debugging the second CPU of the slave disk to be debugged, and the third channel is the channel between the second CPLD of the slave disk to be debugged and the backplane channel.
[0022] In some possible embodiments, the second channel is connected to the fourth channel for debugging the third CPU of another main control disk, and the fourth channel is a channel between the third CPLD of another main control disk to be debugged and the backplane channel.
[0023] In a third aspect, an embodiment of the present application further provides a serial port debugging device, the serial port debugging device serving as a slave disk, comprising:
[0024] A second CPLD and a second CPU, wherein the second CPLD is connected to a backplane channel;
[0025] The second CPLD is used to connect the third channel between the backplane channel and the second CPU when the slave disk where the second CPLD is located is the slave disk to be debugged; otherwise, the third channel between the backplane channel and the second CPU is closed, and the backplane channel is connected to the debugging interface through the second channel;
[0026] The connected second channel and third channel are used for debugging the second CPU of the slave disk to be debugged by the debugging interface.
[0027] In a fourth aspect, the embodiment of the present application further proposes a serial port debugging method based on the system described in the first aspect, comprising:
[0028] receiving a serial port signal from a debugging interface via a first CPLD of a main control disk;
[0029] Connecting the first channel between the debugging interface and the first CPU of the main control disk through the first CPLD according to the serial port signal, and debugging the first CPU through the first channel; or
[0030] The second channel between the debugging interface and the backplane channel is connected through the first CPLD according to the serial port signal, the third channel between the backplane channel and the second CPU is connected through the second CPLD of the slave disk to be debugged according to the serial port signal, the third channel between the backplane channel and the second CPU is closed through the second CPLD of the slave disk not to be debugged according to the serial port signal, and the second CPU to be debugged is debugged through the connected second and third channels.
[0031] In some possible embodiments, the method further includes:
[0032] The third CPLD of another main control disk connects the fourth channel between the backplane channel and the third CPU according to the serial port signal received from the backplane channel when the third CPLD is the main control disk to be debugged; otherwise, the fourth channel between the backplane channel and the third CPU is closed;
[0033] The third CPU of another main control disk is debugged through the connected second channel and fourth channel.
[0034] A serial port debugging system, device and method provided in an embodiment of the present invention adopts a complex programmable logic chip CPLD to realize the switching function of the serial port, is deployed in a master disk and a slave disk, controls the connection or closing of the corresponding channel through the received serial port signal, automatically judges and switches, does not need to rely on a traditional CPU system, and can flexibly switch the serial port to a board that needs to be configured.
[0035] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures specifically pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0037] Figure 1 This is a schematic diagram of a large machine frame in an embodiment of the present application;
[0038] Figure 2 This is a working schematic diagram of a backplane switching chip in an embodiment of the present application;
[0039] Figure 3 This is a schematic diagram of the structure of a serial port debugging system in an embodiment of the present application;
[0040] Figure 4a This is a schematic diagram of the internal structure of a main control disk in an embodiment of the present application;
[0041] Figure 4b This is another schematic diagram of the internal structure of the main control disk in the embodiment of the present application;
[0042] Figure 5 This is a schematic diagram of the internal structure of a slave disk in an embodiment of the present application;
[0043] Figure 6 This is a schematic diagram of the internal structure of the master disk and the slave disk in a default state in an embodiment of the present application;
[0044] Figure 7 This is a schematic diagram of the working logic of the main control disk processing serial port signals in an embodiment of the present application;
[0045] Figure 8 This is a working logic diagram of a slave disk corresponding to slot 1 processing a serial port signal in an embodiment of the present application;
[0046] Fig. 9 This is a working logic diagram of a slave disk corresponding to slot 2 processing a serial port signal in an embodiment of the present application;
[0047] Fig.10 This is a flow chart of serial port debugging of a main control disk in an embodiment of the present application;
[0048] Fig.11 This is a flow chart of serial port debugging of a slave disk in an embodiment of the present application;
[0049] Fig.12 This is a flow chart of serial port debugging of a spare main control disk in an embodiment of the present application. DETAILED DESCRIPTION
[0050] To further illustrate the technical solution provided by the embodiments of the present application, a detailed description is given below in conjunction with the accompanying drawings and specific implementation methods.
[0051] In large-frame applications, such as Figure 1 As shown in the figure, the boards have many ports and each board needs to use the serial port to implement certain configurations. The existing design usually uses the backplane switching chip to achieve switching, such as Figure 2As shown in the figure, it is similar to a serial port multiplexer, but has obvious defects: first, adding a serial port switching chip to the backplane greatly reduces the durability of the backplane. Once the chip is damaged or fails, the entire frame cannot be used normally; second, when the main control panel debugs other boards, it relies on the CPU of the main control panel to do signal forwarding and switching control. The system needs to be started before debugging, and the information when the board is powered on and started cannot be viewed, which has limitations; in addition, the switching action in the dual-main control system shown in the figure depends on the CPU of the main control panel to control the switching chip. When the debugging interface is switched to other boards connected to the backplane, the debugging interface is disconnected from the CPU of the main control panel, and the debugging personnel can no longer send commands to the CPU of the main control panel through the debugging interface to switch back.
[0052] In view of the fact that the above-mentioned existing serial port switching chips are not durable, have limitations, and rely on the CPU system, the embodiments of the present application propose a serial port debugging system, device and method, which implements the switching function of the serial port by adopting a complex programmable logic chip CPLD. It can automatically determine whether to switch, does not need to rely on the traditional CPU system, and flexibly switches the serial port to the board that needs to be configured.
[0053] In the first aspect, the present application embodiment provides a serial port debugging system, such as Figure 3 As shown, the system includes a master control disk, at least one slave disk, and backplane channels respectively connecting the master control disk and each slave disk, wherein:
[0054] The main control disk includes a first CPLD and a first CPU, wherein the first CPLD is connected to the debugging interface and the backplane channel respectively, and is used to connect the first channel between the debugging interface and the first CPU or to connect the second channel between the debugging interface and the backplane channel, such as Figure 4a and Figure 4b shown.
[0055] The slave disks are as follows: Figure 5 As shown, it includes a second CPLD and a second CPU, and the second CPLD is used to connect or close the third channel between the backplane channel and the second CPU.
[0056] The first channel is used for debugging the first CPU through the debugging interface, and the connected second channel and third channel are used for debugging the second CPU of the slave disk to be debugged through the debugging interface.
[0057] In an embodiment of the present application, the UART signal from the debug interface, that is, the serial port signal, needs to first pass through the CPLD and then be forwarded by the CPLD. By setting the working logic of the first CPLD of the master control disk, the connection and closing states of the channel between the debug interface and the first CPU / backplane channel of the master control disk are controlled, which is equivalent to realizing the functions of two channel switches through the first CPLD of the master control disk. By setting the working logic of the second CPLD of the slave disk, the connection and closing states of the channel between the backplane channel and the second CPU of the slave disk are controlled, which is equivalent to realizing the function of a channel switch. The embodiment of the present application realizes automatic control of the channel through the CPLD, which overcomes the problem in the prior art that the channel switching needs to rely on the CPU of the master control disk.
[0058] When performing serial port debugging, the first CPLD in the main control disk is used to receive a serial port signal from the debugging interface, parse the serial port signal to obtain a corresponding character string, and connect the corresponding channel based on the pre-set logic in the first CPLD, wherein the first CPLD is specifically used to:
[0059] When it is determined that the serial port signal carries a first character string corresponding to the main control disk, connecting the first channel between the debugging interface and the first CPU, and closing the second channel between the debugging interface and the backplane channel;
[0060] When it is determined that the serial port signal carries a second character string corresponding to the slave disk to be debugged, the first channel between the debugging interface and the first CPU is closed, and the second channel between the debugging interface and the backplane channel is connected.
[0061] In some possible embodiments, before debugging the device, the corresponding relationship between the master disk / slave disk to be debugged and the character string is stored as logic in the first CPLD, and the first CPLD will automatically switch the direction of serial port data forwarding according to the character string. In actual debugging, adjustments can be made according to the character string carried by the sent serial port signal, and the corresponding channel can be connected according to the logic stored in the first CPLD before the system is powered on but not started, and the information of the corresponding board can be directly viewed through the debugging interface, which is more flexible.
[0062] In an embodiment of the present application, when the first channel / the second channel is connected, the two correspondingly connected devices can transmit operation instructions through the channel, and when the device to be debugged is switched, the first CPLD can automatically switch the channel in time according to the character string in the new serial port signal without relying on the CPU system of the main control disk.
[0063] The backplane channel described in the embodiment of the present application is used to forward the received signal from any direction to all devices except the receiving device. When the second channel is connected, the backplane channel is used to receive the serial port signal / operation instruction from the debug interface and forward the serial port signal / operation instruction to all slave disks.
[0064] The second CPLD in each slave disk is used to receive a serial port signal from the backplane channel, parse the serial port signal to obtain a corresponding character string, and connect or close a third channel between the backplane channel and the second CPU based on a pre-set logic in the second CPLD, wherein the second CPLD is specifically used to:
[0065] When it is determined that the second character string carried by the serial port signal corresponds to the slave disk where the slave disk is located, connecting the backplane channel to the third channel between the second CPU;
[0066] When it is determined that the second character string carried by the serial port signal does not correspond to the slave disk where the slave disk is located, the third channel between the backplane channel and the second CPU is closed.
[0067] In some possible embodiments, the first CPLD connects the first channel between the debug interface and the first CPU and connects the second channel between the debug interface and the backplane channel by default, and the second CPLD closes the third channel between the backplane channel and the second CPU by default. Figure 6 As shown. In the default state, after the serial port signal from the debugging interface reaches the first CPLD, the received serial port signal is sent to the first CPU and the backplane channel of the main control disk by default. Even if the first CPLD of the main control disk forwards the serial port signal in two directions, the second CPLD receives the serial port signal forwarded from the backplane channel at this time, but the third channel is in a closed state by default. Even if the serial port signal from the backplane channel is received, the second CPLD does not send the received signal to the second CPU of the slave disk where it is located, nor does it forward the information of the second CPU of the slave disk where it is located to the backplane channel. At this time, only the first CPU of the main control disk can receive the serial port signal and transmit information with the debugging interface, and the slave disks are not affected.
[0068] In an embodiment of the present application, when the third channel is connected, the corresponding connected backplane channel and the second CPU of the corresponding slave disk to be debugged can transmit operation instructions through the third channel. When the above-mentioned second channel and third channel are connected at the same time, the board corresponding to the slave disk to be debugged can be debugged directly through the debugging interface without relying on the CPU system of the main control disk. Even if the CPU system of the main control disk fails, it will not affect the debugging of other boards.
[0069] In some possible embodiments, the second character string adopts the slot information corresponding to the slave disk to be debugged, and may also adopt other character strings with corresponding relationships. The embodiments of the present application do not make specific limitations. Before the device is debugged, the correspondence between the slave disk to be debugged and the character string is stored as logic in the second CPLD.
[0070] For example, the slot information of the master disk / slave disk to be debugged is used as the corresponding string to set the working logic of the first CPLD of the master disk and the second CPLD of each slave disk:
[0071] When the string carried by the serial port signal does not contain continuous strings such as "qieslot1", "qieslot2", and "qieslot3", that is, the serial port signal is not used to debug the board in a certain slot, the first channel between the debugging interface and the first CPU is connected, and the second channel between the debugging interface and the backplane channel is closed. At this time, the serial port signal is processed by the first CPU on the main control disk, such as Figure 7 As shown;
[0072] When the string carried by the serial port signal contains continuous "qieslot1", that is, the serial port signal for debugging the board in slot 1, the first CPLD of the master control disk closes the first channel between the debug interface and the first CPU, and connects the second channel between the debug interface and the backplane channel, the second CPLD of the slave disk corresponding to slot 1 connects the third channel between the backplane channel and the second CPU of the slave disk, and other slots close the third channel between the backplane channel and the second CPU of the slave disk where they are located. At this time, the second CPU of the slave disk corresponding to slot 1 processes the serial port signal, such as Figure 8 Similarly, when the debug interface inputs the continuous string "qieslot2", the second CPLD of the slave disk in slot 2 will connect the third channel between the backplane channel and the second CPU of the slave disk where it is located, and other slots will close the third channel between the backplane channel and the second CPU of the slave disk where it is located. At this time, the second CPU of the slave disk corresponding to slot 2 processes the serial port signal, as shown in FIG. Fig. 9 shown.
[0073] In actual debugging, the first CPLD will automatically switch the direction of serial port data forwarding according to the parsed string and the set working logic. The specific working logic can adopt the slot information of the above-mentioned master disk / slave disk to be debugged, or other strings with corresponding relationships, which are not specifically limited in the embodiments of the present application.
[0074] In some possible embodiments, the above-mentioned master control disk / slave disks parse the serial port signal through CPLD to obtain the corresponding character string, which is to detect the character content of the serial port signal according to the data format. The serial port signal is usually UART serial port data, which is an 8-bit serial code, and the rate is not fast. When the CPLD receives the serial port signal, it synchronously detects the character content of the serial port according to the data format. When the continuous character content meets the artificially set working logic, it will trigger the connection or closing logic of the channel. The artificially set character string usually avoids the character string used for debugging and configuration. The specific character string set for switching channels is not specifically limited in the embodiments of the present application.
[0075] In some possible embodiments, the main control disk includes a primary main control disk and a backup main control disk. By implementing the above system using the present application, one of the main control disks can be used to debug another main control disk, wherein:
[0076] When the first CPLD of any main control disk receives a serial port signal from the debugging interface, it is used to connect the first channel between the debugging interface and the first CPU or to connect the second channel between the debugging interface and the backplane channel. The third CPLD of the other main control disk is used to connect or close the fourth channel between the backplane channel and the third CPU according to the serial port signal received from the backplane channel. The connected second channel and fourth channel are used for the debugging interface to debug the third CPU of the other main control disk.
[0077] Based on the serial port debugging system proposed in the above embodiment of the present application, a process of serial port debugging the main control disk through a debugging interface connected to the main control disk is given below, such as Fig.10 As shown, including:
[0078] Step 1001, receiving a serial port signal from a debugging interface through a first CPLD of a main control disk, and determining that the serial port signal carries a character string corresponding to the main control disk;
[0079] Step 1002: connect the first channel between the debugging interface and the first CPU of the main control disk through the first CPLD of the main control disk, and close the second channel between the debugging interface and the backplane channel;
[0080] Step 1003: Send an operation instruction to the first CPU of the main control disk through the debugging interface through the connected first channel for debugging.
[0081] The following is a process of serial debugging of the slave disk through the debugging interface connected to the master disk, such as Fig.11 As shown, including:
[0082] Step 1101, receiving a serial port signal from a debugging interface through a first CPLD of a master control disk, and determining that the serial port signal carries a character string corresponding to the slave disk to be debugged;
[0083] Step 1102: close the first channel between the debugging interface and the first CPU of the main control disk through the first CPLD of the main control disk, and connect the second channel between the debugging interface and the backplane channel;
[0084] Step 1103, forwarding the serial port signal to all slave disks through the backplane channel;
[0085] Step 1104a, the second CPLD of the slave disk to be debugged receives the serial port signal from the backplane channel, determines that the character string carried by the serial port signal corresponds to the slave disk where the second CPLD is located, and connects the backplane channel to the third channel between the first CPU of the slave disk to be debugged;
[0086] Step 1104b, the second CPLD of the other slave disk receives the serial port signal from the backplane channel, determines that the character string carried by the serial port signal does not correspond to the slave disk where the slave disk is located, and closes the third channel between the backplane channel and the second CPU of the other slave disk;
[0087] Step 1105: The debugging interface sends an operation instruction to the second CPU of the slave disk to be debugged through the connected second channel and the third channel to perform debugging.
[0088] The following is a process for serial debugging of the standby main control disk through the debugging interface connected to the active main control disk, and vice versa. Fig.12 As shown, including:
[0089] Step 1201, receiving a serial port signal from a debugging interface through a first CPLD of the active main control disk, and determining that the serial port signal carries a character string corresponding to the standby main control disk to be debugged;
[0090] Step 1202: close the first channel between the debugging interface and the first CPU of the active main control disk through the first CPLD of the active main control disk, and connect the second channel between the debugging interface and the backplane channel;
[0091] Step 1203, forwarding the serial port signal to each slave disk and the standby master disk through the backplane channel;
[0092] Step 1204a, the second CPLD of each slave disk receives the serial port signal from the backplane channel, determines that the character string carried by the serial port signal does not correspond to the slave disk where the slave disk is located, and closes the third channel between the backplane channel and the second CPU of each slave disk;
[0093] Step 1204b, the third CPLD of the standby main control disk to be debugged receives the serial port signal from the backplane channel, determines that the character string carried by the serial port signal corresponds to the standby main control disk where the third CPLD is located, and connects the fourth channel between the backplane channel and the third CPU of the standby main control disk to be debugged;
[0094] Step 1205: Send an operation instruction to the third CPU of the standby main control disk to be debugged through the connected second channel and fourth channel by the debugging interface for debugging.
[0095] In the embodiment of the present application, any board connected to the backplane channel can be debugged through the debugging interface connected to the main control disk, including the main control disk, each slave disk and the backup main control disk. The corresponding channel is connected or closed only by relying on the CPLD in each device to realize the switching function of the serial port. It can automatically determine whether to switch, and does not need to rely on the traditional CPU system. The serial port can be flexibly switched to the board that needs to be configured.
[0096] Based on the same inventive concept, the embodiment of the present application proposes a serial port debugging device, which serves as a main control disk and includes:
[0097] A first complex programmable logic chip CPLD and a first CPU, wherein the first CPLD is connected to a debugging interface and a backplane channel respectively, wherein the backplane channel is connected to each slave disk;
[0098] The first CPLD is used to connect the first channel between the debugging interface and the first CPU, or to connect the second channel between the debugging interface and the backplane channel;
[0099] The first channel is used for debugging the first CPU through the debugging interface; the second channel is connected to the third channel for debugging the second CPU of the slave disk to be debugged, and the third channel is the channel between the second CPLD of the slave disk to be debugged and the backplane channel.
[0100] In some possible embodiments, the second channel is connected to the fourth channel for debugging the third CPU of another main control disk, and the fourth channel is a channel between the third CPLD of another main control disk to be debugged and the backplane channel.
[0101] A serial port debugging device proposed in an embodiment of the present application, when used as a main control disk, debugs any board connected to the backplane channel through a debugging interface connected to the main control disk, and only relies on the CPLD in each device to connect or close the corresponding channel to realize the switching function of the serial port. It can automatically determine whether to switch, does not need to rely on the traditional CPU system, and flexibly switches the serial port to the board that needs to be configured.
[0102] Based on the same inventive concept, the embodiment of the present application further proposes a serial port debugging device, which serves as a slave disk and includes:
[0103] A second CPLD and a second CPU, wherein the second CPLD is connected to a backplane channel;
[0104] The second CPLD is used to connect the third channel between the backplane channel and the second CPU when the slave disk where the second CPLD is located is the slave disk to be debugged; otherwise, the third channel between the backplane channel and the second CPU is closed, and the backplane channel is connected to the debugging interface through the second channel;
[0105] The connected second channel and third channel are used for debugging the second CPU of the slave disk to be debugged by the debugging interface.
[0106] A serial port debugging device proposed in an embodiment of the present application, when acting as a slave disk, can determine whether the slave disk where it is located is the slave disk to be debugged through the second CPLD in the slave disk, and control the third channel between the backplane channel and the second CPU, cooperate with the CPLD in the above-mentioned master control disk to manage the channel, and flexibly switch the serial port to the board that needs to be configured.
[0107] Based on the same inventive concept, the embodiment of the present application further proposes a serial port debugging method based on the system described in the first aspect above, comprising:
[0108] receiving a serial port signal from a debugging interface via a first CPLD of a main control disk;
[0109] Connecting the first channel between the debugging interface and the first CPU of the main control disk through the first CPLD according to the serial port signal, and debugging the first CPU through the first channel; or
[0110] The second channel between the debugging interface and the backplane channel is connected through the first CPLD according to the serial port signal, the third channel between the backplane channel and the second CPU is connected through the second CPLD of the slave disk to be debugged according to the serial port signal, the third channel between the backplane channel and the second CPU is closed through the second CPLD of the slave disk not to be debugged according to the serial port signal, and the second CPU to be debugged is debugged through the connected second and third channels.
[0111] In some possible embodiments, the method further includes:
[0112] The third CPLD of another main control disk connects the fourth channel between the backplane channel and the third CPU according to the serial port signal received from the backplane channel when the third CPLD is the main control disk to be debugged; otherwise, the fourth channel between the backplane channel and the third CPU is closed;
[0113] The third CPU of another main control disk is debugged through the connected second channel and fourth channel.
[0114] A serial port debugging system, device and method proposed in the embodiments of the present application realize the switching function of the serial port by adopting a complex programmable logic chip CPLD. The connection or closing of the corresponding channel is controlled by the received serial port signal. The switching can be automatically determined without relying on the traditional CPU system, and the serial port can be flexibly switched to the board that needs to be configured.
[0115] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.
Claims
1. A serial port debugging system, characterized in that: The system includes a master control disk, at least one slave disk, and backplane channels respectively connecting the master control disk and each slave disk, wherein: The main control disk includes a first complex programmable logic chip CPLD and a first CPU, wherein the first CPLD is connected to the debugging interface and the backplane channel respectively, and is used to connect the first channel between the debugging interface and the first CPU or the second channel between the debugging interface and the backplane channel; Each slave disk includes a second CPLD and a second CPU, wherein the second CPLD is used to connect or close a third channel between the backplane channel and the second CPU; The first channel is used for debugging the first CPU through the debugging interface, and the connected second channel and third channel are used for debugging the second CPU of the slave disk to be debugged through the debugging interface.
2. The system according to claim 1, characterized in that The first CPLD is also used for: receiving a serial port signal from the debugging interface, and when determining that the serial port signal carries a first character string corresponding to the main control disk, connecting a first channel between the debugging interface and the first CPU, and closing a second channel between the debugging interface and the backplane channel; When it is determined that the serial port signal carries a second character string corresponding to the slave disk to be debugged, the first channel between the debugging interface and the first CPU is closed, and the second channel between the debugging interface and the backplane channel is connected.
3. The system according to claim 1, characterized in that The second CPLD is also used for: When receiving a serial port signal through a backplane channel and determining that a second character string carried by the serial port signal corresponds to the slave disk where the slave disk is located, connecting the backplane channel to a third channel between the second CPU; When it is determined that the second character string carried by the serial port signal does not correspond to the slave disk where the slave disk is located, the third channel between the backplane channel and the second CPU is closed.
4. The system according to claim 1, characterized in that The main control disk includes a primary main control disk and a backup main control disk, wherein: When the first CPLD of any main control disk receives a serial port signal from the debugging interface, it is used to connect the first channel between the debugging interface and the first CPU or to connect the second channel between the debugging interface and the backplane channel. The third CPLD of the other main control disk is used to connect or close the fourth channel between the backplane channel and the third CPU according to the serial port signal received from the backplane channel.
5. The system according to claim 1, characterized in that In a default state, the first CPLD connects the first channel between the debugging interface and the first CPU, and connects the second channel between the debugging interface and the backplane channel; the second CPLD closes the third channel between the backplane channel and the second CPU in a default state.
6. A serial port debugging device, characterized in that: The serial port debugging device serves as a main control disk and includes: A first complex programmable logic chip CPLD and a first CPU, wherein the first CPLD is connected to a debugging interface and a backplane channel respectively, wherein the backplane channel is connected to each slave disk; The first CPLD is used to connect the first channel between the debugging interface and the first CPU, or to connect the second channel between the debugging interface and the backplane channel; The first channel is used for debugging the first CPU through the debugging interface; the second channel is connected to the third channel for debugging the second CPU of the slave disk to be debugged, and the third channel is the channel between the second CPLD of the slave disk to be debugged and the backplane channel.
7. The device according to claim 6, characterized in that The second channel is connected to the fourth channel for debugging the third CPU of another main control disk, and the fourth channel is a channel between the third CPLD of another main control disk to be debugged and the backplane channel.
8. A serial port debugging device, characterized in that: The serial port debugging device as a slave disk includes: A second CPLD and a second CPU, wherein the second CPLD is connected to a backplane channel; The second CPLD is used to connect the third channel between the backplane channel and the second CPU when the slave disk where the second CPLD is located is the slave disk to be debugged; otherwise, the third channel between the backplane channel and the second CPU is closed, and the backplane channel is connected to the debugging interface through the second channel; The connected second channel and third channel are used for debugging the second CPU of the slave disk to be debugged by the debugging interface.
9. A serial port debugging method based on the system of claim 1, characterized in that: include: receiving a serial port signal from a debugging interface via a first CPLD of a main control disk; Connecting the first channel between the debugging interface and the first CPU of the main control disk through the first CPLD according to the serial port signal, and debugging the first CPU through the first channel; or The second channel between the debugging interface and the backplane channel is connected through the first CPLD according to the serial port signal, the third channel between the backplane channel and the second CPU is connected through the second CPLD of the slave disk to be debugged according to the serial port signal, the third channel between the backplane channel and the second CPU is closed through the second CPLD of the slave disk not to be debugged according to the serial port signal, and the second CPU to be debugged is debugged through the connected second and third channels.
10. The method according to claim 9, characterized in that Also includes: The third CPLD of another main control disk connects the fourth channel between the backplane channel and the third CPU according to the serial port signal received from the backplane channel when the third CPLD is the main control disk to be debugged; otherwise, the fourth channel between the backplane channel and the third CPU is closed; The third CPU of another main control disk is debugged through the connected second channel and fourth channel.