IO circuit based on LPDDR5 / 5X PHY

Abstract

The invention aims to provide an IO circuit based on an LPDDR5 / 5X PHY. The circuit comprises a receiver circuit, an LPDDR5 / 5X PHY IO circuit and a PHY IO circuit, the receiver circuit includes: a first coarse tuning circuit; the input end of the first coarse tuning circuit is connected with the analog amplification circuit, and the output end of the first coarse tuning circuit is connected with the first D-trigger; the first coarse tuning circuit is located in a clock path. According to the invention, by improving the IO architecture, the CDL module is ingeniously adjusted to the clock path from the original data path, so that the adjustment result with the same delay can be achieved. However, jitter of IO TX end output data and RX end input data can be well improved. And meanwhile, the data cycle is improved, and data accumulation jitter can be improved to a certain extent. By reducing the delay units on the data path, the influence of high-speed data signals and ISI (International Standard Interference) can be well improved, so that the signal quality is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a LPDDR5 / 5X PHY IO circuit. Background Art

[0002] In the field of circuit design technology, as high-performance computing and AI (Artificial Intelligence) large models move towards large-scale applications, the demand for transmission bandwidth of high-speed data interfaces is growing. However, this growth in demand is also accompanied by new challenges, and the requirements for IO architecture are getting higher and higher. The main problems suffered by signals during transmission include inter-symbol interference (ISI), crosstalk, reflection and attenuation, all of which may cause signal quality to deteriorate and affect the correct interpretation of data. Especially for high-speed signals, these problems become more serious, seriously affecting the transmission reliability of the signal.

[0003] IO architecture refers to the communication flow within the operating system, which is used to provide communication between different modules. At the hardware level, IO architecture describes how to connect different computer hardware modules, usually in a master-slave mode, that is, there is a management center (such as the memory management unit MMU) responsible for connecting with other hardware. In this way, the CPU memory is isolated from the computer hardware, which is convenient for subsequent iterative maintenance.

[0004] In order to solve the problem of signal quality in high-speed data transmission, IO architecture is crucial. IO architecture mainly includes transmitter (TX) and receiver (RX) circuits. TX circuit mainly includes driver circuit (Driver), coarse tuning circuit (CDL), D-flip-flop (DFF), cycle adjustment (DCC) circuit, etc. RX circuit mainly includes analog amplifier circuit (AFE), coarse tuning circuit (CDL), D-flip-flop (DFF), cycle adjustment (DCC) circuit, etc. Traditional TX such as Figure 6 As shown in the figure, the traditional RX structure is as follows Figure 7 shown.

[0005] The traditional transmitter circuit places the CDL circuit on the data path to adjust the data delay so as to meet the required design requirements. As we all know, CDL contains a large number of delay units, so when the data passes through CDL, it is equivalent to passing through these delay units. As the number of delay units increases, jitter will accumulate, increasing the impact of ISI. At the same time, it will also increase the difficulty of adjusting the data cycle at all process corners. The deterioration of the data cycle will also affect DDJ, thereby deteriorating the signal quality. The same receiver (RX) has similar defects. Summary of the invention

[0006] The purpose of the present invention is to provide a LPDDR5 / 5X PHY IO circuit, which improves the IO architecture and cleverly adjusts the CDL module from the original data path to the clock path, so that the same delay adjustment result can be achieved. However, the jitter of the IO TX end output data and the RX end input data can be well improved. At the same time, the data cycle is improved, and the data accumulation jitter can also be improved to a certain extent. By reducing the delay unit on the data path, especially for high-speed data signals, the impact on ISI can be well improved, thereby improving the signal quality.

[0007] A LPDDR5 / 5X PHY IO circuit, comprising: a receiver circuit; The receiver circuit includes: a first coarse adjustment circuit; The input end of the first coarse adjustment circuit is connected to the analog amplifier circuit, and the output end is connected to the first D-flip-flop; The first coarse adjustment circuit is located in the clock path.

[0008] Preferably, it also includes: a transmitter circuit; The transmitter circuit includes: a second coarse adjustment circuit; The input end of the second coarse adjustment circuit is connected to the second D-flip-flop, and the output end is connected to the driving circuit; The second coarse adjustment circuit is located in the clock path.

[0009] Preferably, the receiver circuit further comprises: an analog amplifier circuit, a first D-flip-flop and a first period adjustment circuit; The output terminal of the first period adjustment circuit is connected to the first D-flip-flop; The input end of the analog amplifier circuit is connected to the PAD, and the output end is connected to the first coarse adjustment circuit; The first D-flip-flop is connected to the period adjustment circuit.

[0010] Preferably, the transmitter circuit further comprises: a driving circuit, a second D-flip flop and a second period adjustment circuit; The output terminal of the second D-flip-flop is connected to the input terminal of the driving circuit; The output end of the driving circuit is connected to the PAD, and is used to receive the signal output by the second D-flip-flop and output it after encoding; An output terminal of the second period adjustment circuit is connected to the second D-flip-flop.

[0011] The first coarse adjustment circuit includes a plurality of delay units for adjusting circuit delay.

[0012] Preferably, the first coarse adjustment circuit specifically includes: a first comparator, a second comparator, a first NOT gate, a second NOT gate, a first D register, a second D register, an adder and a D / A converter; The output terminal of the first comparator is connected to the input terminal of the first NOT gate; The output end of the first NOT gate is connected to the D end of the first D register; The CK terminal of the first D register is connected to the clock frequency, and the Q terminal is connected to the adder; The output terminal of the second comparator is connected to the input terminal of the second NOT gate; The output terminal of the second NOT gate is connected to the D terminal of the second D register; The CK terminal of the second D register is connected to the clock frequency, and the Q terminal is connected to the adder; The output terminal of the adder is connected to the input terminal of the D / A converter.

[0013] Preferably, the analog amplifier circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, and a first transistor; The collector of the first transistor is connected to the second end of the third resistor, the transmitter is connected to the first end of the fourth resistor and the first plate of the third capacitor, and the base is connected to the first capacitor; The second end of the first resistor is connected to the first end of the second resistor, and the first end is connected to VCC; The second end of the second resistor is grounded; The second end of the fourth resistor is grounded; The second electrode plate of the third capacitor is grounded; The first electrode plate of the second capacitor is connected to the collector, and the second electrode plate is connected to the first end of the fifth resistor; The second end of the fifth resistor is grounded; The first end of the third resistor is connected to VCC.

[0014] A LPDDR5 / 5X PHY IO circuit control method is applied to a LPDDR5 / 5X PHY IO circuit, comprising: The transmitter converts the low-speed parallel signal into a high-speed serial signal and sends it to the receiver; The receiver converts the received high-speed serial signal into a low-speed parallel signal and sends it to the digital end.

[0015] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program code, the computer program code comprises computer instructions, and when the processor executes the computer instructions, the electronic device executes a LPDDR5 / 5X PHY IO circuit control method.

[0016] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a LPDDR5 / 5X PHY IO circuit control method.

[0017] The beneficial effects of the present invention are as follows: 1. For the transmitter circuit, the present invention can greatly reduce the number of levels on the data path by adjusting the CDL module from the original data path to the clock path, thereby reducing the impact of ISI, improving jitter (DJ), and improving signal quality. 2. For the receiver circuit, the present invention can greatly reduce the number of levels on the data path by adjusting the CDL module from the original data path to the clock path, thereby improving the data period, thereby improving the jitter (DDJ) caused by periodic errors and improving signal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 It is a schematic diagram of the circuit structure of a transmitter based on LPDDR5 / 5X PHY IO circuit of the present invention; Figure 2 A schematic diagram of the structure of a receiver circuit based on LPDDR5 / 5X PHY IO circuit of the present invention; Figure 3 It is a schematic diagram of the structure of the coarse adjustment circuit of the present invention; Figure 4 It is a structural diagram of the analog amplifier circuit of the present invention; Figure 5 A schematic diagram of the hardware structure of an electronic device of the present invention; Figure 6 It is a schematic diagram of the structure of a conventional transmitter circuit of the present invention; Figure 7 FIG. 1 is a schematic diagram of a conventional receiver circuit structure of the present invention. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0023] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0024] The traditional transmitter circuit places the CDL circuit on the data path to adjust the data delay so as to meet the required design requirements. As we all know, CDL contains a large number of delay units, so when the data passes through CDL, it is equivalent to passing through these delay units. As the number of delay units increases, jitter will accumulate, increasing the impact of ISI. At the same time, it will also increase the difficulty of adjusting the data cycle at all process corners. The deterioration of the data cycle will also affect DDJ, thereby deteriorating the signal quality. The same receiver (RX) has similar defects.

[0025] For the transmitter circuit, the present invention can greatly reduce the number of levels on the data path by adjusting the CDL module from the original data path to the clock path, thereby reducing the impact of ISI, improving jitter (DJ), and improving signal quality. For the receiver circuit, the present invention can greatly reduce the number of levels on the data path by adjusting the CDL module from the original data path to the clock path, thereby improving the data period, thereby improving jitter (DDJ) caused by periodic errors and improving signal quality.

[0026] Example 1 A LPDDR5 / 5X PHY IO circuit, reference Figure 1 , comprising: a receiver circuit; The receiver circuit includes: a first coarse adjustment circuit; The receiver circuit plays a vital role in the IO architecture. It ensures that data can be transmitted from external devices to the CPU accurately and efficiently. Specifically, the working principle of the receiver circuit includes the following aspects: Data transmission: Through the front-end bus and the back-end bus, the receiver circuit is responsible for transferring data from external devices to the CPU, or transferring data from the CPU to external devices. These buses are channels for high-speed data transmission, ensuring the rapid exchange of data. Signal processing: The receiver circuit also needs to handle operations such as signal amplification and filtering to ensure signal stability and accuracy. This includes amplification of input signals and suppression of noise to ensure data integrity and reliability. Clock synchronization: In multi-device communication, the receiver circuit also needs to deal with clock synchronization issues to ensure that each device exchanges data on the same time base to avoid data conflicts and losses.

[0027] The input end of the first coarse adjustment circuit is connected to the analog amplifier circuit, and the output end is connected to the first D-flip-flop; The first coarse adjustment circuit is located in the clock path.

[0028] The difference between the clock path and the data path lies in the type of signal, transmission method and application scenario. The clock path refers to the path of the clock signal from the source to the register clock pin. In FPGA, the clock signal is usually provided by an external crystal oscillator, and after being processed by the internal phase-locked loop (PLL), it is distributed to each register that needs to be synchronized. The transmission of the clock path needs to ensure the stability and accuracy of the clock signal, because clock deviation, jitter and temperature drift will affect the correct sampling of data. The data path refers to the process of data transmission from the output pin of one register to the input pin of another register. Data may pass through programmable interconnects and combinational logic during transmission, so the transmission time will be affected by wiring delays and logic gate delays. The key to the data path is to ensure that the data is stable before the rising edge of the clock arrives and remains stable for enough time to meet the setup time and hold time requirements of the register.

[0029] Inter-Symbol Interference (ISI) refers to the situation in digital communication systems where the waveforms of the previous and next symbols are distorted and widened due to the unsatisfactory overall transmission characteristics of the system, causing the tail of the waveform of the previous symbol to spread to the sampling time of the current symbol, thereby interfering with the decision of the current symbol. This interference is different from additive noise, a multiplicative interference. The main cause of inter-symbol interference is the unsatisfactory overall transmission characteristics of the system, which causes the signal waveform to be distorted and widened. Specifically, when the signal passes through the transmission medium, due to the different frequency components of the signal, some frequency components will be subject to greater attenuation or phase changes, resulting in waveform distortion. This distorted waveform will continue to the sampling time of the next symbol, interfering with the decision of the next symbol. The impact of inter-symbol interference is mainly reflected in the increase in the bit error rate of the signal, resulting in a decrease in communication quality.

[0030] In the embodiment of the present invention, by adjusting the coarse adjustment circuit from the original data path to the clock path, the number of stages on the data path can be greatly reduced, thereby reducing the impact of ISI, improving jitter (DJ), and improving signal quality.

[0031] Preferably, reference Figure 2 , further comprising: a transmitter circuit; The transmitter circuit includes: a second coarse adjustment circuit; The input end of the second coarse adjustment circuit is connected to the second D-flip-flop, and the output end is connected to the driving circuit; A second coarse tuning circuit is located in the clock path.

[0032] The working principle of the transmitter circuit mainly includes the following steps: Signal generation: First, generate the signal to be transmitted. Modulation: Modulate the signal to a specific frequency, usually using amplitude modulation (AM), frequency modulation (FM) or phase modulation (PM). Power amplification: Enhance the power of the signal to ensure the transmission distance and stability. Transmission: Radiate the modulated signal through the antenna. The transmitter circuit implements the data buffering function to ensure the speed matching between the high-speed CPU and the slow peripherals, and avoid transmission errors caused by speed mismatch. The transmitter circuit performs signal conversion, including digital-to-analog conversion, serial-to-parallel format conversion and logic level conversion, to ensure compatibility between different devices and the accuracy of data transmission. The transmitter circuit implements the interrupt control function, so that the CPU and external devices can work in parallel, and automatically handle faults when necessary, improving the stability and response speed of the system. The transmitter circuit is also responsible for the timing of the system and the counting and control of external events to ensure that the system operates at the scheduled time and improve the automation and accuracy of the system. DMA transfer: The transmitter circuit supports direct memory access (DMA) transfer, which enables direct information exchange between memory and I / O devices, improving the efficiency and speed of data transmission. In the field of communications, the transmitter circuit ensures the communication protocol standards and data transmission reliability between different devices through signal conversion and interrupt control functions. In data processing, the transmitter circuit ensures that the system processes data and schedules tasks according to the scheduled time through the timing and counting function, improving the automation and accuracy of the system.

[0033] Preferably, the receiver circuit further comprises: an analog amplifier circuit, a first D-flip-flop and a first period adjustment circuit; An output terminal of the first cycle regulating circuit is connected to a first D-flip-flop; The input end of the analog amplifier circuit is connected to the PAD, and the output end is connected to the first coarse adjustment circuit; The PAD side of the IO architecture refers to the input and output interface part of the integrated circuit, including the pad (PAD) and related circuits, power lines and ground lines. These components together constitute the interface between the integrated circuit and the outside world, realizing the input and output functions of data. In an integrated circuit, the PAD is the metal wire connection point that connects the chip to the package socket, usually a rectangle of tens of microns. In order to prevent the gold wire from short-circuiting, a minimum distance needs to be maintained between the PADs, and this distance depends on the package form. Most I / O PADs appear in the form of a standard unit structure, with a set of I / O libraries, usually with shapes of equal height and unequal width. IO Ring and Pad Ring refer to rings composed of IO and Pad, respectively. General input / output ports are composed of IO and Pad together.

[0034] The first D-flip-flop is connected to the cycle adjustment circuit.

[0035] The main function of the cycle adjustment circuit is to adjust the working cycle of the circuit to ensure that the circuit can operate stably under different working conditions. The cycle adjustment circuit is an electronic device that can adjust the working cycle of the circuit as needed. It adjusts the working cycle of the circuit by controlling the switching state of the circuit to meet different working requirements. The cycle adjustment circuit usually consists of two parts: the control circuit and the execution circuit. The control circuit is responsible for generating the control signal, and the execution circuit performs the switch operation according to the control signal. The main functions of the cycle adjustment circuit of the IO architecture include the following aspects: Data buffering and latching function: The cycle adjustment circuit can provide data buffering and latching functions to ensure smooth data transmission between the CPU and the peripherals and avoid data loss or conflict. Signal level conversion function: The circuit can convert different signal levels to adapt to the voltage and current requirements between the CPU and the peripherals to ensure the correct transmission of the signal. Data format conversion function: The cycle adjustment circuit can realize the conversion of data formats, such as serial and parallel conversion, to meet different data transmission requirements. Interrupt management function: Through the interrupt management function, the cycle adjustment circuit can realize the parallel operation of the CPU and the external device, and perform fault processing when necessary to improve the response speed and stability of the system. Timing and counting function: The cycle adjustment circuit can also realize the timing of the system and the counting function of external events to ensure accurate timing and event control of the system. In some cases, the cycle adjustment circuit also has an isolation function to ensure stable operation of the system in different environments.

[0036] Preferably, the transmitter circuit further comprises: a driving circuit, a second D-flip flop and a second period adjustment circuit; An output terminal of the second D-flip-flop is connected to an input terminal of the driving circuit; The output end of the driving circuit is connected to the PAD, and is used to receive the signal output by the second D-flip-flop and output it after encoding; The output terminal of the second cycle regulation circuit is connected to the second D-flip-flop.

[0037] A D flip-flop usually has two inputs: a clock (CLK) input and a data (D) input. It also has two outputs: a main output Q and a Q' complement output Q'. When the clock signal is high, the D flip-flop is in a hold state and the input signal is locked; when the clock signal is low, the input signal is transferred to the output terminal ‌4. This clock-controlled circuit is called a sequential circuit because the state of the D flip-flop is controlled by the clock signal and can maintain a certain level‌.

[0038] The role of the D flip-flop in the IO architecture mainly includes the following aspects: Data storage: The D flip-flop is a device with memory function that can store 1 bit of binary data. It has two stable states, 0 and 1, and can flip from one state to another under the action of external signals. Providing a ready state for peripheral data: The D flip-flop can be used to provide a ready state for peripheral data to ensure the accuracy and reliability of data during transmission. The basic unit that constitutes the timing circuit: The D flip-flop is the basic logic unit that constitutes a variety of timing circuits and is widely used in digital systems and computers. It can maintain a certain level under the control of the clock signal, so it is called a circuit with memory function.

[0039] The first coarse adjustment circuit includes a plurality of delay units for adjusting circuit delay.

[0040] The function of the delay unit is to limit the current and thus control the delay time of the circuit.

[0041] The function of the delay unit is to increase the delay time of the signal to fix the hold time violation of the clock signal. Compared with the buffer unit, the delay unit can provide more delay to fix the hold time violation of the clock signal. Specifically, the delay unit increases the propagation time of the signal to ensure that the signal remains valid when it reaches the receiving end, thereby meeting the hold time requirement of the clock signal. The delay unit can ensure the stability and reliability of the clock signal by increasing the propagation time of the signal.

[0042] Preferably, reference Figure 3 , the first coarse adjustment circuit specifically includes: a first comparator, a second comparator, a first NOT gate, a second NOT gate, a first D register, a second D register, an adder and a D / A converter; An output terminal of the first comparator is connected to an input terminal of the first NOT gate; ‌‌The first comparator is used to compare the current or voltage of the two input terminals, and output different voltage results at the output terminal according to the comparison result. ‌ The first comparator has two input terminals (such as Vi+ and Vi-) and an output terminal (Vout). The input terminal receives analog signals and the output terminal outputs digital signals, which usually have two states: high level or low level. ‌ The comparator compares the voltage or current of the two input terminals and generates a high level or low level signal at the output terminal according to the comparison result. The state of the output terminal depends on the high and low relationship of the voltage of the two input terminals. When the voltage of the positive input terminal is higher than the voltage of the negative input terminal, a high level is output; otherwise, a low level is output.

[0043] An output terminal of the first NOT gate is connected to a D terminal of the first D register; The CK terminal of the first D register is connected to the clock frequency, and the Q terminal is connected to the adder; Adders are used to produce the sum of numbers. ‌ An adder is a digital circuit that is used to perform the calculation of adding numbers. It can be a half adder or a full adder, depending on its design and functionality. ‌

[0044] The output terminal of the second comparator is connected to the input terminal of the second NOT gate; The output terminal of the second NOT gate is connected to the D terminal of the second D register; The CK terminal of the second D register is connected to the clock frequency, and the Q terminal is connected to the adder; The output terminal of the adder is connected to the input terminal of the D / A converter.

[0045] A D / A converter is a circuit device that converts digital quantities into analog quantities. It is mainly used in various application scenarios that require digital signal to analog signal conversion, such as data transmission systems, automatic test equipment, medical information processing, digitization of television signals, processing and recognition of image signals, digital communication and information processing, etc. The basic working principle of a D / A converter is to convert each bit of the digital code into a corresponding analog quantity according to its "weight", and then add these analog quantities to finally obtain an analog quantity proportional to the digital quantity. Its structure usually includes a data latch, an electronic switch, a bit weight network, a summing operational amplifier and a reference voltage source (or constant current source). Specifically, each bit of the digital quantity stored in the data latch controls the electronic switch of the corresponding bit, so that the bit with a digital value of 1 generates a current value proportional to its bit weight on the bit weight network, and then the operational amplifier sums the current values ​​and converts them into a voltage value. The main components of a D / A converter include a weight resistor network, an operational amplifier, a reference power supply and an analog switch. Such devices play a key role in many electronic systems, particularly where digital signals need to be converted to analog for further processing or display.

[0046] Preferably, reference Figure 4 , the analog amplifier circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, and a first transistor; The collector of the first triode is connected to the second end of the third resistor, the transmitter is connected to the first end of the fourth resistor and the first plate of the third capacitor, and the base is connected to the first capacitor; The second end of the first resistor is connected to the first end of the second resistor, and the first end is connected to VCC; A second end of the second resistor is grounded; The second end of the fourth resistor is grounded; The second plate of the third capacitor is grounded; The first plate of the second capacitor is connected to the collector, and the second plate is connected to the first end of the fifth resistor; The second end of the fifth resistor is grounded; A first end of the third resistor is connected to VCC.

[0047] The functions of analog amplifier circuits include signal amplification, signal conditioning, impedance matching and signal driving. Signal amplification: The basic function of analog amplifier circuits is to amplify weak input signals to the required amplitude, so that the signal can be more easily processed by subsequent circuits or drive external devices. Gain is a key parameter to measure the amplification ability of an amplifier, which indicates the amplitude ratio between the output signal and the input signal. Signal conditioning: In addition to the simple amplification function, analog amplifiers can also condition signals, including filtering, level conversion, etc. For example, operational amplifiers (op amps) can achieve multiple functions such as positive amplification, inverting amplification, and filtering through different configurations. The filtering function can help remove noise and unwanted frequency components in the signal and improve the signal-to-noise ratio and purity. Impedance matching: Analog amplifiers can also be used to achieve impedance matching, that is, adjust the input and output impedance of the circuit to optimize signal transmission and power conversion efficiency. In some applications, such as audio amplifiers, impedance matching is essential to ensure sound quality. Signal driving: The amplified signal can drive various loads, and the analog amplifier can provide enough power and current to drive these loads to work properly.

[0048] Example 2 A LPDDR5 / 5X PHY IO circuit control method is applied to a LPDDR5 / 5X PHY IO circuit, comprising: The transmitter converts the low-speed parallel signal into a high-speed serial signal and sends it to the receiver; ‌Low-speed parallel signaling‌ refers to a parallel data transmission method with a lower transmission rate, which is usually used to connect multiple devices or components and transmit multiple data bits at the same time. This transmission method transmits data simultaneously through multiple data lines, each line represents a data bit, and the data is read and processed at the same time‌.

[0049] High-speed serial signals refer to data signals transmitted through serial communication. Compared with traditional parallel transmission, serial transmission uses a single data line, avoiding the crosstalk problem between multiple data lines in parallel transmission, thereby improving the transmission speed and anti-interference ability. Serial signals transmit data through a single data line, avoiding the crosstalk problem between multiple data lines in parallel transmission. In addition, serial signals can use differential signals, clock-data recovery (CDR) and channel equalization to further improve the transmission rate. Differential signals transmit signals through two wires, which can effectively resist noise and interference, while CDR technology can eliminate clock offset and reduce electromagnetic interference, thereby improving the transmission rate. Serial signals greatly enhance their anti-interference ability by adopting technologies such as differential signals and low-voltage differential signals. Differential signals transmit opposite signals through two wires, which can effectively offset external noise and reduce interference. In addition, serial signals can also eliminate clock offset and further reduce electromagnetic interference through clock-data recovery (CDR) technology. Serial signals reduce electromagnetic interference through CDR technology. CDR technology can eliminate clock offset and avoid electromagnetic interference problems caused by transmitting high-frequency clock signals on PCB or wires, thereby improving the stability and reliability of the system.

[0050] The receiver converts the received high-speed serial signal into a low-speed parallel signal and sends it to the digital end.

[0051] Example 3 An electronic device includes: a processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, when the processor executes the computer instructions, the electronic device executes a LPDDR5 / 5XPHY IO circuit control method.

[0052] refer to Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0053] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0054] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0055] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0056] Example 4 A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a LPDDR5 / 5X PHY IO circuit control method.

[0057] For the transmitter circuit, the present invention can greatly reduce the number of levels on the data path by adjusting the CDL module from the original data path to the clock path, thereby reducing the impact of ISI, improving jitter (DJ), and improving signal quality. For the receiver circuit, the present invention can greatly reduce the number of levels on the data path by adjusting the CDL module from the original data path to the clock path, thereby improving the data period, thereby improving jitter (DDJ) caused by periodic errors and improving signal quality.

[0058] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A LPDDR5 / 5X PHY IO circuit, characterized in that: include: Receiver circuit; The receiver circuit includes: a first coarse adjustment circuit; The input end of the first coarse adjustment circuit is connected to the analog amplifier circuit, and the output end is connected to the first D-flip-flop; The first coarse adjustment circuit is located in the clock path.

2. The LPDDR5 / 5X PHY IO circuit according to claim 1, characterized in that: Also includes: Transmitter circuit; The transmitter circuit includes: a second coarse adjustment circuit; The input end of the second coarse adjustment circuit is connected to the second D-flip-flop, and the output end is connected to the driving circuit; The second coarse adjustment circuit is located in the clock path.

3. The LPDDR5 / 5X PHY IO circuit according to claim 1, characterized in that: The receiver circuit also includes: an analog amplifier circuit, a first D-flip-flop, and a first period adjustment circuit; The output terminal of the first period adjustment circuit is connected to the first D-flip-flop; The input end of the analog amplifier circuit is connected to the PAD, and the output end is connected to the first coarse adjustment circuit; The first D-flip-flop is connected to the period adjustment circuit.

4. The LPDDR5 / 5X PHY IO circuit according to claim 2, characterized in that: The transmitter circuit also includes: a driving circuit, a second D-flip-flop and a second period adjustment circuit; The output terminal of the second D-flip-flop is connected to the input terminal of the driving circuit; The output end of the driving circuit is connected to the PAD, and is used to receive the signal output by the second D-flip-flop and output it after encoding; An output terminal of the second period adjustment circuit is connected to the second D-flip-flop.

5. The LPDDR5 / 5X PHY IO circuit according to claim 1, characterized in that: The first coarse adjustment circuit includes a plurality of delay units for adjusting circuit delay.

6. The LPDDR5 / 5X PHY IO circuit according to claim 1, characterized in that: The first coarse adjustment circuit specifically includes: a first comparator, a second comparator, a first NOT gate, a second NOT gate, a first D register, a second D register, an adder and a D / A converter; The output terminal of the first comparator is connected to the input terminal of the first NOT gate; The output end of the first NOT gate is connected to the D end of the first D register; The CK terminal of the first D register is connected to the clock frequency, and the Q terminal is connected to the adder; The output terminal of the second comparator is connected to the input terminal of the second NOT gate; The output terminal of the second NOT gate is connected to the D terminal of the second D register; The CK terminal of the second D register is connected to the clock frequency, and the Q terminal is connected to the adder; The output terminal of the adder is connected to the input terminal of the D / A converter.

7. The LPDDR5 / 5X PHY IO circuit according to claim 3, characterized in that: The analog amplifier circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, and a first transistor; The collector of the first transistor is connected to the second end of the third resistor, the transmitter is connected to the first end of the fourth resistor and the first plate of the third capacitor, and the base is connected to the first capacitor; The second end of the first resistor is connected to the first end of the second resistor, and the first end is connected to VCC; The second end of the second resistor is grounded; The second end of the fourth resistor is grounded; The second electrode plate of the third capacitor is grounded; The first electrode plate of the second capacitor is connected to the collector, and the second electrode plate is connected to the first end of the fifth resistor; The second end of the fifth resistor is grounded; The first end of the third resistor is connected to VCC.

8. A method for controlling a LPDDR5 / 5X PHY IO circuit, applied to a LPDDR5 / 5X PHY IO circuit according to any one of claims 1 to 7, characterized in that: include: The transmitter converts the low-speed parallel signal into a high-speed serial signal and sends it to the receiver; The receiver converts the received high-speed serial signal into a low-speed parallel signal and sends it to the digital end.

9. An electronic device, characterized in that: include: A processor and a memory, wherein the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and when the processor executes the computer instructions, the electronic device executes a LPDDR5 / 5X PHY IO circuit control method according to claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor executes a LPDDR5 / 5X PHY IO circuit control method according to claim 8.

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