A kind of LPDDR5 / 5X PHY IO circuit-based

Abstract

The object of the present invention is to provide an LPDDR5 / 5X PHY IO circuit, which includes: a receiver circuit; the receiver circuit includes: a first coarse adjustment circuit; the input end of the first coarse adjustment circuit is connected to an analog amplification circuit, and the output end is connected to a first D-flip flop; the first coarse adjustment circuit is located in the clock path. By improving the IO architecture, the present invention cleverly adjusts the CDL module from the original data path to the clock path, so as to achieve the same delay adjustment result. However, it can well improve the jitter of the output data at the IO TX end and the input data at the RX end. At the same time, by improving the data period, the accumulated jitter of the data can also be improved to a certain extent. By reducing the delay units on the data path, especially for high-speed data signals, the influence on ISI can be well improved, thereby improving the signal quality.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to an LPDDR5 / 5X PHY IO circuit. Background Art

[0002] In the field of circuit design technology, with the large-scale application of high-performance computing and AI (Artificial Intelligence) large models, the demand for the transmission bandwidth of high-speed data interfaces is increasing day by day. However, the growth of this demand is also accompanied by new challenges, and the requirements for the IO architecture are getting higher and higher. The main problems suffered by signals during transmission include inter-symbol interference (ISI), crosstalk, reflection, and attenuation, all of which may lead to a decline in signal quality and affect the correct interpretation of data. Especially for high-speed signals, these problems become more serious, seriously affecting the transmission reliability of signals.

[0003] The IO architecture refers to the communication flow inside the operating system, which is used to provide communication between different modules. At the hardware level, the IO architecture describes how to connect different computer hardware modules, usually adopting the master-slave mode, that is, there is a management center (such as the memory management unit MMU) responsible for connecting with other hardware. In this way, the CPU memory is isolated from the computer hardware, facilitating subsequent iterative maintenance.

[0004] To solve the problem of signal quality in high-speed data transmission, the IO architecture is crucial. The IO architecture mainly includes a transmitter (TX) and a receiver (RX) circuit. The TX circuit mainly includes a driver circuit, a coarse delay line (CDL), a D flip-flop (DFF), a duty cycle corrector (DCC) circuit, etc. The RX circuit mainly includes an analog front-end (AFE) circuit, a coarse delay line (CDL), a D flip-flop (DFF), a duty cycle corrector (DCC) circuit, etc. Traditional TXs are as Figure 6 shown, and traditional RX structures are as Figure 7 shown.

[0005] The traditional transmitter circuit places the CDL circuit on the data path to adjust the delay of the data, so as to meet the required design requirements. As is well known, a large number of delay cells are included in the CDL. Then, when the data passes through the CDL, it is equivalent to passing through these delay cells. As the number of delay cells passed through increases, jitter will accumulate, increasing the influence of ISI. At the same time, it will also increase the difficulty of adjusting the data cycle at the full process corner. The variation of the data cycle will also affect the DDJ, thus deteriorating the signal quality. Similarly, the receiver (RX) has similar defects. Summary of the Invention

[0006] The object of the present invention is to provide an LPDDR5 / 5X PHY IO circuit, which can achieve the same delay adjustment result by improving the IO architecture and cleverly adjusting the CDL module from the original data path to the clock path. However, it can well improve the jitter of the output data at the IO TX end and the input data at the RX end. At the same time, it improves the data cycle and can also improve the data accumulation jitter to a certain extent. By reducing the delay units on the data path, especially for high-speed data signals, it can well improve the influence on ISI, thereby improving the signal quality.

[0007] An LPDDR5 / 5X PHY IO circuit, comprising: a receiver circuit;

[0008] The receiver circuit includes: a first coarse adjustment circuit;

[0009] The input end of the first coarse adjustment circuit is connected to an analog amplification circuit, and the output end is connected to a first D flip-flop;

[0010] The first coarse adjustment circuit is located on the clock path.

[0011] Preferably, it further includes: a transmitter circuit;

[0012] The transmitter circuit includes: a second coarse adjustment circuit;

[0013] The input end of the second coarse adjustment circuit is connected to the second D flip-flop, and the output end is connected to a drive circuit;

[0014] The second coarse adjustment circuit is located on the clock path.

[0015] Preferably, the receiver circuit further includes: an analog amplification circuit, a first D flip-flop and a first cycle adjustment circuit;

[0016] The output end of the first cycle adjustment circuit is connected to the first D flip-flop;

[0017] The input end of the analog amplification circuit is connected to PAD, and the output end is connected to the first coarse adjustment circuit;

[0018] The first D flip-flop is connected to the cycle adjustment circuit.

[0019] Preferably, the transmitter circuit further includes: a drive circuit, a second D flip-flop and a second cycle adjustment circuit;

[0020] The output end of the second D flip-flop is connected to the input end of the drive circuit;

[0021] The output end of the drive circuit is connected to PAD, and is used to receive the signal output by the second D flip-flop after encoding and then output;

[0022] The output terminal of the second cycle adjustment circuit is connected to the second D flip-flop.

[0023] The first coarse adjustment circuit includes a plurality of delay units for adjusting the circuit delay.

[0024] Preferably, the first coarse adjustment circuit specifically includes: a first comparator, a second comparator, a first NOT gate, a second NOT gate, a first D register, a second D register, an adder, and a D / A converter;

[0025] The output terminal of the first comparator is connected to the input terminal of the first NOT gate;

[0026] The output terminal of the first NOT gate is connected to the D terminal of the first D register;

[0027] The CK terminal of the first D register is connected to the clock frequency, and the Q terminal is connected to the adder;

[0028] The output terminal of the second comparator is connected to the input terminal of the second NOT gate;

[0029] The output terminal of the second NOT gate is connected to the D terminal of the second D register;

[0030] The CK terminal of the second D register is connected to the clock frequency, and the Q terminal is connected to the adder;

[0031] The output terminal of the adder is connected to the input terminal of the D / A converter.

[0032] Preferably, the analog amplification circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, and a first triode;

[0033] The collector of the first triode is connected to the second end of the third resistor, the emitter is connected to the first end of the fourth resistor and the first plate of the third capacitor, and the base is connected to the first capacitor;

[0034] The second end of the first resistor is connected to the first end of the second resistor, and the first end is connected to VCC;

[0035] The second end of the second resistor is grounded;

[0036] The second end of the fourth resistor is grounded;

[0037] The second plate of the third capacitor is grounded;

[0038] The first plate of the second capacitor is connected to the collector, and the second plate is connected to the first end of the fifth resistor;

[0039] The second end of the fifth resistor is grounded;

[0040] The first end of the third resistor is connected to VCC.

[0041] A control method based on an LPDDR5 / 5X PHY IO circuit is applied to an LPDDR5 / 5X PHY IO circuit, and includes:

[0042] The transmitter converts a low-speed parallel signal into a high-speed serial signal and sends it to the receiver;

[0043] The receiver converts the received high-speed serial signal into a low-speed parallel signal and sends it to the digital end.

[0044] An electronic device includes: a processor and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a control method based on an LPDDR5 / 5X PHY IO circuit.

[0045] A computer-readable storage medium stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is caused to execute a control method based on an LPDDR5 / 5X PHY IO circuit.

[0046] The beneficial effects of the present invention are as follows: 1. For the transmitter circuit, by adjusting the CDL module from the original data path to the clock path, the present invention can greatly reduce the number of stages on the data path, thereby reducing the influence of ISI, improving jitter (DJ), and improving signal quality. 2. For the receiver circuit, by adjusting the CDL module from the original data path to the clock path, the present invention can greatly reduce the number of stages on the data path, improve the data period, thereby improving jitter (DDJ) caused by periodic errors and improving signal quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings herein are incorporated into the specification and form a part of the specification, indicating embodiments consistent with the present invention, and are used together with the specification to explain the principles of the present invention.

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 Schematic diagram of a transmitter circuit structure of a LPDDR5 / 5X PHY IO circuit according to the present invention;

[0050] Figure 2 Schematic diagram of a receiver circuit structure of a LPDDR5 / 5X PHY IO circuit according to the present invention;

[0051] Figure 3 Schematic diagram of a coarse adjustment circuit structure according to the present invention;

[0052] Figure 4 Schematic diagram of an analog amplifier circuit structure according to the present invention;

[0053] Figure 5 Schematic diagram of a hardware structure of an electronic device according to the present invention;

[0054] Figure 6 Schematic diagram of a traditional transmitter circuit structure according to the present invention;

[0055] Figure 7 Schematic diagram of a traditional receiver circuit structure according to the present invention. Detailed implementation manners

[0056] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0057] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the drawings). If the specific posture changes, the directional indications will also change accordingly.

[0058] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0059] In traditional transmitter circuits, the CDL circuit is placed on the data path to adjust the delay of the data, so as to meet the required design requirements. As is well known, a large number of delay units are included in the CDL. When data passes through the CDL, it is equivalent to passing through these delay units as well. As the number of delay units passed through increases, jitter will accumulate, increasing the impact of ISI. At the same time, it will also increase the difficulty of adjusting the data period at the full process corner. The variation of the data period will also affect DDJ, thus deteriorating the signal quality. Similarly, the receiver (RX) has similar defects.

[0060] For the transmitter circuit, by adjusting the CDL module from the original data path to the clock path, the present invention can greatly reduce the number of stages on the data path, thereby reducing the impact of ISI, improving jitter (DJ), and improving signal quality. For the receiver circuit, by adjusting the CDL module from the original data path to the clock path, the present invention can greatly reduce the number of stages on the data path, improve the data period, and thus improve the jitter (DDJ) caused by periodic errors, improving signal quality.

[0061] Embodiment 1

[0062] A kind of LPDDR5 / 5X PHY IO circuit, referring to Figure 1 , including: a receiver circuit;

[0063] The receiver circuit includes: a first coarse adjustment circuit;

[0064] The receiver circuit plays a crucial role in the IO architecture, ensuring that data can be accurately and efficiently transmitted from external devices to the CPU. Specifically, the working principle of the receiver circuit includes the following aspects: Data transmission: Through the front-end bus and the back-end bus, the receiver circuit is responsible for transmitting the data of external devices to the CPU, or transmitting the data of the CPU to external devices. These buses are channels for high-speed data transmission, ensuring the rapid exchange of data. Signal processing: The receiver circuit also needs to process operations such as signal amplification and filtering to ensure the stability and accuracy of the signal. This includes the amplification of the input signal and the suppression of noise to ensure the integrity and reliability of the data. Clock synchronization: In multi-device communication, the receiver circuit also needs to handle the clock synchronization problem, ensuring that each device exchanges data on the same time basis, avoiding data conflicts and losses.

[0065] The input end of the first coarse adjustment circuit is connected to the analog amplification circuit, and the output end is connected to the first D-flip flop;

[0066] The first coarse adjustment circuit is located on the clock path.

[0067] The difference between the clock path and the data path lies in the type of signal, transmission method and application scenario. The clock path refers to the path of the clock signal from the source to the register clock pin. In FPGA, the clock signal is usually provided by an external crystal oscillator, and after being processed by the internal phase-locked loop (PLL), it is distributed to each register that needs to be synchronized. The transmission of the clock path needs to ensure the stability and accuracy of the clock signal, because clock deviation, jitter and temperature drift will affect the correct sampling of data. The data path refers to the process of data transmission from the output pin of one register to the input pin of another register. Data may pass through programmable interconnects and combinational logic during transmission, so the transmission time will be affected by wiring delays and logic gate delays. The key to the data path is to ensure that the data is stable before the rising edge of the clock arrives and remains stable for enough time to meet the setup time and hold time requirements of the register.

[0068] Inter-Symbol Interference (ISI) refers to the situation in digital communication systems where the waveforms of the previous and next symbols are distorted and widened due to the unsatisfactory overall transmission characteristics of the system, causing the tail of the waveform of the previous symbol to spread to the sampling time of the current symbol, thereby interfering with the decision of the current symbol. This interference is different from additive noise, a multiplicative interference. The main cause of inter-symbol interference is the unsatisfactory overall transmission characteristics of the system, which causes the signal waveform to be distorted and widened. Specifically, when the signal passes through the transmission medium, due to the different frequency components of the signal, some frequency components will be subject to greater attenuation or phase changes, resulting in waveform distortion. This distorted waveform will continue to the sampling time of the next symbol, interfering with the decision of the next symbol. The impact of inter-symbol interference is mainly reflected in the increase in the bit error rate of the signal, resulting in a decrease in communication quality.

[0069] In the embodiment of the present invention, by adjusting the coarse adjustment circuit from the original data path to the clock path, the number of stages on the data path can be greatly reduced, thereby reducing the impact of ISI, improving jitter (DJ), and improving signal quality.

[0070] Preferably, reference Figure 2 , further comprising: a transmitter circuit;

[0071] The transmitter circuit includes: a second coarse adjustment circuit;

[0072] The input end of the second coarse adjustment circuit is connected to the second D-flip-flop, and the output end is connected to the driving circuit;

[0073] A second coarse tuning circuit is located in the clock path.

[0074] The working principle of the transmitter circuit mainly includes the following steps: Signal generation: First, generate the signal to be transmitted. Modulation: Modulate the signal to a specific frequency, usually using methods such as amplitude modulation (AM), frequency modulation (FM), or phase modulation (PM). Power amplification: Enhance the power of the signal to ensure the transmission distance and stability. Transmission: Radiate the modulated signal through the antenna. The transmitter circuit realizes the data buffering function to ensure the speed matching between the high-speed CPU and the slow peripheral devices, and avoid transmission errors caused by speed mismatch. The transmitter circuit performs signal conversion, including digital-to-analog conversion, serial-to-parallel format conversion, and logic level conversion, to ensure compatibility between different devices and the accuracy of data transmission. The transmitter circuit realizes the interrupt control function, enabling the CPU and external devices to work in parallel and automatically handling faults when needed, improving the stability and response speed of the system. The transmitter circuit is also responsible for the timing of the system and the counting and control of external events, ensuring that the system operates according to the predetermined time, and improving the automation and accuracy of the system. DMA transfer: The transmitter circuit supports direct memory access (DMA) transfer to realize the direct exchange of information between the memory and I / O devices, improving the efficiency and speed of data transmission. In the communication field, the transmitter circuit ensures the communication protocol standards between different devices and the reliability of data transmission through signal conversion and interrupt control functions. In data processing, the transmitter circuit ensures that the system performs data processing and task scheduling according to the predetermined time through the timing and counting function, improving the automation and accuracy of the system.

[0075] Preferably, the receiver circuit further includes: an analog amplification circuit, a first D flip-flop, and a first cycle adjustment circuit;

[0076] The output terminal of the first cycle adjustment circuit is connected to the first D flip-flop;

[0077] The input terminal of the analog amplification circuit is connected to the PAD, and the output terminal is connected to the first coarse adjustment circuit;

[0078] The PAD side of the IO architecture refers to the input / output interface part in the integrated circuit, including the bonding pad (PAD) and related circuits, power supply lines, and ground lines. These components together constitute the interface between the integrated circuit and the external world, realizing the functions of data input and output. In the integrated circuit, the PAD is the metal wire connection point connecting the chip and the package socket, usually a rectangle with a size of dozens of micrometers. To prevent short circuits of the gold wires, a minimum distance needs to be maintained between the PADs, and this distance depends on the package form 2. Most I / O PADs appear in the form of a standard cell structure, with an I / O library, usually having a shape with equal height but unequal width. The IO Ring and Pad Ring respectively refer to the rings composed of IO and Pad. Generally, the input / output ports are composed of IO and Pad together.

[0079] The first D-flip flop is connected to the cycle adjustment circuit.

[0080] The main function of the cycle adjustment circuit is to adjust the working cycle of the circuit to ensure stable operation of the circuit under different working conditions. The cycle adjustment circuit is an electronic device that can adjust the working cycle of the circuit as needed. It realizes the adjustment of the circuit working cycle by controlling the switching state of the circuit, so as to meet different working requirements. The cycle adjustment circuit usually consists of a control circuit and an execution circuit. The control circuit is responsible for generating control signals, and the execution circuit performs switching operations according to the control signals. The main functions of the cycle adjustment circuit of the IO architecture include the following aspects: Data buffering and latching function: The cycle adjustment circuit can provide data buffering and latching functions to ensure smooth data transmission between the CPU and peripherals and avoid data loss or conflicts. Signal level conversion function: The circuit can convert different signal levels to adapt to the voltage and current requirements between the CPU and peripherals to ensure correct signal transmission. Data format conversion function: The cycle adjustment circuit can realize data format conversion, such as serial-to-parallel conversion, to meet different data transmission requirements. Interrupt management function: Through the interrupt management function, the cycle adjustment circuit can realize the parallel operation of the CPU and external devices and perform fault handling when needed to improve the response speed and stability of the system. Timing and counting function: The cycle adjustment circuit can also realize the timing of the system and the counting of external events to ensure accurate timing and event control of the system. In some cases, the cycle adjustment circuit also has an isolation function to ensure the stable operation of the system in different environments.

[0081] Preferably, the transmitter circuit further includes: a drive circuit, a second D-flip flop, and a second cycle adjustment circuit;

[0082] The output terminal of the second D-flip flop is connected to the input terminal of the drive circuit;

[0083] The output terminal of the drive circuit is connected to the PAD and is used to receive the signal output after being encoded by the second D-flip flop;

[0084] The output terminal of the second cycle adjustment circuit is connected to the second D-flip flop.

[0085] A D-flip flop usually has two inputs: a clock (CLK) input and a data (D) input. It also has two outputs: a main output Q and a complement output Q' of Q. When the clock signal is high, the D-flip flop is in the hold state and the input signal is locked; when the clock signal is low, the input signal is transmitted to the output terminal 4. This circuit controlled by the clock is called a sequential circuit because the state of the D-flip flop is controlled by the clock signal and can maintain a certain level.

[0086] The functions of D flip - flops in the IO architecture mainly include the following aspects: Data storage: A D flip - flop is a device with memory function that can store 1 - bit binary data. It has two stable states, namely 0 and 1, and can flip from one state to another under the action of external signals. Provide the state that the peripheral data is ready: D flip - flops can be used to provide the state that the peripheral data is ready, ensuring the accuracy and reliability of data during transmission. Constitute the basic unit of sequential circuits: D flip - flops are the basic logic units that constitute various sequential circuits and are widely used in digital systems and computers. It can maintain a certain level under the control of a clock signal, so it is called a circuit with memory function.

[0087] The first coarse - tuning circuit includes multiple delay units for adjusting circuit delay.

[0088] The function of the delay unit is to limit the magnitude of the current, thereby controlling the circuit delay time.

[0089] The function of the delay unit is to increase the signal delay time to repair the hold - time violation problem of the clock signal. Compared with a buffer unit, the delay unit can provide more delay, thus repairing the hold - time violation problem of the clock signal. Specifically, the delay unit ensures that the signal remains valid when it reaches the receiving end by increasing the signal propagation time, thereby meeting the hold - time requirements of the clock signal. The delay unit can ensure the stability and reliability of the clock signal by increasing the signal propagation time.

[0090] Preferably, referring to Figure 3 , the first coarse - tuning circuit specifically includes: a first comparator, a second comparator, a first NOT gate, a second NOT gate, a first D register, a second D register, an adder, and a D / A converter;

[0091] The output terminal of the first comparator is connected to the input terminal of the first NOT gate;

[0092] The first comparator is used to compare the magnitudes of the currents or voltages at two input terminals and output different voltage results at the output terminal according to the comparison result. The first comparator has two input terminals (such as Vi+ and Vi - ) and one output terminal (Vout). The input terminals receive analog signals and the output terminal outputs digital signals, usually having two states: high level or low level. The comparator generates a high - level or low - level signal at the output terminal by comparing the magnitudes of the voltages or currents at the two input terminals. The state of the output terminal depends on the high - low relationship of the voltages at the two input terminals. When the voltage at the positive input terminal is higher than the voltage at the negative input terminal, a high level is output; otherwise, a low level is output.

[0093] The output terminal of the first NOT gate is connected to the D terminal of the first D register;

[0094] The CK terminal of the first D register is connected to the clock frequency, and the Q terminal is connected to the adder;

[0095] The adder is used to generate the sum of numbers. The adder is a digital circuit used to perform digital addition calculations. It can be a half adder or a full adder, depending on its design and function.

[0096] The output terminal of the second comparator is connected to the input terminal of the second NOT gate;

[0097] The output terminal of the second NOT gate is connected to the D terminal of the second D register;

[0098] The CK terminal of the second D register is connected to the clock frequency, and the Q terminal is connected to the adder;

[0099] The output terminal of the adder is connected to the input terminal of the D / A converter.

[0100] The D / A converter is a circuit device that converts digital quantities into analog quantities. It is mainly used in various application scenarios that require the conversion between digital signals and analog signals, such as data transmission systems, automatic test equipment, medical information processing, digitalization of TV signals, processing and recognition of image signals, digital communication, and information processing. The basic working principle of the D / A converter is to convert each bit that makes up the digital code into a corresponding analog quantity according to its "weight", and then add these analog quantities to finally obtain an analog quantity proportional to the digital quantity. Its structure usually includes a data latch, electronic switches, a bit-weight network, a summing operational amplifier, and a reference voltage source (or constant current source). Specifically, each digit of the digital quantity stored in the data latch controls the corresponding electronic switch, so that the bits with a digit of 1 generate current values proportional to their bit weights on the bit-weight network, and then the operational amplifier sums up the current values and converts them into voltage values. The main components of the D / A converter include a weighted resistor network, an operational amplifier, a reference power supply, and analog switches. This device plays a key role in many electronic systems, especially in occasions where digital signals need to be converted into analog signals for further processing or display.

[0101] Preferably, referring to Figure 4 , the analog amplification circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, and a first triode;

[0102] The collector of the first triode is connected to the second end of the third resistor, the emitter is connected to the first end of the fourth resistor and the first plate of the third capacitor, and the base is connected to the first capacitor;

[0103] The second terminal of the first resistor is connected to the first terminal of the second resistor, and the first terminal is connected to VCC;

[0104] The second terminal of the second resistor is grounded;

[0105] The second terminal of the fourth resistor is grounded;

[0106] The second plate of the third capacitor is grounded;

[0107] The first plate of the second capacitor is connected to the collector, and the second plate is connected to the first terminal of the fifth resistor;

[0108] The second terminal of the fifth resistor is grounded;

[0109] The first terminal of the third resistor is connected to VCC.

[0110] The functions of the analog amplifier circuit include signal amplification, signal conditioning, impedance matching, and signal driving. Signal amplification: The basic function of the analog amplifier circuit is to amplify a weak input signal to the required amplitude so that the signal can be more easily processed by subsequent circuits or drive external devices. Gain is a key parameter to measure the amplification ability of the amplifier, indicating the amplitude ratio relationship between the output signal and the input signal. Signal conditioning: In addition to the simple amplification function, the analog amplifier can also condition the signal, including filtering, level conversion, etc. For example, an operational amplifier (op-amp) can achieve various functions such as positive amplification, inverting amplification, and filtering through different configurations. The filtering function can help remove noise and unwanted frequency components in the signal, improving the signal-to-noise ratio and purity of the signal. Impedance matching: The analog amplifier can also be used to achieve impedance matching, that is, to adjust the input and output impedances of the circuit to optimize signal transmission and power conversion efficiency. In some applications, such as audio amplifiers, impedance matching is crucial for ensuring sound quality. Signal driving: The amplified signal can drive various loads, and the analog amplifier can provide sufficient power and current to drive these loads to make them work properly.

[0111] Embodiment 2

[0112] A control method based on the LPDDR5 / 5X PHY IO circuit is applied to a circuit based on the LPDDR5 / 5X PHY IO, including:

[0113] The transmitter converts the low-speed parallel signal into a high-speed serial signal and sends it to the receiver;

[0114] The low-speed parallel signal refers to a parallel data transmission method with a relatively low transmission rate, which is usually used to connect multiple devices or components and transmit multiple data bits simultaneously. This transmission method transmits data through multiple data lines at the same time, each line representing a data bit, and the data is read and processed at the same time.

[0115] A high-speed serial signal refers to a data signal transmitted through serial communication. Compared with traditional parallel transmission, serial transmission uses a single data line, avoiding crosstalk problems between multiple data lines in parallel transmission, thereby improving the transmission speed and anti-interference ability. The serial signal transmits data through a single data line, avoiding crosstalk problems between multiple data lines in parallel transmission. In addition, the serial signal can adopt technologies such as differential signals, clock-data recovery (CDR), and channel equalization to further improve the transmission rate. The differential signal transmits the signal through two lines, which can effectively resist noise and interference, while the CDR technology can eliminate clock skew and reduce electromagnetic interference, thereby improving the transmission rate. The serial signal greatly enhances its anti-interference ability by adopting technologies such as differential signals and low-voltage differential signals. The differential signal transmits opposite signals through two lines, which can effectively cancel external noise and reduce interference. In addition, the serial signal can also eliminate clock skew through the clock-data recovery (CDR) technology, further reducing electromagnetic interference. The serial signal reduces electromagnetic interference through the CDR technology. The CDR technology can eliminate clock skew, avoiding electromagnetic interference problems caused by transmitting high-frequency clock signals on the PCB or wires, thereby improving the stability and reliability of the system.

[0116] The receiver converts the received high-speed serial signal into a low-speed parallel signal and sends it to the digital end.

[0117] Embodiment 3

[0118] An electronic device includes: a processor and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a control method based on the LPDDR5 / 5X PHY IO circuit.

[0119] Reference Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled through a connector, which includes various interfaces, transmission lines, or buses, etc. The embodiments of the present invention do not limit this. It should be understood that in various embodiments of the present invention, coupling refers to the mutual connection through a specific method, including directly connected or indirectly connected through other devices. For example, it can be connected through various interfaces, transmission lines, buses, etc.

[0120] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0121] The memory 22 can be used to store computer program instructions and various computer program codes including the program codes for executing the solution of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), or compact disc read-only memory (CD-ROM), and the memory is used for relevant instructions and data.

[0122] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0123] Embodiment 4

[0124] A computer-readable storage medium stores a computer program, and the computer program includes program instructions. When the program instructions are executed by a processor of an electronic device, the processor is enabled to execute a method for controlling an LPDDR5 / 5X PHY IO circuit.

[0125] For the transmitter circuit, by adjusting the CDL module from the original data path to the clock path, the present invention can greatly reduce the number of stages on the data path, thereby reducing the influence of ISI, improving the jitter (DJ), and improving the signal quality. For the receiver circuit, by adjusting the CDL module from the original data path to the clock path, the present invention can greatly reduce the number of stages on the data path, improve the data period, thereby improving the jitter (DDJ) caused by periodic errors and improving the signal quality.

[0126] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A LPDDR5 / 5X PHY IO circuit, characterized in that, Comprising: A receiver circuit; The receiver circuit includes: a first coarse-tuning circuit; The input end of the first coarse-tuning circuit is connected to an analog amplification circuit, and the output end is connected to a first D flip-flop; The first coarse-tuning circuit is located in the clock path; The first coarse-tuning circuit specifically includes: a first comparator, a second comparator, a first NOT gate, a second NOT gate, a first D register, a second D register, an adder, and a D / A converter; The output end of the first comparator is connected to the input end of the first NOT gate; The output end of the first NOT gate is connected to the D end of the first D register; The CK end of the first D register is connected to a clock signal, and the Q end is connected to the adder; The output end of the second comparator is connected to the input end of the second NOT gate; The output end of the second NOT gate is connected to the D end of the second D register; The CK end of the second D register is connected to a clock signal, and the Q end is connected to the adder; The output end of the adder is connected to the input end of the D / A converter.

2. The LPDDR5 / 5X PHY IO circuit according to claim 1, wherein Also comprising: A transmitter circuit; The transmitter circuit includes: a second coarse-tuning circuit; The input end of the second coarse-tuning circuit is connected to a second D flip-flop, and the output end is connected to a driving circuit; The second coarse-tuning circuit is located in the clock path; The structure of the second coarse-tuning circuit is the same as that of the first coarse-tuning circuit.

3. The one kind of LPDDR5 / 5X PHY IO circuit according to claim 1, characterized in that The receiver circuit further includes: an analog amplification circuit, a first D flip-flop, and a first period adjustment circuit; The output end of the first period adjustment circuit is connected to the first D flip-flop; The input end of the analog amplification circuit is connected to a PAD, and the output end is connected to the first coarse-tuning circuit; The first D flip-flop is connected to the first period adjustment circuit.

4. The LPDDR5 / 5X PHY IO circuit according to claim 2, wherein The transmitter circuit further includes: a driving circuit, a second D flip-flop, and a second period adjustment circuit; The output end of the second D flip-flop is connected to the input end of the driving circuit; The output end of the driving circuit is connected to a PAD, and is used to output the signal received from the output of the second D flip-flop after encoding processing; The output end of the second period adjustment circuit is connected to the second D flip-flop.

5. A LPDDR5 / 5X PHY IO circuit according to claim 1, wherein The first coarse-tuning circuit includes a plurality of delay units for adjusting the circuit delay.

6. The LPDDR5 / 5X PHY IO circuit according to claim 3, wherein, The analog amplification circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor, a third capacitor, and a first triode; The collector of the first triode is connected to the second end of the third resistor, the emitter is connected to the first end of the fourth resistor and the first plate of the third capacitor, and the base is connected to the first capacitor; The second end of the first resistor is connected to the first end of the second resistor, and the first end is connected to VCC; The second end of the second resistor is grounded; The second end of the fourth resistor is grounded; The second plate of the third capacitor is grounded; The first plate of the second capacitor is connected to the collector, and the second plate is connected to the first end of the fifth resistor; The second end of the fifth resistor is grounded; The first end of the third resistor is connected to VCC.

7. A control method for an LPDDR5 / 5X PHY IO circuit, applied to an LPDDR5 / 5X PHY IO circuit according to any one of claims 1-6, characterized in that Comprising: The transmitter converts a low-speed parallel signal into a high-speed serial signal and sends it to the receiver; The receiver converts the received high-speed serial signal into a low-speed parallel signal and sends it to the digital end.

8. An electronic device, characterized in that, Including: A processor and a memory, where the memory is used to store computer program code, and the computer program code includes computer instructions. When the processor executes the computer instructions, the electronic device executes a method for controlling an LPDDR5 / 5X PHY IO circuit as claimed in claim 7.

9. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by the processor of the electronic device, the processor is caused to execute a method for controlling an LPDDR5 / 5X PHY IO circuit as claimed in claim 7.

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