System and method for transmitting PCM (Pulse Code Modulation) data through synchronous serial interface of portable mobile communication equipment

Abstract

The invention discloses a system and a method for transmitting PCM (Pulse Code Modulation) data through a synchronous serial interface of portable mobile communication equipment, and relates to the technical field of communication. The system comprises a synchronous serial interface module, a PCM receiving dual-port RAM, a PCM sending dual-port RAM and a PCM interface module. During receiving, the PCM interface module completes PCM interface data serial-parallel conversion, and stores the data to the PCM receiving dual-port RAM according to a PCM time slot and a frame sequence; and the synchronous serial interface module reads data regularly and sends the data to the main control chip. During sending, the main control chip sends data and addresses regularly, the synchronous serial interface module extracts the data and the addresses and stores the data to the corresponding addresses of the PCM sending dual-port RAM, and the PCM interface module reads the data of the corresponding addresses before each time slot arrives and sends the data according to the time slots and the frame sequence. According to the invention, the interface requirement on the main control chip is reduced, and the type selection range of the main control chip is expanded; and multi-frame data is processed regularly, so that the occupancy rate of a main control chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a system and method for transmitting PCM data via a synchronous serial interface of a portable mobile communication device. Background Art

[0002] Portable mobile communication equipment such as portable boxes and command boxes are the core equipment of on-site emergency command and communication solutions. They can unify the command and dispatch of different communication terminals on site. They are small in size, light in weight, highly integrated, easy to carry and quickly deployed. PCM (Pulse Code Modulation) is a voice coding method used by portable mobile communication equipment. It digitizes analog signals through pulse sampling, digital quantization, and coding.

[0003] Portable mobile communication devices usually process voice through the main control chip and audio codec chip, where the main control chip processes digital voice, the audio codec chip completes the conversion from analog voice to digital voice, and the main control chip and the audio codec chip transmit data through the PCM interface. The PCM interface is not a common peripheral interface, and is usually only available in dedicated voice processing chips. With the development of technology, the performance of general-purpose processors is becoming more and more powerful, but general-purpose processors generally do not have a PCM interface. The synchronous serial interface is a common peripheral interface of general-purpose processors. How to achieve communication between the synchronous serial interface and the PCM interface has become a problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the present invention proposes a system and method for transmitting PCM data via a synchronous serial interface of a portable mobile communication device. The present invention reduces the interface requirements for the main control chip, expands the selection range of the main control chip, and processes multiple frames of data at a regular time, reducing the occupancy rate of the main control chip.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] A system for transmitting PCM data via a synchronous serial interface of a portable mobile communication device, which is used to realize communication between the synchronous serial interface of a main control chip and the PCM interface of an audio codec chip in a portable mobile communication device; it is realized based on a programmable logic device, and the programmable logic device includes a synchronous serial interface module, a PCM receiving dual-port RAM, a PCM sending dual-port RAM, and a PCM interface module;

[0007] The PCM receiving dual-port RAM and the PCM transmitting dual-port RAM are respectively connected to the synchronous serial interface module and the PCM interface module through the address data bus, and are used for storing the transmitting information data;

[0008] The synchronous serial interface module receives the sampling clock MCLK and the chip select signal nCS of the master chip, the synchronous serial interface clock signal SCLK and the master output data signal SDI, and sends the master input data signal SDO to the master chip; in addition, the synchronous serial interface module also receives information data from the PCM dual-port RAM, and sends the information data stored in the dual-port RAM to the PCM;

[0009] The PCM interface module receives the slave output data signal PCMR of the audio codec chip, and sends the PCM interface clock signal PCLK, the frame synchronization signal FSYNC and the slave input data signal PCMX to the audio codec chip; in addition, the PCM interface module also receives information data from the PCM sending dual-port RAM, and stores information data in the PCM receiving dual-port RAM.

[0010] Furthermore, the PCM receiving dual-port RAM and the PCM transmitting dual-port RAM are internally divided into two areas of equal size, one area stores the information data currently being received, and the other area stores the information data of the previous cycle. The synchronous serial interface or PCM interface receives the information data of the previous cycle, and the two areas are used alternately.

[0011] The method for transmitting PCM data via a synchronous serial interface of a portable mobile communication device is implemented based on any of the above-mentioned systems for transmitting PCM data via a synchronous serial interface of a portable mobile communication device; specifically, the method comprises the following steps:

[0012] Step 1, the system is powered on, and the synchronous serial interface module samples the chip select signal nCS and the synchronous serial interface clock signal SCLK according to the sampling clock MCLK to obtain the rising edge and falling edge of the chip select signal nCS and the synchronous serial interface clock signal SCLK;

[0013] Step 2: The main control chip sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and the synchronous serial interface module is in an idle state; the PCM interface module sends a periodic PCM interface clock signal PCLK and a frame synchronization signal FSYNC to the audio codec chip;

[0014] Step 3, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module, and the synchronous serial interface module is in a synchronous state after receiving the low-level chip select signal nCS;

[0015] Step 4, the master control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and at the rising edge or falling edge of the synchronous serial interface clock signal SCLK, sends the control word of the current cycle to the synchronous serial interface module through the master output data signal SDI; when the synchronous serial interface module recognizes the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the control word sent by the master control chip;

[0016] Step 5, after the main control chip sends the control word of the current cycle, it sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module. After the synchronous serial interface module receives the high-level chip select signal nCS and the synchronous serial interface clock signal SCLK, it extracts the control word received in the current cycle;

[0017] Step 6, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module. After receiving the low-level chip select signal nCS, the synchronous serial interface module judges the control word extracted in the current cycle. If the control word is a byte data preset to represent a read operation or a write operation, the synchronous serial interface module enters the address state, otherwise, an error is reported to the main control chip through the master input data signal SDO, and the module returns to step 2;

[0018] Step 7, the master control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and at the rising edge or falling edge of the synchronous serial interface clock signal SCLK, sends the address of the current cycle to the synchronous serial interface module through the master output data signal SDI according to the time slot and frame sequence; when the synchronous serial interface module recognizes the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the address sent by the master control chip;

[0019] Step 8, after the main control chip sends the address of the current cycle, it sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module. After the synchronous serial interface module receives the high-level chip select signal nCS and the synchronous serial interface clock signal SCLK, it extracts the address received in the current cycle;

[0020] Step 9, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module. After receiving the low-level chip select signal nCS, the synchronous serial interface module judges the address extracted in the current cycle. If the address is within the valid range, the synchronous serial interface module enters the data state; if the address is not within the valid range, an error is reported to the main control chip through the master-side input data signal SDO, and the process returns to step 2;

[0021] Step 10, if the control word is determined to be a read operation in step 6, then execute step 11; if the control word is determined to be a write operation in step 6, then execute step 12;

[0022] Step 11, the main control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module. The synchronous serial interface module receives the information data sent by the audio codec chip from the PCM dual-port RAM according to the address extracted in step 8. When the synchronous serial interface module identifies the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, the information data is sent to the main control chip through the master input data signal SDO. After the main control chip completes receiving the information data, it returns to execute step 2;

[0023] The specific process of the audio codec chip sending information data is as follows:

[0024] Step 1101, after the audio codec chip receives the rising edge of the frame synchronization signal FSYNC sent by the PCM interface module, it sends information data to the PCM interface module through the slave output data signal PCMR at the rising edge or falling edge of the PCM interface clock signal PCLK;

[0025] Step 1102, the PCM interface module stores the received information data into the PCM receiving dual-port RAM according to the time slot and frame sequence;

[0026] Step 12, the main control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and sends information data to the synchronous serial interface module through the master output data signal SDI. When the synchronous serial interface module identifies the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the information data sent by the main control chip, and stores the information data in the PCM sending dual-port RAM according to the address extracted in step 8; the PCM interface module sends the information data in the PCM sending dual-port RAM to the audio codec chip, and after the main control chip finishes sending the information data, it returns to execute step 2;

[0027] The process of the PCM interface module sending the information data in the PCM dual-port RAM to the audio codec chip is as follows:

[0028] Step 1201, the PCM interface module extracts information data in the PCM transmission dual-port RAM according to the time slot and frame sequence;

[0029] Step 1202, after the PCM interface module sends the high-level frame synchronization signal FSYNC to the audio codec chip, the PCM interface module sends information data to the audio codec chip via the slave input data signal PCMX at the rising edge or falling edge of the PCM interface clock signal PCLK.

[0030] Due to the adoption of the above technical solution, the beneficial effects of the present invention compared with the prior art are:

[0031] 1. The present invention can realize the communication between the synchronous serial interface of the main control chip and the PCM interface of the audio codec chip in the portable mobile communication device, thereby reducing the interface requirements for the main control chip and expanding the selection range of the main control chip.

[0032] 2. The present invention supports various PCM timings such as long frame mode, short frame mode and clock delay; and can realize the transmission of all PCM time slot data, not just the data of the effective time slot of the frame.

[0033] 3. The present invention can process multiple frames of data regularly and reduce the occupancy rate of the main control chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The figure is a schematic diagram of the overall structure of a system for transmitting PCM data via a synchronous serial interface of a portable mobile communication device according to an embodiment of the present invention.

[0035] Figure 2 This is a timing diagram of the PCM interface in an embodiment of the present invention.

[0036] Figure 3 4 is a timing diagram of a synchronous serial interface read operation in an embodiment of the present invention.

[0037] Figure 4 This is a timing diagram of a synchronous serial interface write operation in an embodiment of the present invention.

[0038] Figure 5 4 is a timing diagram of synchronous serial interface state transition in an embodiment of the present invention.

[0039] Figure 6 Schematic diagram of the state machine state transition process in an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0041] A system for transmitting PCM data via a synchronous serial interface of a portable mobile communication device is used to realize communication between the synchronous serial interface of a main control chip and the PCM interface of an audio codec chip in a portable mobile communication device; Figure 1 As shown, it is implemented based on a programmable logic device, and the programmable logic device includes a synchronous serial interface module, a PCM receiving dual-port RAM, a PCM sending dual-port RAM and a PCM interface module;

[0042] Specifically, the synchronous serial interface module uses a state machine model to process three consecutive read and write operations. The state machine includes four states: idle, synchronous, address and data. In the idle state, the synchronous serial interface read signal and write signal are invalid.

[0043] The PCM receiving dual-port RAM and the PCM transmitting dual-port RAM are respectively connected to the synchronous serial interface module and the PCM interface module through the address data bus, and are used for storing the transmitting information data;

[0044] The synchronous serial interface module receives the sampling clock MCLK and the chip select signal nCS of the master chip, the synchronous serial interface clock signal SCLK and the master output data signal SDI, and sends the master input data signal SDO to the master chip; in addition, the synchronous serial interface module also receives information data from the PCM dual-port RAM, and sends the information data stored in the dual-port RAM to the PCM;

[0045] The PCM interface module receives the slave output data signal PCMR of the audio codec chip, and sends the PCM interface clock signal PCLK, the frame synchronization signal FSYNC and the slave input data signal PCMX to the audio codec chip; in addition, the PCM interface module also receives information data from the PCM sending dual-port RAM, and stores information data in the PCM receiving dual-port RAM.

[0046] Furthermore, the PCM receiving dual-port RAM and the PCM transmitting dual-port RAM are internally divided into two areas of equal size, one area stores the information data currently being received, and the other area stores the information data of the previous cycle. The synchronous serial interface or PCM interface receives the information data of the previous cycle, and the two areas are used alternately.

[0047] A method for transmitting PCM data via a synchronous serial interface of a portable mobile communication device is implemented based on any of the above-mentioned systems for transmitting PCM data via a synchronous serial interface of a portable mobile communication device; specifically, Figure 5 , Figure 6 As shown, the following steps are included:

[0048] Step 1, the system is powered on, and the synchronous serial interface module samples the chip select signal nCS and the synchronous serial interface clock signal SCLK according to the sampling clock MCLK to obtain the rising edge and falling edge of the chip select signal nCS and the synchronous serial interface clock signal SCLK;

[0049] Step 2: The main control chip sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and the synchronous serial interface module is in an idle state; the PCM interface module sends a periodic PCM interface clock signal PCLK and a frame synchronization signal FSYNC to the audio codec chip;

[0050] Step 3, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module, and the synchronous serial interface module is in a synchronous state after receiving the low-level chip select signal nCS;

[0051] Step 4, the master control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and at the rising edge or falling edge of the synchronous serial interface clock signal SCLK, sends the control word of the current cycle to the synchronous serial interface module through the master output data signal SDI; when the synchronous serial interface module recognizes the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the control word sent by the master control chip;

[0052] Specifically, in this embodiment, the rising edge is used to identify the synchronous serial interface clock signal SCLK, so as to receive the control word; Figure 2 to Figure 5 The hyperbola in the figure indicates unlimited duration, and time is omitted;

[0053] Step 5, after the main control chip sends the control word of the current cycle, it sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module. After the synchronous serial interface module receives the high-level chip select signal nCS and the synchronous serial interface clock signal SCLK, it extracts the control word received in the current cycle;

[0054] Step 6, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module. After receiving the low-level chip select signal nCS, the synchronous serial interface module judges the control word extracted in the current cycle. If the control word is a byte data preset to represent a read operation or a write operation, the synchronous serial interface module enters the address state, otherwise, an error is reported to the main control chip through the master input data signal SDO, and the module returns to step 2;

[0055] Step 7, the master control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and at the rising edge or falling edge of the synchronous serial interface clock signal SCLK, sends the address of the current cycle to the synchronous serial interface module through the master output data signal SDI according to the time slot and frame sequence; when the synchronous serial interface module recognizes the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the address sent by the master control chip;

[0056] Specifically, in this embodiment, the rising edge is used to identify the synchronous serial interface clock signal SCLK to receive the address;

[0057] Step 8, after the main control chip sends the address of the current cycle, it sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module. After the synchronous serial interface module receives the high-level chip select signal nCS and the synchronous serial interface clock signal SCLK, it extracts the address received in the current cycle;

[0058] Step 9, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module. After receiving the low-level chip select signal nCS, the synchronous serial interface module judges the address extracted in the current cycle. If the address is within the valid range, the synchronous serial interface module enters the data state; if the address is not within the valid range, an error is reported to the main control chip through the master-side input data signal SDO, and the process returns to step 2;

[0059] Step 10, if the control word is determined to be a read operation in step 6, then execute step 11; if the control word is determined to be a write operation in step 6, then execute step 12;

[0060] Step 11, such as Figure 3 As shown, the main control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module. The synchronous serial interface module receives the information data sent by the audio codec chip from the PCM receiving dual-port RAM according to the address extracted in step 8. When the synchronous serial interface module identifies the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, the information data is sent to the main control chip through the master input data signal SDO. After the main control chip receives the information data, it returns to execute step 2;

[0061] Among them, Figure 2 As shown in the figure, the process of sending information data by the audio codec chip is as follows:

[0062] Step 1101, after the audio codec chip receives the rising edge of the frame synchronization signal FSYNC sent by the PCM interface module, it sends information data to the PCM interface module through the slave output data signal PCMR at the rising edge or falling edge of the PCM interface clock signal PCLK;

[0063] Step 1102, the PCM interface module stores the received information data into the PCM receiving dual-port RAM according to the time slot and frame sequence;

[0064] Step 12, such as Figure 4As shown, the main control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and sends information data to the synchronous serial interface module through the master-end output data signal SDI. When the synchronous serial interface module identifies the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the information data sent by the main control chip, and stores the information data in the PCM sending dual-port RAM according to the address extracted in step 8; the PCM interface module sends the information data in the PCM sending dual-port RAM to the audio codec chip, and after the main control chip finishes sending the information data, it returns to execute step 2;

[0065] Among them, Figure 2 As shown, the process of the PCM interface module sending the information data in the PCM dual-port RAM to the audio codec chip is as follows:

[0066] Step 1201, the PCM interface module extracts information data in the PCM transmission dual-port RAM according to the time slot and frame sequence;

[0067] Step 1202, after the PCM interface module sends the high-level frame synchronization signal FSYNC to the audio codec chip, the PCM interface module sends information data to the audio codec chip via the slave input data signal PCMX at the rising edge or falling edge of the PCM interface clock signal PCLK.

[0068] Specifically, in this embodiment, the rising edge is used to identify the synchronous serial interface clock signal SCLK, so as to send and receive information data; PORT0 and PORT1 represent different time slots;

[0069] In summary, the present invention reduces the interface requirements for the main control chip and expands the selection range of the main control chip; and processes multiple frames of data at a regular time to reduce the occupancy rate of the main control chip.

[0070] Those skilled in the art will appreciate that the embodiments described are intended to help readers understand the principles of the present invention, and should be understood that the scope of protection of the present invention is not limited to the embodiments described. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A system for transmitting PCM data via a synchronous serial interface of a portable mobile communication device, which is used to realize communication between the synchronous serial interface of a main control chip and the PCM interface of an audio codec chip in a portable mobile communication device; characterized in that: It is implemented based on a programmable logic device, which includes a synchronous serial interface module, a PCM receiving dual-port RAM, a PCM sending dual-port RAM and a PCM interface module; The PCM receiving dual-port RAM and the PCM transmitting dual-port RAM are respectively connected to the synchronous serial interface module and the PCM interface module through the address data bus, and are used for storing the transmitting information data; The synchronous serial interface module receives the sampling clock MCLK, the chip select signal nCS of the master chip, the synchronous serial interface clock signal SCLK, and the master output data signal SDI, and sends the master input data signal SDO to the master chip; In addition, the synchronous serial interface module also receives information data from the PCM dual-port RAM and sends information data stored in the dual-port RAM to the PCM; The PCM interface module receives the slave output data signal PCMR of the audio codec chip, and sends the PCM interface clock signal PCLK, the frame synchronization signal FSYNC and the slave input data signal PCMX to the audio codec chip; in addition, the PCM interface module also receives information data from the PCM sending dual-port RAM, and stores information data in the PCM receiving dual-port RAM.

2. The system for transmitting PCM data via a synchronous serial interface of a portable mobile communication device according to claim 1, characterized in that: The PCM receiving dual-port RAM and the PCM transmitting dual-port RAM are internally divided into two areas of equal size, one area stores the information data currently being received, and the other area stores the information data of the previous cycle. The synchronous serial interface or PCM interface receives the information data of the previous cycle, and the two areas are used alternately.

3. A method for transmitting PCM data via a synchronous serial interface of a portable mobile communication device, characterized in that: The system for transmitting PCM data via a synchronous serial interface of a portable mobile communication device according to claim 1 or 2 is implemented; specifically, the system comprises the following steps: Step 1, the system is powered on, and the synchronous serial interface module samples the chip select signal nCS and the synchronous serial interface clock signal SCLK according to the sampling clock MCLK to obtain the rising edge and falling edge of the chip select signal nCS and the synchronous serial interface clock signal SCLK; Step 2: The main control chip sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and the synchronous serial interface module is in an idle state; the PCM interface module sends a periodic PCM interface clock signal PCLK and a frame synchronization signal FSYNC to the audio codec chip; Step 3, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module, and the synchronous serial interface module is in a synchronous state after receiving the low-level chip select signal nCS; Step 4, the master control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and at the rising edge or falling edge of the synchronous serial interface clock signal SCLK, sends the control word of the current cycle to the synchronous serial interface module through the master output data signal SDI; when the synchronous serial interface module recognizes the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the control word sent by the master control chip; Step 5, after the main control chip sends the control word of the current cycle, it sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module. After the synchronous serial interface module receives the high-level chip select signal nCS and the synchronous serial interface clock signal SCLK, it extracts the control word received in the current cycle; Step 6, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module. After receiving the low-level chip select signal nCS, the synchronous serial interface module judges the control word extracted in the current cycle. If the control word is a byte data preset to represent a read operation or a write operation, the synchronous serial interface module enters the address state, otherwise, an error is reported to the main control chip through the master input data signal SDO, and the module returns to step 2; Step 7, the master control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and at the rising edge or falling edge of the synchronous serial interface clock signal SCLK, sends the address of the current cycle to the synchronous serial interface module through the master output data signal SDI according to the time slot and frame sequence; when the synchronous serial interface module recognizes the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the address sent by the master control chip; Step 8, after the main control chip sends the address of the current cycle, it sends a high-level chip select signal nCS and a synchronous serial interface clock signal SCLK to the synchronous serial interface module. After the synchronous serial interface module receives the high-level chip select signal nCS and the synchronous serial interface clock signal SCLK, it extracts the address received in the current cycle; Step 9, the main control chip sends a low-level chip select signal nCS to the synchronous serial interface module. After receiving the low-level chip select signal nCS, the synchronous serial interface module judges the address extracted in the current cycle. If the address is within the valid range, the synchronous serial interface module enters the data state; if the address is not within the valid range, an error is reported to the main control chip through the master-side input data signal SDO, and the process returns to step 2; Step 10, if the control word is determined to be a read operation in step 6, then execute step 11; if the control word is determined to be a write operation in step 6, then execute step 12; Step 11, the main control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module. The synchronous serial interface module receives the information data sent by the audio codec chip from the PCM dual-port RAM according to the address extracted in step 8. When the synchronous serial interface module identifies the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, the information data is sent to the main control chip through the master input data signal SDO. After the main control chip completes receiving the information data, it returns to execute step 2; The specific process of the audio codec chip sending information data is as follows: Step 1101, after the audio codec chip receives the rising edge of the frame synchronization signal FSYNC sent by the PCM interface module, it sends information data to the PCM interface module through the slave output data signal PCMR at the rising edge or falling edge of the PCM interface clock signal PCLK; Step 1102, the PCM interface module stores the received information data into the PCM receiving dual-port RAM according to the time slot and frame sequence; Step 12, the main control chip sends a synchronous serial interface clock signal SCLK to the synchronous serial interface module, and sends information data to the synchronous serial interface module through the master output data signal SDI. When the synchronous serial interface module identifies the rising edge or falling edge of the corresponding synchronous serial interface clock signal SCLK, it receives the information data sent by the main control chip, and stores the information data in the PCM sending dual-port RAM according to the address extracted in step 8; the PCM interface module sends the information data in the PCM sending dual-port RAM to the audio codec chip, and after the main control chip finishes sending the information data, it returns to execute step 2; The process of the PCM interface module sending the information data in the PCM dual-port RAM to the audio codec chip is as follows: Step 1201, the PCM interface module extracts information data in the PCM transmission dual-port RAM according to the time slot and frame sequence; Step 1202, after the PCM interface module sends the high-level frame synchronization signal FSYNC to the audio codec chip, the PCM interface module sends information data to the audio codec chip via the slave input data signal PCMX at the rising edge or falling edge of the PCM interface clock signal PCLK.

Images