PCIE bus interconnection transmission method for multiple processing nodes

Abstract

The PCIE bus interconnection transmission method for the multiple processing nodes is suitable for data transmission of an airborne embedded computer system, the computer is provided with an SOC chip, an exchange chip and a photoelectric transceiver, and the PCIE bus interconnection transmission method comprises the steps that the SOC chip is used for processing and controlling airborne data; the exchange chip is electrically connected with the SOC chip through the serial high-speed interface and is used for data exchange of the serial high-speed interface; the photoelectric transceiver is electrically connected with the switching chip through a serial high-speed interface and is used for converting an electric signal of the serial high-speed interface into an optical signal and communicating with external equipment through an optical fiber; the computer communicates with the external equipment through a serial high-speed interface, transmitted signals are optical signals, and when the optical signals are transmitted through the photoelectric transceiver, the optical signals are prolonged in an external optical fiber mode, so that long-distance transmission is realized, and the use efficiency of the system is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of embedded computer data processing, and in particular relates to a PCIE bus interconnection transmission method for multiple processing nodes. Background Art

[0002] With the complexity of airborne computer systems and changes in the military situation, the demand for the transmission of complex signals, high-speed lossless signal processing and transmission in airborne embedded computer systems in complex environments has increased. For a PCIE bus interconnection transmission method for multiple processing nodes in an airborne embedded computer system, its performance and environmental adaptability determine the task execution capability of the entire airborne computer system to a certain extent. In order to support the ever-increasing bandwidth requirements and other functional characteristics of the application end, high-speed interfaces such as PCIe are currently used in airborne embedded computer systems. The disadvantages are: the signal attenuation during long-distance transmission cannot meet the requirements of airborne embedded computer systems for high-speed transmission, which reduces the performance of embedded computer systems. Summary of the invention

[0003] In view of this, the PCIE bus interconnection transmission method for multiple processing nodes of the present invention solves the technical problem of low performance of embedded computer systems in the prior art.

[0004] A PCIE bus interconnection transmission method for multiple processing nodes is applicable to data transmission of an airborne embedded computer system, wherein the computer is provided with a SOC chip, a switching chip and an optoelectronic transceiver. The PCIE bus interconnection transmission method comprises:

[0005] The SOC chip is used for processing and controlling airborne data;

[0006] The switching chip is electrically connected to the SOC chip via a serial high-speed interface and is used for data exchange of the serial high-speed interface;

[0007] The optoelectronic transceiver is electrically connected to the switching chip via a serial high-speed interface, and is used to convert the electrical signal of the serial high-speed interface into an optical signal, and communicate with an external device via an optical fiber;

[0008] The computer and the external device communicate with each other using a serial high-speed interface, and the transmitted signal is an optical signal. When the optical signal is transmitted through an optoelectronic transceiver, it is extended by an external optical fiber to achieve long-distance transmission.

[0009] The technical beneficial effects of the present invention are:

[0010] On the basis of not changing the PCIe protocol structure, the PCIe exchange of multiple master nodes and the transmission of PCIe signals by optical signals are adopted, which has certain flexibility and improves the performance of the embedded computer system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0012] Figure 1 A PCIe system composition diagram according to an embodiment of the present invention;

[0013] Figure 2 A diagram showing the composition of a multi-master node interconnection switching system according to an embodiment of the present invention;

[0014] Figure 3 This is a composition diagram of a dynamically configurable PCIe system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0016] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0017] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0018] like Figures 1 to 3 The PCIE bus interconnection transmission method of multiple processing nodes shown is suitable for data transmission of an airborne embedded computer system. The computer is provided with a SOC chip, a switching chip and an optoelectronic transceiver. The PCIE bus interconnection transmission method includes:

[0019] S101: SOC chip is a processor used for calculation, capable of processing and controlling airborne data;

[0020] S102: The switching chip is electrically connected to the SOC chip via a serial high-speed interface for data exchange via the serial high-speed interface;

[0021] S103: The optoelectronic transceiver is electrically connected to the switching chip via a serial high-speed interface, and is used to convert the electrical signal of the serial high-speed interface into an optical signal, and communicate with an external device via an optical fiber;

[0022] S104: The computer communicates with an external device using a serial high-speed interface, and the transmitted signal is an optical signal. When the optical signal is transmitted through an optoelectronic transceiver, it is extended by an external optical fiber to achieve long-distance transmission. When the optical signal is transmitted through an optoelectronic transceiver, it is extended by an external optical fiber, including that the serial high-speed interfaces of the SOC chip, the switching chip and the optoelectronic transceiver are all provided with a backup serial high-speed interface, and the functional parameters of the backup serial high-speed interface are the same as the functional parameters of the serial high-speed interface, and the computer runs health management software, which can monitor the optical signal output by the optoelectronic transceiver. If the light intensity of the optical signal output by the optoelectronic transceiver is lower than a threshold, the optical signal is switched to the backup serial high-speed interface for output, and the switching information is recorded.

[0023] As a specific implementation method provided in this case, the configuration of the traditional embedded computer processor as RC / EP has been determined by hardware and software at the beginning of the PCIe system construction, and the configuration of RC / EP cannot be changed. In order to realize the configuration change of RC / EP, specifically,

[0024] The SOC chip is configured with a processing end and a logic end. The logic end runs a data bit stream file and also includes a configuration method for the switch chip.

[0025] The processing end reads the data bit stream file stored in different data addresses, which includes the configuration information of the switching chip, and switches the SOC chip as the root endpoint RC and the terminal device EP. After the SOC chip reads the data bit stream file and the configuration information of the switching chip is determined, the SOC chip can work as the root endpoint RC or the terminal device EP, thus solving the problem that the configuration of RC / EP is fixed after the processor of the embedded computer is powered on and the RC / EP cannot be changed again.

[0026] As a specific implementation method provided in this case, the traditional PCIe bus is a point-to-point connection method, which cannot meet the communication design or requirements of complex airborne embedded computer systems. The solution to this problem is as follows:

[0027] Through the combination of non-transparent bridge and virtual switching network, multiple root endpoints RC can be configured for the switching chip, realizing the face-to-face connection of PCIe bus.

[0028] Loading a data bit stream file through the SOC chip, the data bit stream file includes configuration information for the switch chip, setting the switch chip to a non-transparent bridge mode, in which the switch chip can connect multiple root endpoints RC;

[0029] The switching chip is configured with a virtual switching network function, which enables any root endpoint RC to access the terminal device connected to the switching chip.

[0030] In the above description, the serial high-speed interface is a PCIe3.0 interface, that is, the backup serial high-speed interface is also a PCIe3.0 interface.

[0031] For example: This embodiment involves 4 PCIe devices, 25G Ethernet devices, including two ports, each port is an 8x PCIe3.0 interface, which is an electrical interface; the processor Z7 (corresponding to the SOC chip) is an RC port or EP port, which is an 8x PCIe2.0 interface, which is an electrical interface; the FPGA is an EP port, which is an 8x PCIe3.0 interface, which is an electrical interface. Other processor nodes are 8x PCIe3.0 interfaces, and the processor nodes can act as RCs. When the processor Z7 acts as an RC, the PCIe switch can be configured. The system supports the Z7 processor and other processing nodes as RCs, and also supports the switching of Z7 as RC and EP. The use of PCIe3.0 Ethernet switching can solve the interconnection problem of multiple devices. Other processing nodes can be interconnected with PCIe switching through optical signals, which effectively improves the transmission distance of PCIe signals, see Figure 2 As shown below:

[0032] Step 1: The Z7 processor is connected to the PCIe switch and starts as an RC in the initial state. It configures the PCIe switch and other endpoints connected to the PCIe switch as EPs and enumerates the devices on other ports.

[0033] Step 2: The PL part of the Z7 processor configures the PCIe switch as a non-transparent bridge. Through the non-transparent bridge, multiple hosts can access the EP node connected to the PCE switch.

[0034] Step 3: Configure the PCIe switch as a virtual switch, and realize information interaction between the two virtual switches by combining the virtual switch with the non-transparent bridge. This will enable the expansion of the PCIe bus to a higher level;

[0035] Step 4: Use Figure 3 As shown, the Z7 processor is dynamically configured. The BOOT file of the Z7 processor contains the FSBL target code. The boot address parameter is set in the FSBL, and the target code at different addresses of the FLASH can be read and loaded.

[0036] Step 5: In the Z7 processor, the logic of the PL side includes the configuration of the PCIe switch port. The settings of RC and EP can be selected through the target code fixed at different addresses of FLASH. Read the different configuration PL logic target codes stored in the FLASH location, load them, and configure the switch chip after loading to realize the role conversion of the SOC chip and other processing nodes from RC to EP, or from EP to RC;

[0037] Step 6: Use an optical module to convert the electrical PCIe signal output by the PCIe switch into an optical PCIe signal to achieve optical signal transmission of PCIe3.0 and effectively reduce the loss;

[0038] Step 7: The Z7 processor monitors the status of the PCIe exchange through the I2C interface, and timely identifies the link status information and port configuration information of the PCIe exchange.

[0039] The Z7 processor in the embodiment adopts the JFMQL100T900-N of Fudan Microelectronics, the PCIe exchange is implemented by the SM8748MP switch chip of Shenzhen Guowei, and the optical module is implemented by the HTA8546A-PJ-DB6BD-G of Factory 158. During the operation of JFMQL100T900-N, the following functions are mainly implemented: the PCIe exchange is configured through the PL end, mainly including the configuration of non-transparent bridge and transparent bridge, as well as the configuration of RC and EP. The status of the switching chip is read periodically through the I2C interface, including link status, traffic, bit error rate, etc.; the interrupt transaction reported by the switching chip is responded to and processed, and fault recovery is performed. During the system initialization or fault recovery process, the configuration management of the local PCIe exchange is completed.

[0040] During the operation of PCIe switch SM8748MP, the following functions are mainly realized: receiving the instructions of RC, completing the initial configuration of the chip, configuring it for virtualization, and combining it with the non-transparent bridge setting to realize the interaction of multiple master nodes. Reporting status information to JFMQL100T900-N through the I2C interface. The SM8748MP can be debugged and burned through the I2C interface to determine the initial state.

[0041] Overall technical effect:

[0042] PCIe optical signals are used to increase signal propagation distance, reduce signal attenuation, and achieve long-distance transmission; SOC processors are used as RCs to interconnect with PCIe switches, and SOC is used to configure PCIe switching to achieve flexible switching between RC and EP, and a non-transparent bridge combined with a virtual switching network is used to achieve the design of multiple RCs in the PCIe switching system. The flexibility and reliability of the PCIe system are improved, and there is no need to implement a complex PCIe system through hardware revision design, which reduces complexity and cost and improves flexibility and reliability.

[0043] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A PCIE bus interconnection transmission method for multiple processing nodes, suitable for data transmission of an airborne embedded computer system, characterized in that: The computer is provided with a SOC chip, a switching chip and an optoelectronic transceiver, and the PCIE bus interconnection transmission method comprises: The SOC chip is used for processing and controlling airborne data; The switching chip is electrically connected to the SOC chip via a serial high-speed interface and is used for data exchange of the serial high-speed interface; The optoelectronic transceiver is electrically connected to the switching chip via a serial high-speed interface, and is used to convert the electrical signal of the serial high-speed interface into an optical signal, and communicate with an external device via an optical fiber; The computer and the external device communicate with each other using a serial high-speed interface, and the transmitted signal is an optical signal. When the optical signal is transmitted through an optoelectronic transceiver, it is extended by an external optical fiber to achieve long-distance transmission.

2. The PCIE bus interconnection transmission method according to claim 1, characterized in that: When optical signals are transmitted through optoelectronic transceivers, they are extended by external optical fibers, including: The serial high-speed interfaces of the SOC chip, the switch chip and the optoelectronic transceiver are all provided with backup serial high-speed interfaces, and the functional parameters of the backup serial high-speed interfaces are the same as those of the serial high-speed interfaces; The computer runs health management software, which can monitor the optical signal output by the optoelectronic transceiver. If the light intensity of the optical signal output by the optoelectronic transceiver is lower than a threshold, the backup serial high-speed interface is switched to output the optical signal, and the switching information is recorded.

3. The PCIE bus interconnection transmission method according to claim 1, characterized in that: The SOC chip is configured with a processing end and a logic end, the logic end runs a data bit stream file, and also includes a configuration method for the switching chip, The data bit stream files stored in different data addresses are read by the processing end, the data bit stream files include configuration information for the switching chip, and the SOC chip is switched as the root endpoint RC and the end device EP.

4. The PCIE bus interconnection transmission method according to claim 3, characterized in that: The configuration method includes configuring a plurality of root endpoints RC for the switching chip by combining a non-transparent bridge with a virtual switching network, wherein: Loading a data bitstream file through the SOC chip, the data bitstream file includes configuration information for the switch chip, setting the switch chip to a non-transparent bridge mode, in which the switch chip can connect to multiple root endpoints RC; The switching chip is configured with the function of the virtual switching network, and the function can enable any root endpoint RC to access the terminal device connected to the switching chip.

5. The PCIE bus interconnection transmission method according to claim 4, characterized in that: The serial high-speed interface is a PCIe3.0 interface.

6. The PCIE bus interconnection transmission method according to claim 4, characterized in that: The backup serial high-speed interface is a PCIe3.0 interface.

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