Cross-domain time synchronization system and method and electronic medium

Abstract

The invention provides a cross-domain time synchronization system and method and an electronic medium, and the system comprises a first domain processor which is provided with a global counter and a first synchronization time module, and the first synchronization time module is in communication connection with the global counter; the second domain processor is internally provided with a second synchronization time module, and the second synchronization time module is in communication connection with the global counter; the first synchronization time module is in communication connection with the shared memory, and the second synchronization time module is in communication connection with the shared memory. According to the cross-domain time synchronization system, the cross-domain time synchronization method and the electronic medium provided by the invention, the global counter is arranged for timing, and unified timing is provided for the first domain processor and the second domain processor, so that the time error transmitted from the first domain processor to the second domain processor is corrected, and the time of the second domain processor is synchronized with the time of the control unit; meanwhile, the operation processing pressure of the first domain processor is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer networks, and in particular relates to a cross-domain time synchronization system, method and electronic medium. Background Art

[0002] The sensor processor is usually used to process data from various sensors. It collects and processes the data and transmits it to the application domain processor or communication domain processor for more advanced processing and application.

[0003] Currently, after the control unit obtains the time information, it transmits it to the sensor processor, which then sends it to the application domain processor or the communication domain processor. However, due to data transmission delays, processing speed differences and other reasons, the time obtained by the application domain processor or the communication domain processor may be inaccurate, and the computing and processing pressure of the sensor processor is increased. Summary of the invention

[0004] The purpose of the present invention is to propose a cross-domain time synchronization system, method and electronic medium, which solves the problem that the time obtained by the application domain processor or the communication domain processor is inaccurate and the operation processing pressure of the first domain processor is increased.

[0005] To this end, in a first aspect, the present invention provides a cross-domain time synchronization system, comprising:

[0006] A first domain processor, wherein a global counter and a first synchronization time module are provided in the first domain processor, and the first synchronization time module is communicatively connected with the global counter;

[0007] A second domain processor, wherein a second synchronization time module is provided in the second domain processor, the second synchronization time module is communicatively connected with the global counter, and the second domain processor has at least one;

[0008] A shared memory, wherein the first synchronization time module is communicatively connected to the shared memory, and the second synchronization time module is communicatively connected to the shared memory.

[0009] Optionally, a trigger module and a time synchronization interrupt processing module are provided in the first domain processor, the time synchronization interrupt processing module is communicatively connected with the trigger module, and the first synchronization time module is communicatively connected with the global counter through the time synchronization interrupt processing module.

[0010] Optionally, a communication module is provided in the first domain processor, and the communication module is communicatively connected with the first synchronization time module.

[0011] Optionally, a control unit is also included, and the control unit is communicatively connected to the first domain processor.

[0012] In a second aspect, a cross-domain time synchronization method is provided, comprising the following steps:

[0013] The first synchronization time module obtains the first time data, and the global counter generates the second time data;

[0014] The first synchronization time module reads the second time data, obtains shared data according to the first time data and the second time data, and stores the shared data in the shared memory;

[0015] The second synchronization time module reads the second time data from the global counter and reads the shared data from the shared memory at the same time, obtains the synchronization time data through the second time data and the shared data, and completes the time synchronization correction of the cross-domain processor.

[0016] Optionally, the step of the first synchronization time module obtaining the first time data includes:

[0017] When the first synchronization time module detects a change in the level signal, it reads the first time data; wherein the first time data is the time when the change in the level signal is detected.

[0018] Optionally, the step of generating the second time data by the global counter includes:

[0019] When the first synchronization time module detects a level signal change, the global counter generates an interrupt and generates second time data; wherein the second time data is the counting time when the global counter is interrupted.

[0020] Optionally, the first synchronization time module reads the second time data, and the step of obtaining shared data according to the first time data and the second time data includes:

[0021] The first synchronization time module reads the second time data, calculates the difference between the first time data and the second time data, and uses the difference between the first time data and the second time data and the current time of the global counter as shared data.

[0022] Optionally, the second domain processor reads the second time data and the shared data, and the step of obtaining the synchronized time data through the second time data and the shared data includes:

[0023] The second domain processor reads the second time data and the shared data, and obtains the synchronization time data by summing the second time data, the current time of the global counter, and the difference between the first time data and the second time data.

[0024] According to a third aspect, an electronic medium is provided, which includes a controller and a storage device, wherein the controller is electrically connected to the storage device, wherein a computer program executable by the controller is stored in the storage device, and wherein the computer program is executed by the controller to implement the cross-domain time synchronization method.

[0025] Beneficial effects:

[0026] (1) The present disclosure provides a cross-domain time synchronization system, method and electronic medium. By setting a global counter for timing, a unified timing is provided for a first domain processor and a second domain processor. The first domain processor calculates the difference between the first time data and the second time data and stores it in a shared memory. The second domain processor reads the difference between the first time data and the second time data and restores the time, thereby correcting the time error transmitted from the first domain processor to the second domain processor, synchronizing the time of the second domain processor with the control unit, ensuring that the time between the first domain processor and the second domain processor is the same, and reducing the computing pressure of the first domain processor.

[0027] (2) In the present disclosure, multiple second domain processors may be provided. The time of the multiple second domain processors is kept the same as that of the first processor through a global timer and a shared memory, thereby achieving cross-domain time synchronization between the multiple domain processors.

[0028] (3) The global counter in the present disclosure can adjust the timing accuracy by adjusting the counting frequency. The faster the counting frequency, the higher the timing accuracy, which facilitates instant adjustment of the timing accuracy of the global counter.

[0029] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 A system structure diagram of an embodiment of a cross-domain time synchronization system in the present disclosure;

[0032] Figure 2 is a system structure diagram of another embodiment of a cross-domain time synchronization system in the present disclosure;

[0033] Figure 3 is a system structure diagram of another embodiment of a cross-domain time synchronization system in the present disclosure;

[0034] Figure 4 A method flow chart of an embodiment of a cross-domain time synchronization method in the present disclosure;

[0035] Figure 5 A method flow chart of another embodiment of a cross-domain time synchronization method in the present disclosure;

[0036] Figure 6 It is a structural schematic diagram of an embodiment of an electronic medium in the present disclosure.

[0037] In the figure, 100-first domain processor, 101-global counter, 102-first synchronization time module, 103-trigger module, 104-time synchronization interrupt processing module, 105-communication module, 106-automatic parking system control module, 200-second domain processor, 201-second synchronization time module, 202-automatic parking system service module, 203-automatic parking system communication module, 300-shared memory, 400-control unit, 500-electronic medium, 501-controller, 502-memory, 503-communication component, 504-bus. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with the drawings in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0039] The terms "first", "second", "third", "fourth", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances. For example, without departing from the scope of this document, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information.

[0040] The word "if" as used herein may be interpreted as "when" or "when" or "in response to determining," depending on the context.

[0041] Furthermore, as used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context indicates otherwise.

[0042] It should be further understood that the terms “comprises” and “includes” indicate the existence of features, steps, operations, elements, components, items, types, and / or groups, but do not exclude the existence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, types, and / or groups.

[0043] The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Thus, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". An exception to this definition will only occur when a combination of elements, functions, steps or operations are inherently mutually exclusive in some manner.

[0044] Current controllers such as SOC controllers include multiple domain processors, such as sensor domain processors, application domain processors, and communication domain processors. The sensor domain processor is used to process the data collected by the sensor, and converts the sensor's analog signal into a digital signal through data conversion, filtering, and feature extraction. The application domain processor is used to handle the operation of various applications, and provides better performance in this application field by optimizing the hardware architecture, instruction set, etc. The communication domain processor is used to handle communication-related functions, and is mainly responsible for processing, transmission control, and protocol management of communication data.

[0045] At present, after the control unit obtains the time information, it transmits it to the sensor domain processor, which then sends it to the application domain processor or the communication domain processor. However, due to data transmission delays, processing speed differences and other reasons, the time obtained by the application domain processor or the communication domain processor may be inaccurate. For example, the time sent by the sensor domain processor is A, but the time to reach the application domain processor may be A+0.4S, and the time to reach the communication domain processor may be A+0.6S, resulting in different times between processors in different domains. In addition, a large amount of time data is transferred in the sensor domain processor, which also increases the computing and processing pressure of the sensor domain processor.

[0046] To solve the above problems, firstly, Figure 1 As shown, the embodiment of the present disclosure provides a cross-domain time synchronization system, including:

[0047] A first domain processor 100, wherein the first domain processor 100 is provided with a global counter 101 and a first synchronization time module 102, wherein the first synchronization time module 102 is communicatively connected to the global counter 101; a second domain processor 200, wherein the second domain processor 200 is provided with a second synchronization time module 201, wherein the second synchronization time module 201 is communicatively connected to the global counter 101; a shared memory 300, wherein the first synchronization time module 102 is communicatively connected to the shared memory 300, wherein the second synchronization time module 201 is communicatively connected to the shared memory 300; and a control unit 400, wherein the control unit 400 is communicatively connected to the first domain processor 100.

[0048] In one embodiment, the control unit 400 is used to generate a level signal. The control unit 400 can be optionally a microcontroller (MCU), a programmable logic controller (PLC), a field programmable gate array (FPGA) or a digital signal processor (DSP). The waveform of the level signal can be optionally a square wave, a pulse wave, a sine wave, a triangle wave, or a sawtooth wave. In one embodiment, the level signal is a pulse wave, which is a level change signal that appears in a short time. In one cycle of the pulse wave, it will suddenly rise from a low level to a high level, and suddenly drop back to a low level after a period of time. The pulse wave can accurately represent 0 and 1 in the digital signal, that is, the low level represents 0, and the high level represents 1, which is suitable for the transmission and processing of information in digital circuits and computer systems. The pulse wave provides an accurate time reference for the controller to ensure the correct processing and transmission of data.

[0049] The first domain processor 100 may be one of a sensor domain processor, an application domain processor and an information domain processor. In one embodiment, the first domain processor 100 is a sensor domain processor, which is a real-time operating system that completes specific tasks within a specified time and has a high degree of time predictability. The time synchronization operation in the sensor domain processor makes the time synchronization process between the second domain processor 200 and the first domain processor 100 accurate, stable and efficient due to its time predictability.

[0050] In one embodiment, the global counter 101 is a counter that counts in the form of a countdown. When the countdown is 0, the timer overflows, the overflow count is increased by one, and the countdown starts again. Both the first synchronization time module 102 and the second synchronization time module 201 can read the overflow count and the current time from the global counter 101. The counting frequency can be adjusted according to actual conditions. The counting frequency is the speed at which the timer can count input pulses. For example, in a cycle of 1ms, the counting frequency is 1MHz. At this time, if counting is performed per nanosecond, the maximum time can be counted for 4 seconds, and then it will overflow; if counting is performed per microsecond, the maximum time can be counted for 4000 seconds, and then it will overflow; if counting is performed per millisecond, the maximum time can be saved for 50 days. The faster the counting frequency, the higher the accuracy. The global counter 101 can enable different domain processors to obtain the same time reference. By setting the global counter 101 for timing, a unified timing is provided for the first domain processor 100 and the second domain processor 200, thereby correcting the time error transmitted from the first domain processor 100 to the second domain processor 200, synchronizing the time of the second domain processor 200 with the control unit 400, and reducing the computing processing pressure of the first domain processor 100.

[0051] The second domain processor 200 may be a sensor domain processor, an application domain processor or an information domain processor. In one embodiment, the second domain processor 200 is an application domain processor. The application domain processor is used to process the operation of various application programs.

[0052] In one embodiment, the shared memory 300 allows different domain processors to access and obtain data, with a faster data transmission speed. The data exchange between different domain processors does not need to be copied multiple times through the kernel, reducing the overhead of system calls.

[0053] When the control unit 400 generates a level signal change, the first synchronization time module 102 receives the first time data of the level signal change generated by the control unit 400, and simultaneously reads the second time data of the global counter 101, calculates the difference between the first time data and the second time data, obtains the shared data, and stores the shared data in the shared memory 300. The second synchronization time module 201 reads the shared data from the shared memory 300, and reads the second time data from the global counter 101, adds the second time data to the shared data, and synchronizes the time of the second domain processor 200 with that of the first domain processor 100.

[0054] like Figure 2 As shown, another embodiment of the present disclosure provides another cross-domain time synchronization system, including: a first domain processor 100 and two second domain processors 200 in the SOC controller, the first domain processor 100 and the second domain processor 200 are connected via a shared memory 300,

[0055] The first domain processor 100 is provided with a global counter 101, a first synchronization time module 102, a trigger module 103, a time synchronization interrupt processing module 104 and a communication module 106. The time synchronization interrupt processing module 104 and the trigger module 103 are communicatively connected. The first synchronization time module 102 is communicatively connected to the global counter 101 via the time synchronization interrupt processing module 214; the communication module 106 is communicatively connected to the first synchronization time module 102.

[0056] The second domain processor 200 is provided with a second synchronization time module 201, and the second synchronization time module 201 is communicatively connected to the global counter 101; the first synchronization time module 102 is communicatively connected to the shared memory 300, and the second synchronization time module 201 is communicatively connected to the shared memory 300.

[0057] The device further comprises a control unit 400, which is communicatively connected with the first domain processor 100. The control unit 400 is used to generate a level signal.

[0058] In one embodiment, the first domain processor 100 is a sensor domain processor, which is a real-time operating system that completes specific tasks within a specified time and has a high degree of time predictability. The time synchronization operation in the sensor domain processor makes the time synchronization process between the second domain processor 200 and the first domain processor 100 accurate, stable and efficient due to its time predictability.

[0059] The trigger module 103 is a module used in an electronic system to generate a signal to start or trigger a specific operation, event or process, and is used to generate a trigger signal when a level signal is changed. The time synchronization interrupt processing module is a module that ensures the accuracy and consistency of time in an electronic system. When a high-level signal is changed, the trigger module 103 generates a trigger signal and sends it to the time synchronization interrupt processing module 104. After receiving the trigger signal, the time synchronization interrupt processing module stops the timing of the global counter 101 and reads the overflow number and current time of the global counter 101. In one embodiment, the trigger module 103 realizes data transmission between the control unit 400 and the first domain processor 100 through a general-purpose input / output interface (GPIO, General-Purpose Input / Output), wherein the input end is connected to the control unit 400, and the output end is connected to the time synchronization interrupt processing module 104, and the input end can sense that the control unit 400 is currently at a high level or a low level. When a level signal is changed, the output end generates a trigger signal and sends it to the time synchronization interrupt processing module.

[0060] The communication module 106 is used to send the time when the level signal is changed to the first synchronization time module 102. In one embodiment, the communication module 106 realizes data transmission between the control unit 400 and the first domain processor 100 through a serial peripheral interface (SPI), and realizes data exchange through four data lines. When the control unit 400 generates a level signal change, the time when the level signal change is generated is synchronously transmitted to the communication module 106.

[0061] The second domain processor 200 may be a sensor domain processor, an application domain processor or an information domain processor. There is at least one second domain processor 200. Specifically, when there is one second domain processor 200, it may be an application domain processor, or an information domain sensor, or a sensor domain processor; when there are two second domain processors 200, they may be an application domain sensor and an information domain sensor, or an application domain sensor and a sensor domain processor, or a sensor domain sensor and an information domain sensor; when there are three second domain processors 200, they may be a sensor domain processor, an application domain processor and an information domain processor. The number of second domain processors 200 may be set according to the specific requirements of the SOC controller.

[0062] Each second domain processor 200 is provided with a second synchronization time module 201 , and the second synchronization time module 201 is used to correct the time error so that the time of the second domain processor 200 is synchronized with the time of the first domain processor 100 .

[0063] In one embodiment, the control unit 400 generates a level signal. When the level signal changes, for example, when it changes from a low level to a high level, the communication module 106 detects the level signal change and transmits the time when the level signal change occurs as the first time data to the first synchronization time module 102. At the same time, the trigger module 103 detects the level signal change, generates a trigger signal and sends it to the time interrupt processing module 214. The time interrupt processing module 214 causes the global counter 101 to generate an interrupt, and reads the current timing time of the global counter 101 as the second time data. The second synchronization time module 212 reads the second time data from the time interrupt processing module 214, calculates the difference between the first time data and the second time data, and stores it in the shared memory 300. The second synchronization time module 201 reads the difference between the first time data and the second time data from the shared memory 300, and reads the second time data from the global counter 101, and sums the difference between the first time data and the second time data with the second time data, so that the time of the second domain processor 200 and the first domain processor 100 remains the same.

[0064] like Figure 3 As shown, in another embodiment, the first domain processor 100 is a sensor domain processor, in which an automatic parking system control module 106 is provided, and the first synchronization time module 102 is connected to the automatic parking system control module 106 in communication. The two second domain processors 200 are respectively an application domain processor and an information domain processor, wherein the application domain processor is provided with an automatic parking system service module 202, the second synchronization time module 201 is connected to the automatic parking system service module 202 in communication, and the information domain processor is provided with an automatic parking system communication module 203, and the second synchronization time module 201 is connected to the automatic parking system communication module 203 in communication. Among them, the automatic parking system control module 106 is used to receive information from various sensors, process this information to determine the parking strategy, and then control the steering, speed and other actuators of the vehicle to park the vehicle safely and accurately in the parking space. The automatic parking system service module 202 is used to provide various support services for the realization of the automatic parking function. The automatic parking system communication module 203 is used for information transmission and interaction between various components within the automatic parking system and between the system and external devices. The first synchronization time module 102 directly transmits the first time data to the automatic parking system control module 106, and the second synchronization time module 201 calculates and obtains the synchronization time data and transmits it to the automatic parking system service module 202 or the automatic parking system communication module 203, ensuring that the time of the automatic parking system control module 106, the automatic parking system service module 202 and the automatic parking system communication module 203 is consistent, ensuring that the automatic parking system smoothly implements the automatic parking function. Further, the second synchronization time module 201 can also transmit the synchronization time data to other modules in the same domain processing to ensure that the time of other system modules is the same as the time of the first domain processor.

[0065] Second, it provides Figure 4 A cross-domain time synchronization method is shown, comprising the following steps:

[0066] S101, a first synchronization time module obtains first time data, and a global counter generates second time data;

[0067] When the first synchronization time module detects the level signal change, the first time data is read; wherein the first time data is the time when the level signal change is detected. The control unit generates a level signal, and when the level signal changes from a low level to a high level or from a high level to a low level, the time when the level signal changes is recorded as the first time data.

[0068] The step of generating second time data by the global counter comprises:

[0069] When the first synchronization time module detects a change in the level signal, the global counter generates an interrupt and generates second time data; wherein the second time data is the counting time when the global counter is interrupted.

[0070] The global counter counts in a countdown manner, and when the countdown ends, the overflow number is increased by one and the countdown starts again. The global counter can provide a same timing time for the first domain processor and the second domain processor.

[0071] S102, the first synchronization time module reads the second time data, obtains shared data according to the first time data and the second time data, and stores the shared data in a shared memory;

[0072] The first synchronization time module reads the second time data, calculates the difference between the first time data and the second time data, and stores the difference between the first time data and the second time data and the current time of the global counter as shared data in the shared memory.

[0073] S103, the second synchronization time module reads the second time data from the global counter, and reads the shared data from the shared memory at the same time, obtains the synchronization time data through the second time data and the shared data, and completes the time synchronization correction of the cross-domain processors.

[0074] The second synchronization time module reads the second time data and the shared data, and obtains the synchronization time data by summing the second time data, the current time of the global counter, and the difference between the first time data and the second time data.

[0075] A cross-domain time synchronization method disclosed in the present invention provides unified timing for a first domain processor and a second domain processor by setting a global counter for timing, thereby correcting the time error transmitted from the first domain processor to the second domain processor, so that the second domain processor keeps the time synchronized with the first domain processor.

[0076] like Figure 5 As shown, another embodiment of the present disclosure provides another cross-domain time synchronization method, including the following steps:

[0077] S201, when the communication module detects that the level signal of the control unit changes, the first synchronization time module reads the first time data through the communication module;

[0078] In one embodiment, the control unit generates a high level signal once per second, and the moment when the high level is generated is used as the first time data, recorded as T1.

[0079] In one embodiment, the communication module reads the first time data when the control unit is converted from a low level to a high level through the serial peripheral interface.

[0080] S202, when the trigger module detects the level signal change of the control unit, it generates a trigger signal and sends it to the time interrupt processing module;

[0081] In one embodiment, the trigger module detects the control unit through a general input and output interface, and generates a trigger signal when the control unit is converted from a low level to a high level.

[0082] S203, the time interrupt processing module controls the global timer to generate an interrupt, and reads the time of the global timer as the second time data;

[0083] In one embodiment, the second time data is:

[0084] T2=X×T n

[0085] Among them, the second time data is T2, the overflow number is X, and the total time of the global counter is T n , the current time of the global counter is T d for

[0086] T d =T n -T s .

[0087] Among them, T d is the current time of the global counter, and the total time of the global counter is T n , the current timing number of the global counter is T s .

[0088] S204, the first synchronization time module periodically reads the second time data,

[0089] In one embodiment, the first synchronization time module reads the second time data from the global counter at regular intervals. For example, the first synchronization time module reads the second time data T2 of the global counter every 1000 ms and resets the global counter to zero and restarts timing.

[0090] S205, the first synchronization time module calculates the difference between the first time data and the second time data to obtain shared data;

[0091] In one embodiment, the difference between the first time data and the second time data is:

[0092] Δt=T1-T2

[0093] The shared data includes the difference Δt between the first time data and the second time data and the current time T of the global counter d .

[0094] S206, the first synchronization time module stores the shared data into the shared memory;

[0095] The shared memory allows different domain processors to access and obtain data, so both the first domain processor and the second domain processor can access data in the shared memory with a faster access speed.

[0096] S207, the second synchronization time module reads shared data from the shared memory;

[0097] S208, the second synchronization time module reads the second time data from the global counter;

[0098] In one embodiment, the second domain processor reads the second time data T2 from the global counter.

[0099] S209: The second synchronization time module calculates synchronization time data.

[0100] The synchronization time data is the same time as the first domain processor. In one embodiment, the synchronization time data is equal to the sum of the second time data and the shared data. The time after synchronization is T t =T2+T d +Δt. The synchronization time data is calculated by using the shared data and the second time data, so that the time of the second domain processor is synchronized with that of the first domain processor.

[0101] According to a third aspect, an electronic medium is provided, comprising a controller and a storage device, wherein the controller is electrically connected to the storage device, wherein a computer program executable by the controller is stored in the storage device, and wherein the computer program is executed by the controller to implement a cross-domain time synchronization method as described in any one of claims 1 to 7.

[0102] like Figure 6 As shown, the electronic medium 500 provided in this embodiment includes: at least one controller 501 and a memory 502. Optionally, the electronic medium 500 also includes a communication component 503. The controller 501, the memory 502 and the communication component 503 are connected via a bus 504.

[0103] In a specific implementation process, at least one controller 501 executes the computer-executable instructions stored in the memory 502, so that at least one controller 501 executes the above method.

[0104] The specific implementation process of the controller 501 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0105] In the above embodiments, it should be understood that the controller 501 can be a central processing unit (CPU), or other general controllers 501, digital signal processors 501 (DSP), application specific integrated circuits (ASIC), etc. The general controller 501 can be a microcontroller 501 or the controller 501 can also be any conventional controller 501, etc. The steps of the method disclosed in the invention can be directly embodied as being executed by the hardware controller 501, or can be executed by a combination of hardware and software modules in the controller 501.

[0106] The memory 502 may include a high-speed memory 502 (Random Access Memory, RAM), and may also include a non-volatile memory 502 (Non-volatile Memory, NVM), such as at least one disk memory 502 .

[0107] The bus 504 may be an Industry Standard Architecture (ISA) bus 504, a Peripheral Component Interconnect (PCI) bus 504, or an Extended Industry Standard Architecture (EISA) bus 504, etc. The bus 504 may be divided into an address bus 504, a data bus 504, a control bus 504, etc. For ease of representation, the bus 504 in the drawings of the present application is not limited to only one bus 504 or one type of bus 504.

[0108] It should be understood that, although the various steps in the flowcharts in the above-described embodiments are sequentially displayed according to the indications of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and they can be executed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily to be carried out sequentially, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0109] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the above embodiments can still be modified, or some or all of the technical features can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A cross-domain time synchronization system, characterized in that: include: A first domain processor, wherein a global counter and a first synchronization time module are provided in the first domain processor, and the first synchronization time module is communicatively connected with the global counter; A second domain processor, wherein a second synchronization time module is provided in the second domain processor, the second synchronization time module is communicatively connected with the global counter, and the second domain processor has at least one; A shared memory, wherein the first synchronization time module is communicatively connected to the shared memory, and the second synchronization time module is communicatively connected to the shared memory.

2. A cross-domain time synchronization system according to claim 1, characterized in that: The first domain processor is provided with a trigger module and a time synchronization interrupt processing module. The time synchronization interrupt processing module is communicatively connected with the trigger module. The first synchronization time module is communicatively connected with the global counter via the time synchronization interrupt processing module.

3. A cross-domain time synchronization system according to claim 1, characterized in that: The first domain processor is provided with a communication module, and the communication module is communicatively connected with the first synchronization time module.

4. The cross-domain time synchronization system according to claim 1, characterized in that: A control unit is also included, and the control unit is communicatively connected to the first domain processor.

5. A cross-domain time synchronization method, characterized in that: A cross-domain time synchronization system for use in any one of claims 1 to 4, comprising the following steps: The first synchronization time module obtains the first time data, and the global counter generates the second time data; The first synchronization time module reads the second time data, obtains shared data according to the first time data and the second time data, and stores the shared data in the shared memory; The second synchronization time module reads the second time data from the global counter and reads the shared data from the shared memory at the same time, obtains the synchronization time data through the second time data and the shared data, and completes the time synchronization correction of the cross-domain processor.

6. A cross-domain time synchronization method according to claim 5, characterized in that: The step of obtaining first time data by the first synchronization time module includes: When the first synchronization time module detects a change in the level signal, it reads the first time data; wherein the first time data is the time when the change in the level signal is detected.

7. A cross-domain time synchronization method according to claim 5, characterized in that: The step of generating second time data by the global counter comprises: When the first synchronization time module detects a change in the level signal, the global counter generates an interrupt and generates second time data; wherein the second time data is the counting time when the global counter is interrupted.

8. A cross-domain time synchronization method according to claim 5, characterized in that: The first synchronization time module reads the second time data, and the step of obtaining shared data according to the first time data and the second time data includes: The first synchronization time module reads the second time data, calculates the difference between the first time data and the second time data, and uses the difference between the first time data and the second time data and the current time of the global counter as shared data.

9. A cross-domain time synchronization method according to claim 8, characterized in that: The second domain processor reads the second time data and the shared data, and the step of obtaining the synchronized time data through the second time data and the shared data includes: The second domain processor reads the second time data and the shared data, and obtains the synchronization time data by summing the second time data, the current time of the global counter, and the difference between the first time data and the second time data.

10. An electronic medium, characterized in that: The electronic medium includes a controller and a storage device, wherein the controller is electrically connected to the storage device, wherein a computer program executable by the controller is stored in the storage device, and the computer program executed by the controller can implement a cross-domain time synchronization method as described in any one of claims 5 to 9.

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