Data processing method based on AI model, chip architecture and intelligent terminal

Abstract

The embodiment of the invention provides a data processing method based on an AI model, a chip architecture and an intelligent terminal, and relates to the technical field of AI. The data processing method based on the AI model is used for a chip architecture, and the chip architecture comprises a computing chip, a flash memory and a running memory. An AI model is stored in a flash memory, and the data processing method based on the AI model comprises the steps that when a target trigger event occurs, a computing chip directly loads the AI model from the flash memory; and on the basis of the data to be processed and the AI model, the calculation chip generates process data, and temporarily stores the process data in the running memory. By adopting the technical scheme provided by the embodiment of the invention, when the target trigger event occurs, the computing chip directly loads the AI model from the flash memory, and the AI model is not transferred through the running memory, so that the delay of data transmission is reduced, and the data processing efficiency is improved. Meanwhile, the storage requirement of the data in the running memory is reduced, so that the use amount and the cost of the running memory are reduced.

Description

Technical Field

[0001] The present application relates to the field of artificial intelligence technology, and in particular to a data processing method, chip architecture and smart terminal based on an AI model. Background Art

[0002] With the development of artificial intelligence (AI) technology, the application scenarios of AI models are becoming increasingly extensive. For example, based on the voice model, users can use AI assistants such as Siri or YOYO to interact with smart terminals such as mobile phones and tablets. The traditional chip architecture includes: computing chip, flash memory and dynamic random access memory (DRAM). Among them, the AI ​​model is stored in the flash memory. When processing data, the AI ​​model stored in the flash memory is first loaded into the DRAM, and then the computing chip loads the AI ​​model from the DRAM, processes the data to be processed based on the AI ​​model, and temporarily stores the generated intermediate data in the DRAM. Taking a large language model with 4 billion parameters as an example, the traditional chip architecture needs to be equipped with 4GB flash memory and 6GB DRAM. Due to the high cost of DRAM and the delay in data transmission between flash memory and DRAM, the existing data processing methods restrict the improvement of chip architecture performance and cost control.

[0003] Therefore, how to provide a high-performance, low-cost data processing method based on AI models is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present application provides a data processing method, chip architecture and intelligent terminal based on an AI model, which can perform data processing based on the AI ​​model efficiently and at low cost.

[0005] In the first aspect, an embodiment of the present application provides a data processing method based on an AI model, which is used for a chip architecture, and the chip architecture includes: a computing chip, a flash memory, and a running memory; the AI ​​model is stored in the flash memory, and the processing method includes: when a target trigger event occurs, the computing chip directly loads the AI ​​model from the flash memory; based on the data to be processed and the AI ​​model, the computing chip generates process data, and temporarily stores the process data in the running memory.

[0006] With this solution, when a target trigger event occurs, the computing chip directly loads the AI ​​model from the flash memory. Since it does not go through the running memory, it reduces the delay of data transmission and improves the efficiency of data processing. At the same time, since it reduces the storage requirements of data in the running memory, this solution also reduces the usage and cost of the running memory.

[0007] In combination with the first aspect, in a possible implementation of the first aspect, when the data to be processed needs to be processed multiple times, the data processing method also includes: after the data to be processed is processed, the computing chip temporarily stores the processing results in the running memory.

[0008] In combination with the first aspect, in a possible implementation manner of the first aspect, before temporarily storing the processing result in the running memory, the data processing method also includes: the computing chip deletes the process data in the running memory.

[0009] By adopting this solution, the process data in the running memory is deleted before the processing results are temporarily stored, which is conducive to the effective management of the storage space of the running memory, avoiding the performance degradation caused by excessive memory usage, and is conducive to the stable operation of the chip architecture.

[0010] In combination with the first aspect, in a possible implementation of the first aspect, the carrier of the flash memory includes one or more flash memory chips, and the carrier of the running memory includes one or more running memory chips; the chip architecture also includes: a printed circuit board; the computing chip is electrically connected to the printed circuit board; all flash memory chips and all running memory chips are directly electrically connected to the computing chip; all flash memory chips, all running memory chips, and the computing chip are integrated together through packaging technology.

[0011] This solution directly connects all flash memory chips and running memory chips to the computing chip and integrates them together, reducing the signal transmission path and delay, improving data transmission speed and overall performance. At the same time, this integrated design simplifies the structure of the chip architecture and reduces manufacturing costs.

[0012] In combination with the first aspect, in a possible implementation of the first aspect, the carrier of the flash memory includes one or more flash memory chips, and the carrier of the running memory includes one or more running memory chips; the chip architecture also includes: a printed circuit board; the computing chip is electrically connected to the printed circuit board; when the carrier of the flash memory includes multiple flash memory chips, at least a part of the multiple flash memory chips are integrated together by vertical stacking, and at least a part of the flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the storage chips that are not integrated together by vertical stacking in the multiple flash memory chips are directly electrically connected to the computing chip; when the carrier of the running memory includes multiple running memory chips, at least a part of the running memory chips are integrated together by vertical stacking, and the running memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the running memory chips that are not integrated together by vertical stacking in the multiple running memory chips are directly electrically connected to the computing chip; when the carrier of the flash memory includes only one flash memory chip, the flash memory chip is directly electrically connected to the computing chip; when the carrier of the running memory includes only one running memory chip, the running memory chip is electrically connected to the computing chip.

[0013] By adopting this solution, when flash memory chips or running memory chips are integrated through vertical stacking, the physical space of the chip architecture is saved. At the same time, the vertical stacking integration method also improves the storage and computing density, which is conducive to efficient data transmission.

[0014] In combination with the first aspect, in a possible implementation of the first aspect, the AI ​​model includes one or more of the following modules: a speech model, an image processing model, a text processing model, a deep learning model, a machine learning model, and a genetic algorithm model.

[0015] This embodiment supports multiple types of AI models (such as speech models, image processing models, etc.), so that the chip architecture can cope with diverse application scenarios, improves the versatility and flexibility of the chip architecture, and is conducive to meeting the diverse needs of users.

[0016] In the second aspect, an embodiment of the present application provides a chip architecture, which includes: a computing chip, a flash memory and a running memory; the flash memory is used to store the AI ​​model: the computing chip is used to load the AI ​​model directly from the flash memory when the target trigger event occurs; and based on the data to be processed and the AI ​​model, process data is generated, and the process data is temporarily stored in the running memory.

[0017] The chip architecture using this solution integrates computing chips, flash memory and running memory. The computing chip directly loads the AI ​​model from the flash memory, reducing the intermediate links in the data processing process and improving processing efficiency. At the same time, this solution reduces the storage requirements of data in the running memory, thereby reducing the usage and cost of running memory.

[0018] In combination with the second aspect, in a possible implementation of the second aspect, the carrier of the flash memory includes one or more flash memory chips, and the carrier of the running memory includes one or more running memory chips; the chip architecture also includes: a printed circuit board; the computing chip is electrically connected to the printed circuit board; all the flash memory chips and all the running memory chips are directly electrically connected to the computing chip; all the flash memory chips, all the running memory chips, and the computing chip are integrated together through packaging technology.

[0019] This implementation method optimizes the data transmission path, improves processing speed and performance, and reduces manufacturing costs by electrically connecting and integrating all flash memory chips and running memory chips directly with the computing chip.

[0020] In combination with the second aspect, in a possible implementation of the second aspect, the carrier of the flash memory includes one or more flash memory chips, and the carrier of the running memory includes one or more running memory chips; the chip architecture also includes: a printed circuit board; the computing chip is electrically connected to the printed circuit board; when the carrier of the flash memory includes multiple flash memory chips, at least a portion of the multiple flash memory chips are integrated together by vertical stacking, and at least a portion of the flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the storage chips that are not integrated together by vertical stacking in the multiple flash memory chips are directly electrically connected to the computing chip; when the carrier of the running memory includes multiple running memory chips, at least a portion of the running memory chips are integrated together by vertical stacking, and at least a portion of the running memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the running memory chips that are not integrated together by vertical stacking in the multiple running memory chips are directly electrically connected to the computing chip; when the carrier of the flash memory includes only one flash memory chip, the flash memory chip is directly electrically connected to the computing chip; when the carrier of the running memory includes only one running memory chip, the running memory chip is electrically connected to the computing chip.

[0021] This solution integrates flash memory chips or running memory chips through vertical stacking, which helps save the physical space of the chip architecture. At the same time, the vertical stacking integration method also improves the storage and computing density, which is conducive to efficient data transmission.

[0022] In a third aspect, an embodiment of the present application provides a smart terminal, comprising a chip architecture provided in the second aspect and any possible implementation thereof.

[0023] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes a data processing method as provided in the first aspect and any possible implementation thereof.

[0024] In a fifth aspect, the present application provides a computer program product. When the computer program product is run on a chip architecture, the chip architecture executes the data processing method provided in the first aspect and any possible implementation thereof.

[0025] It can be understood that the beneficial effects that can be achieved by the chip architecture of the second aspect, the intelligent terminal of the third aspect, the computer-readable storage medium of the fourth aspect, and the computer program product of the fifth aspect provided above can refer to the beneficial effects of the first aspect and any possible implementation manner thereof, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the structure of a chip architecture in the prior art;

[0027] Figure 2 It is a schematic diagram of the structure of a chip architecture provided by an embodiment of the present application;

[0028] Figure 3A It is a flowchart of a data processing method based on an AI model in one embodiment of the present application;

[0029] Figure 3B is a flowchart of a data processing method based on an AI model in another embodiment of the present application;

[0030] Figure 3C It is a flowchart of a data processing method based on an AI model in another embodiment of the present application;

[0031] Figure 4 It is one of the schematic diagrams of the structure of the chip architecture provided in the embodiment of the present application;

[0032] Figure 5A This is the second schematic diagram of the structure of the chip architecture provided in the embodiment of the present application;

[0033] Figure 5B This is the third schematic diagram of the structure of the chip architecture provided in the embodiment of the present application;

[0034] Figure 5C This is a fourth schematic diagram of the structure of the chip architecture provided in the embodiment of the present application;

[0035] Figure 5D This is the fifth schematic diagram of the structure of the chip architecture provided in the embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0037] The terms "first" and "second" in this application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects. For example, a first operation and a second operation are used to distinguish different operations, rather than to describe a specific order of operations. In the embodiments of this application, "plurality" refers to two or more.

[0038] Some nouns or terms involved in this application are explained below.

[0039] 1. Artificial intelligence (AI) model

[0040] AI models are computing frameworks that convert input data (such as text, images, sounds, etc.) into output results through machine learning, deep learning and other technologies. These models can recognize patterns, make predictions, classify, generate content, etc., thereby simulating human cognitive abilities and decision-making processes.

[0041] AI models are widely used in various fields, such as natural language processing, image recognition, speech recognition, autonomous driving, medical diagnosis, financial risk assessment, etc. These models can help people process information, make decisions and solve problems more efficiently.

[0042] AI models include: speech models, image processing models, text processing models, deep learning models, machine learning models, genetic algorithm models, etc.

[0043] Among them, the speech model is an AI model used to process and analyze speech signals; the image processing model is an AI model used to identify, classify, segment, enhance and other operations on images; the text processing model is an AI model used for text processing; the machine learning model is a technology that can automatically learn and improve the algorithm model from data. The machine learning model includes a variety of algorithms, such as logistic regression, decision tree, support vector machine, naive Bayes, etc. These algorithms achieve automatic learning and processing of data in different ways. The deep learning model is a special form of machine learning that simulates the cognitive process of the human brain by building a deep neural network. The genetic algorithm model is a search algorithm based on the concepts of natural selection and genetics. These AI models play an important role in their respective application fields, and through continuous technological innovation and optimization, they provide strong support for the development of artificial intelligence.

[0044] 2. Chip architecture

[0045] The chip is like the "heart" and "brain" of a computer. It is responsible for processing information, storing data, and allowing the device to run various tasks smoothly. The chip architecture includes: computing chip, flash memory and running memory.

[0046] Among them, the computing chip, also called the processor, can be a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), etc. The computing chip is like the "brain" in the chip architecture. It is responsible for performing all computing tasks, such as rendering the screen when the user plays mobile games, decoding when watching videos, opening applications, processing files, etc. The stronger the performance of the computing chip, the faster the device can process tasks, and the smoother it will feel to use.

[0047] Flash memory is like the "long-term memory" in chip architecture. It is used to permanently store data, such as AI models, photos, downloaded music, installed applications, and system files. The size of the flash memory determines how much can be stored, and its read and write speed will also affect how quickly users can save or read data.

[0048] Running memory, also called dynamic random access memory (DRAM), DRAM is like "short-term memory" or "working memory" in chip architecture. It is used to temporarily store data that the device is using, such as the application you currently have open, the document you are editing, etc. The larger the running memory, the more tasks the device can handle at the same time, and the smoother the switching of applications. Moreover, the running memory is also very fast, so the device can access this data faster. It should be noted that the cost of DRAM is relatively high. When the demand for DRAM capacity increases, the cost of the chip architecture and the smart terminals using the chip architecture will increase accordingly.

[0049] Traditional chip architecture such as Figure 1 As shown, the chip architecture 100 includes: flash memory 101, running memory 102 and technology chip 103, and the AI ​​model is stored in the flash memory 101. When using the AI ​​model for data processing, the AI ​​model stored in the flash memory 101 is first loaded into the running memory 102, and then the computing chip 103 loads the AI ​​model from the running memory 102, processes the data to be processed based on the AI ​​model, and temporarily stores the generated intermediate data in the running memory. Taking a large language model with 4 billion parameters as an example, the traditional chip architecture needs to be equipped with 4GB flash memory and 6GB DRAM. Due to the high cost of DRAM and the delay in data transmission between flash memory and DRAM, the existing data processing methods based on AI models restrict the performance improvement and cost control of the chip architecture.

[0050] This application breaks the traditional storage architecture, such as Figure 2 As shown, the chip architecture 200 includes: memory 201, running memory 202 and computing chip 203. When processing data based on the AI ​​model, the computing chip 203 directly loads the AI ​​model from the flash memory 201. During this process, the AI ​​model does not need to be transferred through the running memory 202. This method of directly loading the AI ​​model effectively reduces the delay in data transmission and significantly improves the efficiency of data processing. At the same time, since the AI ​​model does not need to be transferred through the running memory 202, the running memory 202 does not need to reserve a large amount of space for storing the AI ​​model (compared to traditional intermediate data, the space required for the AI ​​model is usually much larger). This change not only optimizes the use of the running memory 202, but also further reduces the usage of the running memory 202 and related costs.

[0051] like Figure 3A As shown, in one embodiment of the present application, the data processing method based on the AI ​​model may include the following steps: 301 to 302.

[0052] 301. When a target trigger event occurs, the computing chip loads the AI ​​model directly from the flash memory.

[0053] Target trigger events are preset conditions for starting specific functions or responses. They play a key role in many chip architectures and smart terminals, especially in scenarios where AI models are used for interaction. Taking voice models as an example, target trigger events are usually specific voice commands issued by users, which are designed to wake up the system and prepare it to receive further commands or inputs.

[0054] For example, the preset target wake-up word can be "hi, Siri". Users can wake up smart home devices by saying "hi, Siri" to control lighting, temperature, security, etc. The microphone continuously monitors the ambient sound, and the computing chip uses a low-power speech recognition algorithm to detect the wake-up word. Once audio information matching the preset wake-up word is detected, it is determined that the target trigger event has occurred.

[0055] Once the wake-up word is detected, the computing chip loads the AI ​​model directly from the flash memory. After loading, the chip architecture enters the speech recognition mode, ready to receive and process further voice commands from the user.

[0056] 302. Based on the data to be processed and the AI ​​model, the computing chip generates process data and temporarily stores the process data in the running memory.

[0057] The data to be processed can be the subsequent voice commands of the user that the microphone continues to obtain after the chip architecture enters the voice recognition mode through the wake-up word. The computing chip can generate process data based on the data to be processed and the AI ​​model, and temporarily store the process data in the running memory. For example, if the user says: "Hi, Siri, what's the weather like today?" The computing chip determines that the user's intention is to check the weather based on the recognized voice information and AI model. The computing chip can temporarily store the process data generated during the data processing in the memory.

[0058] By adopting the technical solution provided in this embodiment, when the target trigger event occurs, the computing chip directly loads the AI ​​model from the flash memory. Since it does not pass through the running memory, the delay of data transmission is reduced and the efficiency of data processing is improved. At the same time, since the storage requirements of data in the running memory are reduced, the usage and cost of the running memory are reduced.

[0059] like Figure 3B As shown, in another embodiment of the present application, the data processing method based on the AI ​​model may include the following steps: 311 to 313.

[0060] 311. When the target trigger event occurs, the computing chip loads the AI ​​model directly from the flash memory.

[0061] Target trigger events are preset conditions for starting specific functions or responses. They play a key role in many chip architectures and smart terminals, especially in scenarios where AI models are used for interaction. Taking voice models as an example, target trigger events are usually specific voice commands issued by users, which are designed to wake up the system and prepare it to receive further commands or inputs.

[0062] For example, the preset target wake-up word can be "hi, Siri". Users can wake up smart home devices by saying "hi, Siri" to control lighting, temperature, security, etc. The microphone continuously monitors the ambient sound, and the computing chip uses a low-power speech recognition algorithm to detect the wake-up word. Once audio information matching the preset wake-up word is detected, it is determined that the target trigger event has occurred.

[0063] Once the wake-up word is detected, the computing chip loads the AI ​​model directly from the flash memory. After loading, the chip architecture enters the speech recognition mode, ready to receive and process further voice commands from the user.

[0064] 312. Based on the data to be processed and the AI ​​model, the computing chip generates process data and temporarily stores the process data in the running memory.

[0065] The data to be processed can be the subsequent voice commands of the user that the microphone continues to obtain after the chip architecture enters the voice recognition mode through the wake-up word. The computing chip can generate process data based on the data to be processed and the AI ​​model, and temporarily store the process data in the running memory. For example, if the user says: "Hi, Siri, what's the weather like today?" The computing chip determines that the user's intention is to check the weather based on the recognized voice information and AI model. The computing chip can temporarily store the process data generated during the data processing in the memory.

[0066] 313. When the data to be processed needs to be processed multiple times, after the data to be processed is processed, the computing chip temporarily stores the processing results in the running memory.

[0067] When the data to be processed needs to be processed multiple times, after each processing is completed, especially when the processing results need to be used in subsequent processing steps, the computing chip can temporarily store the processing results in the running memory. As a temporary storage area, the running memory can quickly provide data access speed to ensure the efficient processing flow. By temporarily storing the processing results in the running memory, the computing chip can avoid repeated calculations, improve processing efficiency, and reduce energy consumption.

[0068] Taking smart home devices as an example, when the user says "Hi, Siri, what's the weather like today?", the computing chip first performs voice recognition and converts the voice into text "What's the weather like today?". And store the intermediate results: temporarily store the text in the running memory. It is understandable that in the specific recognition, you can recognize one word at a time, and then store it in the running memory, and then append iterative recognition and storage. It is also possible to recognize data in a preset time, such as a few seconds, or other possible processing methods are all feasible. The computing chip performs intent analysis on the text, determines that the user wants to query weather information, and then accesses the weather API to obtain weather data. Finally, based on the obtained weather data, the weather data can be formatted and prepared to be sent back to the user. In this process, the recognized text and weather data are temporarily stored in the running memory to ensure the efficiency and smoothness of the processing flow.

[0069] like Figure 3C As shown, in another embodiment of the present application, the data processing method based on the AI ​​model may include the following steps: 321 to 324.

[0070] 321. When a target trigger event occurs, the computing chip loads the AI ​​model directly from the flash memory.

[0071] Target trigger events are preset conditions for starting specific functions or responses. They play a key role in many chip architectures and smart terminals, especially in scenarios where AI models are used for interaction. Taking voice models as an example, target trigger events are usually specific voice commands issued by users, which are designed to wake up the system and prepare it to receive further commands or inputs.

[0072] For example, the preset target wake-up word can be "hi, Siri". Users can wake up smart home devices by saying "hi, Siri" to control lighting, temperature, security, etc. The microphone continuously monitors the ambient sound, and the computing chip uses a low-power speech recognition algorithm to detect the wake-up word. Once audio information matching the preset wake-up word is detected, it is determined that the target trigger event has occurred.

[0073] Once the wake-up word is detected, the computing chip loads the AI ​​model directly from the flash memory. After loading, the chip architecture enters the speech recognition mode, ready to receive and process further voice commands from the user.

[0074] 322. Based on the data to be processed and the AI ​​model, the computing chip generates process data and temporarily stores the process data in the running memory.

[0075] The data to be processed can be the subsequent voice commands of the user that the microphone continues to obtain after the chip architecture enters the voice recognition mode through the wake-up word. The computing chip can generate process data based on the data to be processed and the AI ​​model, and temporarily store the process data in the running memory. For example, if the user says: "Hi, Siri, what's the weather like today?" The computing chip determines that the user's intention is to check the weather based on the recognized voice information and AI model. The computing chip can temporarily store the process data generated during the data processing in the memory.

[0076] 323. The computing chip deletes temporary process data in the running memory.

[0077] Throughout the process of AI models processing user instructions or data, the running memory is used as a temporary storage area to quickly access and process data. As the processing proceeds, a large amount of intermediate or temporary process data is generated. These data may be necessary at a certain stage in the processing chain, but once they are no longer required by subsequent processing steps, continuing to retain them will occupy valuable running memory resources, which may cause performance degradation or processing delays.

[0078] When processing data, the computing chip determines which data is temporary and which data is the final result or needs to be retained for a long time. Once a process data is processed and it is determined that it is no longer required for subsequent steps, the computing chip will mark it as deletable. Then, a memory cleanup operation is performed to delete this data from the running memory.

[0079] 324. The computing chip temporarily stores the processing results in the running memory.

[0080] In this embodiment, the computing chip deletes temporary process data in the running memory, thereby improving the utilization rate of the running memory and ensuring the optimal configuration of system resources.

[0081] like Figure 4 As shown, the embodiment of the present application also provides a chip architecture. Figure 4 It is a schematic diagram of the structure of a chip architecture 400 provided in an embodiment of the present application. The chip architecture 400 includes: a computing chip, a flash memory and a running memory; the flash memory is used to store the AI ​​model: the computing chip is used to load the AI ​​model directly from the flash memory when the target trigger event occurs; and based on the data to be processed and the AI ​​model, process data is generated, and the process data is temporarily stored in the running memory.

[0082] It should be noted that the carrier of the flash memory includes one or more flash memory chips, and the carrier of the running memory includes one or more running memory chips; Figure 4As shown, the chip architecture 400 includes: a printed circuit board 401, a computing chip 402 directly electrically connected to the printed circuit board 401, an operating memory chip 403, and a flash memory chip 404. Among them, the flash memory chip 404 is used to store the AI ​​model: the computing chip 402 is used to load the AI ​​model directly from the flash memory chip 404 when the target trigger event occurs; and based on the data to be processed and the AI ​​model, generate process data, and temporarily store the process data in the operating memory chip 403.

[0083] The chip architecture using this solution integrates computing chips, flash memory chips and running memory chips. The computing chip directly loads the AI ​​model from the flash memory chip, reducing the intermediate links in the data processing process and improving processing efficiency. At the same time, this solution reduces the capacity requirements of data in the running memory chip, thereby reducing related costs.

[0084] In some possible implementations, the flash memory carrier includes one or more flash memory chips, and the running memory carrier includes one or more running memory chips; the chip architecture also includes: a printed circuit board; the computing chip is electrically connected to the printed circuit board; all flash memory chips and all running memory chips are directly electrically connected to the computing chip; all flash memory chips, all running memory chips, and the computing chip are integrated together through packaging technology. Figure 5A As shown, the chip architecture 500 includes: a printed circuit board 501, a computing chip 502, an operating memory chip 503, and a flash memory chip 504. The computing chip 502 is electrically connected to the printed circuit board 501, and the flash memory chip 504 and the operating memory chip 503 are both directly electrically connected to the computing chip. The computing chip 502, the operating memory chip 503, and the flash memory chip 504 are integrated together through packaging technology (such as three-dimensional packaging technology).

[0085] The technical solution provided in this embodiment optimizes the data transmission path, improves the processing speed and performance, and reduces the manufacturing cost by directly electrically connecting and integrating all flash memory chips and running memory chips with the computing chip.

[0086] In some possible implementations, the carrier of the flash memory includes one or more flash memory chips, and the carrier of the running memory includes one or more running memory chips; the chip architecture also includes: a printed circuit board; the computing chip is electrically connected to the printed circuit board; when the carrier of the flash memory includes multiple flash memory chips, at least a portion of the multiple flash memory chips are integrated together by vertical stacking, and the at least a portion of the flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the storage chips that are not integrated together by vertical stacking in the multiple flash memory chips are directly electrically connected to the computing chip; when the carrier of the running memory includes multiple running memory chips, at least a portion of the running memory chips are integrated together by vertical stacking, and the at least a portion of the running memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the running memory chips that are not integrated together by vertical stacking in the multiple running memory chips are directly electrically connected to the computing chip; when the carrier of the flash memory includes only one flash memory chip, the flash memory chip is directly electrically connected to the computing chip; when the carrier of the running memory includes only one running memory chip, the running memory chip is electrically connected to the computing chip.

[0087] In another embodiment, if Figure 5B As shown, Figure 5B The embodiments provided are relative to Figure 5A The embodiment shown has an additional storage chip 505, and two flash memory chips are integrated together by vertical stacking. The two flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole. The computing chip, the operating memory chip and the flash memory chip are integrated together by packaging technology (such as three-dimensional packaging technology).

[0088] In another embodiment, if Figure 5C As shown, Figure 5C The embodiments provided are relative to Figure 5B The embodiment shown has an additional operation memory chip 506. The two operation chips are integrated together by vertical stacking. The two flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole. The computing chip, the operation memory chip and the flash memory chip are integrated together by packaging technology (such as three-dimensional packaging technology).

[0089] In another embodiment, if Figure 5D As shown, Figure 5D The embodiments provided are relative to Figure 5AThe embodiment shown has an additional operation memory chip 507, and the two operation flash memory chips can be integrated together in a vertical stacking manner. The two operation memory chips integrated together in a vertical stacking manner are directly electrically connected to the computing chip as a whole. The computing chip, the operation memory chip and the flash memory chip are integrated together through packaging technology (such as three-dimensional packaging technology).

[0090] Figure 5B , Figure 5C and Figure 5D In the illustrated embodiment, flash memory chips or running memory chips are integrated by vertical stacking, which helps save the physical space of the chip architecture. At the same time, the vertical stacking integration method also improves the storage and computing density, which is conducive to efficient data transmission.

[0091] An embodiment of the present application also provides a smart terminal, including a chip architecture provided by any of the foregoing possible implementations.

[0092] An embodiment of the present application also provides a computer-readable storage medium, including computer instructions. When the computer instructions are executed on an electronic device, the electronic device executes the data processing method provided by any of the above method embodiments.

[0093] The embodiment of the present application further provides a computer program product. When the computer program product is run on a chip architecture, the chip architecture executes the data processing method provided by any of the above method embodiments.

[0094] It can be understood that the beneficial effects that can be achieved by the above-provided intelligent terminal, computer-readable storage medium, computer program product, etc. can refer to the beneficial effects described in the method embodiments, and will not be repeated here.

[0095] In the embodiments provided in this application, it should be understood that the disclosed data processing method based on the AI ​​model, chip architecture and intelligent terminal can be implemented in other ways. For example, the embodiments of the data processing method based on the AI ​​model, chip architecture and intelligent terminal described above are merely illustrative.

[0096] Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment methods, which can be completed by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by the processor, the steps of the above-mentioned method embodiments can be implemented.

[0097] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0098] In the above description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0099] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0100] References to "one embodiment" or "some embodiments" etc. described in the specification of the present application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways. The order of the steps of the method involved in the embodiments of the present application is not fixed and can be changed according to the specific circumstances.

[0101] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A data processing method based on an AI model, characterized in that: For a chip architecture, the chip architecture includes: a computing chip, a flash memory and an operating memory; the flash memory stores an AI model, and the data processing method includes: When a target trigger event occurs, the computing chip directly loads the AI ​​model from the flash memory; Based on the data to be processed and the AI ​​model, the computing chip generates process data and temporarily stores the process data in the running memory.

2. The data processing method according to claim 1, characterized in that: When the data to be processed needs to be processed multiple times, the data processing method further includes: After the data to be processed is processed, the computing chip temporarily stores the processing result in the running memory.

3. The data processing method according to claim 2, characterized in that: Before the computing chip temporarily stores the processing result in the running memory, the data processing method further includes: The computing chip deletes the process data temporarily stored in the running memory.

4. The data processing method according to claim 1, characterized in that: The flash memory carrier includes one or more flash memory chips, and the operating memory carrier includes one or more operating memory chips; the chip architecture also includes: a printed circuit board; The computing chip is electrically connected to the printed circuit board; All of the flash memory chips and all of the operating memory chips are directly electrically connected to the computing chip; All of the flash memory chips, all of the running memory chips, and the computing chip are integrated together through packaging technology.

5. The data processing method according to claim 1, characterized in that: The flash memory carrier includes one or more flash memory chips, and the operating memory carrier includes one or more operating memory chips; the chip architecture also includes: a printed circuit board; The computing chip is electrically connected to the printed circuit board; When the carrier of the flash memory includes a plurality of flash memory chips, at least a portion of the plurality of flash memory chips are integrated together by vertical stacking, and the at least a portion of the flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the storage chips in the plurality of flash memory chips that are not integrated together by vertical stacking are directly electrically connected to the computing chip; When the carrier of the running memory includes a plurality of running memory chips, at least a portion of the running memory chips are integrated together by vertical stacking, and the at least a portion of the running memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the running memory chips that are not integrated together by vertical stacking among the plurality of running memory chips are directly electrically connected to the computing chip; When the carrier of the flash memory includes only one flash memory chip, the flash memory chip is directly electrically connected to the computing chip; When the operating memory carrier includes only one operating memory chip, the operating memory chip is electrically connected to the computing chip.

6. The data processing method according to any one of claims 1 to 5, characterized in that: The AI ​​model includes one or more of the following modules: speech model, image processing model, text processing model, deep learning model, machine learning model, and genetic algorithm model.

7. A chip architecture, characterized in that: The chip architecture includes: a computing chip, a flash memory and an operating memory; The flash memory is used to store the AI ​​model: The computing chip is used to directly load the AI ​​model from the flash memory when a target trigger event occurs; and to generate process data based on the data to be processed and the AI ​​model, and temporarily store the process data in the running memory.

8. The chip architecture according to claim 7, characterized in that: The flash memory carrier includes one or more flash memory chips, and the operating memory carrier includes one or more operating memory chips; the chip architecture also includes: a printed circuit board; The computing chip is electrically connected to the printed circuit board; All of the flash memory chips and all of the operating memory chips are directly electrically connected to the computing chip; All of the flash memory chips, all of the running memory chips, and the computing chip are integrated together through packaging technology.

9. The chip architecture according to claim 8, characterized in that: The flash memory carrier includes one or more flash memory chips, and the operating memory carrier includes one or more operating memory chips; the chip architecture also includes: a printed circuit board; The computing chip is electrically connected to the printed circuit board; When the carrier of the flash memory includes a plurality of flash memory chips, at least a portion of the plurality of flash memory chips are integrated together by vertical stacking, and the at least a portion of the flash memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the storage chips in the plurality of flash memory chips that are not integrated together by vertical stacking are directly electrically connected to the computing chip; When the carrier of the running memory includes a plurality of running memory chips, at least a portion of the running memory chips are integrated together by vertical stacking, and the at least a portion of the running memory chips integrated together by vertical stacking are directly electrically connected to the computing chip as a whole; the running memory chips that are not integrated together by vertical stacking among the plurality of running memory chips are directly electrically connected to the computing chip; When the carrier of the flash memory includes only one flash memory chip, the flash memory chip is directly electrically connected to the computing chip; When the operating memory carrier includes only one operating memory chip, the operating memory chip is electrically connected to the computing chip.

10. An intelligent terminal, characterized in that: Comprising the chip architecture described in any one of claims 7 to 9.

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