Row activation method, DDR controller and system on chip

Abstract

The invention relates to the field of memory management, and discloses a row activation method, a DDR (Double Data Rate) controller and an on-chip system.The method comprises the steps that a data read / write instruction processed by a port processing unit is sent to a first address mapping unit through a first data path, and when it is judged that a preset condition is met, the data read / write instruction is sent to a second address mapping unit; the second data path sends the first address information of the data reading / writing instruction to the bank management module; the first address mapping unit carries out address mapping on the data reading / writing instruction, second address information obtained through mapping is sent to the bank management module, the data reading / writing instruction obtained after address mapping is written into a command queue, the first address information reaches the bank management module earlier than the second address information, and the bank management module responds to the first address information and writes the data reading / writing instruction into the command queue. And activating the row pointed by the first address information. According to the technical scheme provided by one or more embodiments, the memory access efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of memory management, and in particular to a row activation method, a DDR controller and a system on chip. Background Art

[0002] Currently, when accessing DDR memory, the access instruction reaches the bank management module in the DDR controller through a series of operations such as parsing, judgment, caching, and address mapping. The bank management module performs a row activation operation based on the address information of the access instruction. At this time, it is necessary to wait for the tRCD (RAStoCASDelay, the delay time from row address selection to column address selection) timing to be met before executing the corresponding data read / write.

[0003] In actual applications, in low-bandwidth application scenarios, the processor's access frequency to the memory is low, and the time interval between adjacent access instructions is long. The access instruction also needs to wait for the row activation time and tRCD timing delay in the bank management module. The memory access delay is large, resulting in low memory access efficiency.

[0004] In view of this, how to improve memory access efficiency has become the current research focus in the field of memory management. Summary of the invention

[0005] The present application provides a row activation method, a DDR controller and a system on chip, which can improve the efficiency of memory access.

[0006] In a first aspect, the present application provides a row activation method, which is applied to a DDR controller, wherein the DDR controller includes a port processing unit and a control core, wherein the control core includes at least a first address mapping unit, a bank management module, and a command queue, wherein the port processing unit includes a first data path and a second data path in parallel, wherein the first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module, wherein the method includes: receiving a data read / write instruction through the port processing unit, and processing the data read / write instruction in parallel through the first data path and the second data path, wherein the first data path sends the processed data read / write instruction to the first data path; An address mapping unit, wherein the second data path sends the first address information of the data read / write instruction to the bank management module when it is determined that the data read / write instruction meets a preset condition; performs address mapping on the received data read / write instruction through the first address mapping unit, sends the second address information obtained by the address mapping to the bank management module, and writes the data read / write instruction after the address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information; and activates the row pointed to by the first address information in response to the first address information through the bank management module, wherein the activated row is used to process the data read / write instruction after the address mapping in the command queue after a preset delay.

[0007] The technical solution provided by this embodiment of the present application uses two parallel data paths to process read and write instructions, thereby improving memory access efficiency. Specifically, two parallel data paths are used to process read and write instructions so that instructions can be transmitted through two paths at the same time, wherein, when the preset conditions are met, the second data path can parse the address information of the instruction in advance and transmit it to the bank management module to perform the row activation operation in advance, so that after the command reaches the bank management module through the first data path, there is no need to wait for the delay time of row activation, but directly transmits the data read / write instruction to the downstream memory module more quickly. It can be seen that the technical solution provided by this embodiment of the present application shortens the overall time required to process read and write instructions and improves the efficiency of memory access.

[0008] In a possible implementation manner, after receiving the second address information, the bank management module discards the second address information if it is determined that the row pointed to by the second address information has been activated.

[0009] The technical solution provided in this embodiment of the present application describes the processing situation where the row pointed to by the second address information has been activated. When the bank management module determines that the row pointed to by the second address information has been pre-activated through the second data path, it directly discards the current second address information. At this time, the activation operation is no longer required, which simplifies the instruction processing flow of the bank management module.

[0010] In a possible implementation, the second data path includes a second address mapping unit and a logic judgment unit, and the second data path processes the data read / write instruction in the following manner: the second address mapping unit maps the logical address of the data read / write instruction to a physical address, and transmits the mapped physical address to the logic judgment unit; when the logic judgment unit determines that the data read / write instruction meets a preset condition, the mapped physical address is sent to the bank management module as the first address information of the data read / write instruction.

[0011] The technical solution provided in this embodiment of the present application describes the specific structure of the second data path and the instruction pre-processing process. When the preset conditions are met, the physical address information obtained by mapping the data read / write instruction is sent to the bank management module, so as to perform the row activation and preset delay waiting process in advance.

[0012] In a possible implementation, the data read / write instruction satisfies a preset condition, including: the logic judgment unit obtains the current queue status of the command queue, and determines whether the data read / write instruction is the first instruction to be processed in the command queue based on the queue status; if so, it is determined that the data read / write instruction satisfies the preset condition.

[0013] The technical solution provided in this embodiment of the present application refines the preset conditions that must be met for pre-processing of data read / write instructions through the second data path. Only when it is the first instruction to be processed in the command queue will the instruction pre-processing process of the second data path be performed, thereby ensuring normal data transmission on the two parallel data paths.

[0014] In a possible implementation, when the second data path determines that the data read / write instruction does not meet a preset condition, the second data path discards the data read / write instruction, so that the bank management module activates the row pointed to by the second address information in response to the second address information.

[0015] The technical solution provided in this embodiment of the present application adds a second data path to determine whether the data read / write instruction meets the preset conditions, thereby ensuring that the two parallel data paths process the same instruction synchronously to avoid bank resource conflicts caused by instruction adjustment of the command queue.

[0016] In a possible implementation, the first data path includes at least a queue judgment unit and a first-in-first-out queue; the first data path processes the data read / write instruction in the following manner: the data read / write instruction is written into the first-in-first-out queue; the queue judgment unit obtains the current queue status of the command queue, and judges whether the instructions in the first-in-first-out queue can be received by the command queue based on the queue status; if so, the instructions stored in the first-in-first-out queue are popped out to the first address mapping unit.

[0017] In one possible implementation, if the queue judgment unit determines that the instructions in the first-in-first-out queue cannot be received by the command queue, it reacquires the current queue state of the command queue, and determines whether the instructions in the first-in-first-out queue can be received by the command queue based on the reacquired queue state.

[0018] The technical solution provided in this embodiment of the present application describes the structural composition and instruction processing flow of the first data path, writes data read / write instructions into a first-in-first-out queue, and pops out the instructions stored in the first-in-first-out queue according to the queue status of the command queue, thereby ensuring orderly processing of instruction data and stable operation of the system.

[0019] In a possible implementation, the control core further includes a scheduling module, and the first address mapping unit passes the address-mapped data read / write instruction to the scheduling module, so that the address-mapped data read / write instruction is written into the command queue through the scheduling module.

[0020] In a possible implementation, the scheduling module obtains address information of each instruction stored in the command queue, and determines row conflict information in the command queue based on the obtained address information; the scheduling module reorders the instructions stored in the command queue according to the row conflict information; wherein, after the row pointed to by the first address information is activated, other instructions in the command queue carrying the first address information are prioritized after reordering.

[0021] The technical solution provided in this implementation of the present application introduces a scheduling module and its specific functions, which gives priority to other instructions in the same line as the first instruction, ensuring that other instructions in the same target line will be executed earlier, thereby reducing the number of line conflicts and shortening the processing time of commands.

[0022] According to a second aspect of the present application, a DDR controller is provided. The DDR controller includes a port processing unit and a control core. The control core includes at least a first address mapping unit, a bank management module and a command queue. The port processing unit includes a first data path and a second data path in parallel. The first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module. The port processing unit is used to receive a data read / write instruction and process the data read / write instruction in parallel through the first data path and the second data path, respectively. The first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the processed data read / write instruction to the first address mapping unit. The second data path sends the first address information of the data read / write instruction to the bank management module when it is determined that the data read / write instruction meets the preset conditions; the first address mapping unit is used to perform address mapping on the received data read / write instruction, send the second address information obtained by the address mapping to the bank management module, and write the data read / write instruction after the address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information; the bank management module is used to activate the row pointed to by the first address information in response to the first address information, wherein the activated row is used to process the data read / write instruction after the address mapping in the command queue after a preset delay.

[0023] The third aspect of the present application provides a system on chip, which includes a processor core, an on-chip network, a DDR controller and a physical layer, wherein: the processor core is used to send data read / write instructions to the DDR controller through the on-chip network; the DDR controller is used to execute the row activation method as described in the first aspect for the received data read / write instructions; the physical layer is used to perform protocol conversion on the instructions output by the DDR controller, and transmit the protocol-converted instructions to an external memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of the steps of a row activation method provided in an embodiment of the present application; Figure 2A schematic diagram of the steps of processing instructions by a second data path provided in one embodiment of the present application; Figure 3 A schematic diagram of a data processing flow using a single path provided for one embodiment of the present application; Figure 4 A schematic diagram of a data processing flow using parallel data paths provided for one embodiment of the present application; Figure 5 A schematic diagram of a flow chart of a data read / write instruction transmission process provided by an embodiment of the present application; Figure 6 A schematic diagram of the composition of a DDR controller provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a DDR controller provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a DDR controller provided in one embodiment of the present application; Fig. 9 A schematic diagram of the structure of a DDR controller provided in another embodiment of the present application; Fig.10 A schematic diagram of the composition of a system on a chip provided in an embodiment of the present application; Fig.11 A schematic diagram of the structure of a system on a chip provided for one embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0027] In addition, the descriptions involving "first", "second", etc. in this application are for descriptive purposes only and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more. In addition, the use of "based on" or "according to" means openness and inclusiveness, because the process, steps, calculations or other actions "based on" or "according to" one or more of the conditions or values ​​can be based on additional conditions or beyond the described values ​​in practice.

[0028] With the continuous development of the computer industry, the requirements for memory access performance are increasing. In modern computer systems, memory access speed is a key factor affecting the overall performance of the system. Among them, tRCD timing is a key memory access timing parameter, which represents the time required to wait from row activation to the read or write command being effective. The above row activation operation is used to load the specified memory row data into the row buffer. It can be understood that in order to ensure that the data in the row buffer is stable and the command can be read or written correctly, it is necessary to wait for the tRCD timing to be met after the row activation operation.

[0029] In the related art, the traditional memory access process is usually used to process data read / write instructions. The processor issues data read / write instructions to the DDR controller and accesses the memory through the DDR controller. In the DDR controller, the data read / write instructions need to be parsed, judged, cached, and address mapped before they can reach the bank management module, and then the row activation operation is started, and the data read / write instructions can be sent to the downstream memory after the tRCD timing is met.

[0030] In the above command processing process, the bank management module is in an idle state before the command arrives, and when the command reaches the bank management module, it needs to wait for an additional time to meet the tRCD timing, which increases the command delay. In low-bandwidth application scenarios, the processor has a low access frequency to the memory, the bank management module is idle for a long time, the memory access delay is particularly obvious, and the memory access efficiency is low.

[0031] In view of this, one or more embodiments of the present application provide a row activation method, a DDR controller and a system on chip, which introduce an additional data path to parse the address information of the instruction, and transmit the address information to the bank management module to perform the row activation operation in advance. Due to the long command interval, the operation of activating the row in advance will not conflict or interfere with other commands, thereby improving the efficiency of memory access.

[0032] See also Figure 1 An embodiment of the present application provides a row activation method, which is applied to a DDR controller. The DDR controller includes a port processing unit and a control core. The control core includes at least a first address mapping unit, a bank management module and a command queue. The port processing unit includes a first data path and a second data path in parallel. The first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module. The method may include the following steps: S1: receiving a data read / write instruction through the port processing unit, and processing the data read / write instruction in parallel through the first data path and the second data path, respectively, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when determining that the data read / write instruction meets a preset condition.

[0033] On the basis of satisfying the preset condition, the second data path is used to send the first address information of the data read / write instruction to the bank management module in advance. The preset condition may be that the current data read / write instruction needs to perform a row activation operation in advance, and the first address information is preferably the physical address information obtained by the data read / write instruction through address mapping, which points to the target row of the current data read / write instruction, and the target row is a row to be accessed by the current data read / write instruction. Since the bank management module is in an idle state at this time, the bank management module can pre-activate the target row according to the first address information in advance.

[0034] The bank management module is used to manage the row activation operation of the memory bank and control the timing of the row activation. Specifically, after receiving the first address information, the bank management module can pre-activate the row and wait for the tRCD timing to complete. When the data read / write instruction enters the bank management module, the bank management module can directly process the data read / write instruction.

[0035] In this embodiment, the first data path is used to synchronously process the data read / write instruction and send the processed data read / write instruction to the first address mapping unit. Specifically, the processing of the data read / write instruction may include processing operations such as parsing, judging, and caching. The parsing operation may be a preliminary parsing of the data read / write instruction, such as identifying information such as the command type and the target address. The judging operation may be a judgment of whether the command meets the sending conditions, such as checking the legality of the command. The caching operation may be placing the command that meets the conditions into the cache module. Preferably, the command that meets the conditions may be placed into a first-in-first-out queue for subsequent processing. Further, the first data path sends the processed data read / write instruction to the first address mapping unit for address parsing.

[0036] In this embodiment, two data paths are used to process the received data read / write instructions in parallel, respectively, so that the address information of the data read / write instructions can be transmitted to the bank management module in advance for pre-row activation operation, thereby reducing the delay time of the instructions.

[0037] S3: performing address mapping on the received data read / write instruction through the first address mapping unit, sending the second address information obtained by the address mapping to the bank management module, and writing the data read / write instruction after the address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information.

[0038] The first address mapping unit is used to perform address mapping on the data read / write instruction after receiving the processed data read / write operation. Specifically, the logical address in the data read / write instruction is mapped to a physical address so that the control core can correctly access the memory. The second address information can be understood as the physical address obtained by the data read / write instruction after address mapping. Furthermore, the first address mapping unit sends the second address information to the bank management module. Different from the first address information used for pre-activating the row, the second address information is used to ensure the integrity and accuracy of the data read / write instruction, so as to optimize the efficiency of memory access while ensuring the correctness of memory access.

[0039] It should be noted that, since the address information of the data read / write instruction is generated by different entities, the present application uses the descriptions such as "first" and "second" to distinguish the address information obtained by different generating entities. In fact, the first address information of the data read / write instruction carries the same content as the second address information of the current data read / write instruction. In addition, since the data read / write instruction in the first data path undergoes a series of processing operations, it takes a long time for the processed data read / write instruction to obtain the second address information through address mapping, resulting in the first address information arriving at the bank management module earlier than the second address information. Therefore, when the data read / write instruction meets the preset conditions, the bank management unit can perform a row activation operation in advance according to the first address information.

[0040] Furthermore, the data read / write instructions after address mapping are written into the command queue through the first address mapping unit. The command queue is used to store the data read / write instructions to be executed, and send the data read / write instructions to the memory bank in a timely manner, so as to ensure that all the data read / write instructions to be executed can be executed in a certain order.

[0041] S5: activating the row pointed to by the first address information in response to the first address information through the bank management module, wherein the activated row is used to process the address-mapped data read / write instruction in the command queue after a preset delay.

[0042] Specifically, after receiving the first address information sent by the second data path, the bank management module activates the target row of the bank pointed to by the first address information, and satisfies the tRCD timing after a preset delay to ensure that the data is stable in the row buffer. At this time, the command queue pops out the corresponding data read / write instruction to read or write data to the row buffer. The preset delay is determined according to the medium of the DRAM.

[0043] In view of this, the data read / write instructions are processed synchronously through two parallel data paths. When the preset conditions are met, the second data path can transmit the address information to the bank management module earlier to activate the target row and enter the waiting delay process in advance. Subsequently, after the data read / write instructions of the first data path reach the command queue after the normal processing flow, the data read / write operation can be directly executed, reducing the command delay, thereby shortening the overall time required to process the data read / write instructions, thereby improving the efficiency of memory access.

[0044] In one possible implementation, since the first address information arrives at the bank management module earlier than the second address information, if the bank management module determines that the row pointed to by the second address information has been activated, there is no need to perform an activation operation at this time. The bank management module directly discards the second address information currently received, and the command queue pops out the corresponding data read / write instruction, thereby simplifying the instruction processing flow of the bank management module and improving the efficiency of memory access.

[0045] In one possible implementation, see Figure 2 On the basis of the above step S1, the second data path includes a second address mapping unit and a logic judgment unit, and the second data path processes the data read / write instruction in the following manner: S101: The second address mapping unit maps the logical address of the data read / write instruction to a physical address, and transmits the mapped physical address to the logic judgment unit; S103: When the logic judgment unit determines that the data read / write instruction meets a preset condition, the logic judgment unit sends the mapped physical address as the first address information of the data read / write instruction to the bank management module.

[0046] The address information carried by the above data read / write instruction is a logical address. Since the address in the memory unit is a physical address, the second address mapping unit is required to map the above logical address to a physical address, thereby ensuring that the address of the target row can be accurately located.

[0047] In this embodiment, the second data path includes a second address mapping unit and a logic judgment unit. The second address mapping unit is used to map the logical address of the data read / write instruction to a physical address and transmit the physical address to the logic unit, and the logic judgment unit is used to judge whether the data read / write instruction meets the preset condition.

[0048] In this embodiment, the current data read / write command can be used as a preset condition that it is the first instruction to be processed in the command queue. In a DDR controller, the first instruction in the command queue is usually the next instruction to be executed, and when the bank management module performs row activation, it usually needs to make a comprehensive decision based on the information of other instructions in the command queue. Only when processing the first data read / write instruction to be executed in the command queue, it does not need to consider the information of other instructions. Therefore, when the second data path determines that the current data read / write instruction is the first instruction to be processed in the command queue, the bank management module can perform row activation in advance.

[0049] Specifically, the logic judgment unit obtains the current queue state of the command queue, and judges whether the data read / write instruction in the current second data path is the first instruction to be processed in the command queue according to the above queue state. If so, it is determined that the data read / write instruction meets the preset conditions.

[0050] Exemplarily, when the second data path determines that the data read / write instruction meets the preset condition, the logic judgment unit transmits the physical address as the first address information to the bank management module to pre-activate the row and wait for the preset delay. When the data read / write instruction of the first data path reaches the command queue after the normal processing flow, the data read / write operation can be directly executed, thereby improving the efficiency of memory access.

[0051] Exemplarily, when the second data path determines that the data read / write instruction does not meet the preset condition, the data read / write instruction is discarded, and the row activation is no longer performed in advance through the second data path. Normal instruction transmission is performed according to the first data path, so that the bank management module responds to the second address information obtained by the first address mapping unit and activates the row pointed to by the second address information, thereby ensuring the correctness of memory access.

[0052] The technical solution provided in this embodiment of the present application describes the specific structure of the second data path and the instruction pre-processing flow, and refines the preset conditions that must be met for pre-processing of data read / write instructions through the second data path. Only the first instruction to be processed in the command queue will be pre-activated, thereby ensuring normal data transmission in the two parallel data paths to avoid bank resource conflicts caused by instruction adjustments in the command queue.

[0053] In one possible implementation, the first data path includes at least a queue judgment unit and a first-in-first-out queue, writes data read / write instructions into the first-in-first-out queue, and pops out instructions stored in the first-in-first-out queue according to the queue status of the command queue, thereby ensuring orderly processing of instruction data and stable operation of the system.

[0054] Specifically, the data read / write instruction is written into the first-in-first-out queue, and the queue judgment unit obtains the current queue state of the command queue, and judges whether the instruction in the first-in-first-out queue can be received by the command queue according to the queue state. Further, if the queue judgment unit determines that the instruction in the first-in-first-out queue can be received by the command queue, the instruction stored in the first-in-first-out queue is popped out to the first address mapping unit. If the queue judgment unit determines that the instruction in the first-in-first-out queue cannot be received by the command queue, the current queue state of the command queue is re-obtained, and based on the re-obtained queue state, it is judged whether the instruction in the first-in-first-out queue can be received by the command queue.

[0055] The above-mentioned first-in-first-out queue manages data read / write instructions according to the first-in-first-out principle to ensure that the data read / write instructions are processed in the order of arrival to ensure data consistency. The above-mentioned command queue has a certain capacity limit. By obtaining the current queue status of the command queue, such as the length of the command queue, and determining whether to pop up the data read / write instruction according to the queue status, memory access requests can be better scheduled to avoid resource conflicts and processing delays, thereby improving the efficiency of memory access.

[0056] In a possible implementation, the control core further includes a scheduling module, which is used to sort and schedule the data read / write instructions in the command queue. The first address mapping unit transmits the address-mapped data read / write instructions to the scheduling module, so that the address-mapped data read / write instructions are written into the command queue through the scheduling module.

[0057] In this embodiment, the scheduling module transfers, sorts and schedules the data read / write instructions in the command queue according to the state of the command queue. After receiving the data read / write instruction transmitted by the first address mapping unit, the scheduling module writes the data read / write instruction into the command queue, and sorts and schedules the data read / write instructions in the command queue according to the state of the command queue.

[0058] Specifically, the row conflict information in the command queue is used as the scheduling basis, and the scheduling module obtains the address information of each instruction stored in the command queue, and determines the row conflict information in the command queue based on the obtained address information. The above row conflict information includes instructions with row conflicts in the command queue. The above row conflicting instructions can be understood as data read / write instructions in the command queue with row address information different from that of adjacent data read / write instructions. The scheduling module reorders the various instructions stored in the command queue according to the row conflict information. Among them, after the row pointed to by the first address information is activated, other instructions in the command queue carrying the first address information are processed preferentially after reordering.

[0059] In this embodiment, the order of data read / write instructions in the command queue is adjusted by adding a scheduling module to shorten the processing time of the command. Other instructions in the same row as the first instruction are processed first to ensure that other instructions in the same target row are executed earlier. At the same time, the scheduling module adjusts the order of other instructions that have row conflicts according to the address information in the command queue. Since the command queue pops up the data read / write instructions according to the timing optimization principle, it can ensure that the data read / write instructions with the same address information can be processed first, thereby reducing the number of row conflicts and further improving the efficiency of memory access.

[0060] The present application provides one or more embodiments, which can be used to transmit data read / write instructions in a DDR controller, wherein the DDR controller includes a port processing unit and a control core. The embodiment is performed according to the following steps: In one embodiment, see Figure 3 , using the traditional single-channel data processing flow to process the data read / write instructions. Specifically, after receiving the data read / write instruction, the port control unit parses the data read / write instruction and stores the data read / write instruction in a first-in-first-out queue. It is determined whether the command queue can receive the instruction in the first-in-first-out queue. If it can be received, the instruction stored in the first-in-first-out queue is popped out to the first address mapping unit, and the first address mapping unit performs address mapping on the data read / write instruction, and the address information obtained based on the address mapping is passed to the bank management module for row activation, and the data read / write instruction after address mapping is stored in the command queue. Furthermore, after the target row has been activated and waits for the tRCD timing, the data read / write instruction corresponding to the target row is taken out from the command queue and sent to the DFI interface to access the row buffer of the memory.

[0061] In another embodiment, see Figure 4, two parallel data paths are used to process the data read / write instruction. Based on the single-path data processing flow of the first data path adopted in the above embodiment, a second data path is introduced. When the data read / write instruction is the first instruction to be processed in the command queue, the data read / write instruction is address mapped and the preset condition is judged, and the second address information obtained through address mapping is sent to the bank management module in advance to perform the row activation operation in advance. When the first address information of the data read / write instruction reaches the bank management module, the timing and data meet the requirements, and the current data read / write instruction can be directly taken out from the command queue to access the row buffer.

[0062] For example, see Figure 5 The present application also provides an embodiment, using the above-mentioned row activation method, Figure 5 It represents the transmission process of data read / write instructions in the DDR controller. Specifically, when the DDR controller receives the data read / write instruction, it synchronously processes the data read / write instruction through two data paths. The second data path performs address mapping in advance to obtain the first address information, and determines whether the current data read / write instruction meets the preset condition, that is, determines whether the data read / write instruction is the first command in the command queue. If so, the first address information is sent to the bank management module. If not, the current data read / write instruction is discarded and no longer processed through the second data path.

[0063] At the same time, the data read / write instruction is transmitted through the first data path according to the traditional data processing process, the data read / write instruction is parsed and cached in the first-in-first-out queue, and it is determined whether it can be received by the command queue. If it can be received, the data read / write instruction is address mapped, and the second address information of the data read / write instruction obtained based on the address mapping is sent to the bank management module, and the data read / write instruction after address mapping is sent to the command queue through the scheduling module. The scheduling module adjusts the arrangement order of each instruction in the command queue according to the second address information of each data read / write instruction to ensure that the data read / write instruction with the same second address information can be executed first. Further, after the bank management module receives the second address information sent through the first data path, it determines whether the row pointed to by the second address information has been pre-activated. If the row pointed to by the second address information has not been activated, an activation instruction is issued to perform an activation operation on the row pointed to by the second address information. If the row pointed to by the second address information has been pre-activated, the current second address information is discarded and the activation operation is no longer performed. Exemplarily, when the first data read / write instruction arrives at the command queue, its corresponding target row has been activated in advance by the bank management module according to the first address information and meets the tRCD timing. At this time, the current data read / write instruction can be directly taken out from the command queue.

[0064] In view of this, the technical solutions provided in multiple embodiments of the present application use two parallel data paths to synchronously process read and write instructions to optimize the command processing flow, thereby improving memory access efficiency. Specifically, a second data path is introduced on the basis of the original first data path so that instructions can be transmitted through two paths at the same time, wherein the second data path can parse the address information of the instruction in advance and transmit it to the bank management module to perform row activation operations in advance. Therefore, after the command reaches the bank management module through the first data path, there is no need to wait for the delay time of row activation, but directly transmits the data read / write instruction to the downstream memory module more quickly. It can be seen that the technical solutions provided in multiple embodiments of the present application shorten the overall time required to process read and write instructions and improve the efficiency of memory access.

[0065] See also Figure 6 and Figure 7 The present application further provides a DDR controller, the DDR controller comprising a port processing unit 10 and a control core 20, the control core comprising at least a first address mapping unit 201, a bank management module 202 and a command queue 203, the port processing unit 10 comprising a first data path and a second data path in parallel, the first data path being connected to the bank management module 202 via the first address mapping unit 201, and the second data path being directly connected to the bank management module 202, wherein: The port processing unit 10 is used to receive a data read / write instruction and process the data read / write instruction through a first data path and a second data path respectively, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when determining that the data read / write instruction meets a preset condition; The first address mapping unit 201 is used to receive a data read / write instruction, and process the data read / write instruction in parallel through the first data path and the second data path, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when determining that the data read / write instruction meets a preset condition; The bank management module 202 is used to activate the row pointed to by the first address information in response to the first address information, wherein the activated row is used to process the address-mapped data read / write instruction in the command queue after a preset delay.

[0066] In one embodiment, the port processing unit is specifically used to process the data read / write instruction through the parallel first data path and the second data path. Specifically, in the first data path, the data read / write instruction is sent to the first address mapping unit after basic processing, the first address mapping unit performs address mapping on the received data read / write instruction, sends the second address information obtained by address mapping to the bank management module, and sends the data read / write instruction after address mapping to the command queue. At the same time, in the second data path, the data read / write instruction performs address mapping on the data read / write instruction when the preset conditions are met, and the address information obtained by address mapping is sent to the bank management unit in advance as the first address information.

[0067] See also Figure 8 In one embodiment, the port processing unit 10 further includes a parsing unit 101, a judging unit 102 and a first-in-first-out queue 103, which are specifically used to, after receiving a data read / write instruction, send the address information of the data processing instruction to the bank management unit in advance through the second data path. At the same time, the data read / write instruction in the first data path needs to be parsed and judged by the parsing unit and the judging unit of the port processing unit, and the data read / write instruction that meets the requirements is sent to the first-in-first-out queue for temporary storage, and the first-in-first-out queue sends the data read / write instruction to the command queue through the first address mapping unit.

[0068] In one embodiment, the first address mapping unit is specifically used to perform address mapping on the data read / write instruction after receiving the processed data read / write instruction in the first data path, map the logical address of the data read / write instruction into a physical address, and send the mapped physical address as the second address information of the data read / write instruction to the bank management module.

[0069] See also Fig. 9 In one embodiment, the control core also includes a scheduling module 204, which is used to receive data read and write instructions after address mapping in the first data path, write the data read / write instructions into the command queue, and obtain the address information of each instruction in the command queue, determine the row conflict information in the command queue according to the above address information, and reorder the data read / write instructions in the command queue based on the row conflict information.

[0070] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0071] A DDR controller in an embodiment of the present application is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, or other devices that can provide the above functions.

[0072] See also Fig.10 The present application also provides a system on chip, when a component of the system on chip issues a command, under the condition that the processor core has not cached the data of the command, a data read / fetch instruction is issued to access the memory. The system on chip includes a processor core 100, an on-chip network 200, a DDR controller 300 and a physical layer 400, wherein: The processor core 100 is used to send data read / write instructions to the DDR controller through the on-chip network; The DDR controller 200 is used to execute the above-mentioned row activation method according to the received data read / write instruction; The physical layer 400 is used to perform protocol conversion on the instructions output by the DDR controller, and transmit the protocol-converted instructions to the external memory.

[0073] In one embodiment, the above-mentioned physical layer can use PHY (Physical, port physical layer) to convert the commands of the DFI (DDR PHY Interface, an interface protocol between a memory controller and a physical layer) protocol into an actual DDR protocol interface. The above-mentioned physical layer can directly communicate with the memory device, and the commands and data processed by the physical layer access the external memory through the DDR protocol interface to read or write data.

[0074] In one embodiment, the DDR controller is specifically used to perform operations such as address conversion and timing control on data read / write instructions to ensure that the instructions meet the requirements of memory access, convert the data read / write instructions into the command format of the DFI protocol and output it to the physical layer, and convert it into a command format suitable for the DDR protocol interface through the physical layer and transmit it to the external memory.

[0075] See also Fig.11 In one embodiment, the above-mentioned system on chip may include one or more DDR controllers working in parallel to access different external memories through their respective physical layers, thereby improving the bandwidth and efficiency of memory access.

[0076] The processor core may be selected as: CPU (Central Processing Unit), GPU (Graphics Processing Unit), NPU (Neural Network Processing Unit), TPU (Tensor Processing Unit), DPU (Deep Learning Processing Unit), microprocessor, DSP (Digital Signal Processor), ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), or a combination of at least two of these processor forms. The memory stores instructions that can be executed by at least one processor, and the at least one processor may be of different types, such as CPU and FPGA, CPU and artificial intelligence processor, CPU and GPU, etc.

[0077] The above-mentioned external memory can be implemented by DDR memory particles, and the DDR memory particles are DDR SDRAM (Double Data Rate SDRAM, double rate synchronous dynamic random access memory). The storage order of its storage units is organized into a multi-level structure, namely channel, DIMM, rank, chip, Bank, row, column, and one channel corresponds to a DDR controller. Among them, each group of Ranks can be regarded as an independent external memory with an independent address space and control logic, and can perform read and write operations independently. In the external memory, different external memory modules can be accessed by selecting different Ranks.

[0078] The system on chip described in the above embodiments can be implemented by a computer chip or entity, or by a product with a certain function. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0079] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods and systems. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0080] The present application is described with reference to the flowcharts and / or block diagrams of the methods and systems according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0081] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0082] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0083] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0084] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0085] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0086] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A row activation method, characterized in that: The method is applied to a DDR controller, the DDR controller includes a port processing unit and a control core, the control core includes at least a first address mapping unit, a bank management module and a command queue, the port processing unit includes a first data path and a second data path in parallel, the first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module, the method includes: receiving a data read / write instruction through the port processing unit, and processing the data read / write instruction in parallel through the first data path and the second data path, respectively, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when determining that the data read / write instruction meets a preset condition; Performing address mapping on the received data read / write instruction through the first address mapping unit, sending second address information obtained by address mapping to the bank management module, and writing the data read / write instruction after address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information; The bank management module responds to the first address information and activates the row pointed to by the first address information, wherein the activated row is used to process the address-mapped data read / write instruction in the command queue after a preset delay.

2. The method according to claim 1, characterized in that The method further comprises: After receiving the second address information, the bank management module discards the second address information if it is determined that the row pointed to by the second address information has been activated.

3. The method according to claim 1, characterized in that The second data path includes a second address mapping unit and a logic judgment unit, and the second data path processes the data read / write instruction in the following manner: The second address mapping unit maps the logical address of the data read / write instruction into a physical address, and transmits the mapped physical address to the logic judgment unit; When the logic judgment unit determines that the data read / write instruction satisfies a preset condition, the mapped physical address is sent to the bank management module as first address information of the data read / write instruction.

4. The method according to claim 3, characterized in that The data read / write instruction meets the preset conditions including: The logic judgment unit obtains the current queue state of the command queue, and judges whether the data read / write instruction is the first instruction to be processed in the command queue according to the queue state. If so, it is determined that the data read / write instruction meets the preset condition.

5. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: When determining that the data read / write instruction does not meet a preset condition, the second data path discards the data read / write instruction, so that the bank management module activates the row pointed to by the second address information in response to the second address information.

6. The method according to claim 1 or 2, characterized in that: The first data path at least includes a queue determination unit and a first-in-first-out queue; The first data path processes the data read / write instruction in the following manner: The data read / write instruction is written into the first-in-first-out queue; The queue determination unit obtains the current queue status of the command queue, and determines whether the instructions in the first-in-first-out queue can be received by the command queue according to the queue status; if so, the instructions stored in the first-in-first-out queue are popped out to the first address mapping unit.

7. The method according to claim 6, characterized in that The method further comprises: If the queue determination unit determines that the instructions in the FIFO queue cannot be received by the command queue, the current queue state of the command queue is re-acquired, and based on the re-acquired queue state, it is determined whether the instructions in the FIFO queue can be received by the command queue.

8. The method according to claim 1 or 2, characterized in that: The control core also includes a scheduling module, and the first address mapping unit transmits the address-mapped data read / write instruction to the scheduling module, so that the address-mapped data read / write instruction is written into the command queue through the scheduling module.

9. The method according to claim 8, characterized in that The method further comprises: The scheduling module obtains address information of each instruction stored in the command queue, and determines row conflict information in the command queue based on the obtained address information; The scheduling module reorders the instructions stored in the command queue according to the row conflict information; wherein, after the row pointed to by the first address information is activated, other instructions in the command queue carrying the first address information are processed preferentially after reordering.

10. A DDR controller, characterized in that: The DDR controller includes a port processing unit and a control core, wherein the control core includes at least a first address mapping unit, a bank management module and a command queue, and the port processing unit includes a first data path and a second data path in parallel, wherein the first data path is connected to the bank management module through the first address mapping unit, and the second data path is directly connected to the bank management module, wherein: The port processing unit is used to receive a data read / write instruction, and process the data read / write instruction in parallel through the first data path and the second data path, wherein the first data path sends the processed data read / write instruction to the first address mapping unit, and the second data path sends the first address information of the data read / write instruction to the bank management module when it is determined that the data read / write instruction meets a preset condition; The first address mapping unit is used to perform address mapping on the received data read / write instruction, send the second address information obtained by address mapping to the bank management module, and write the data read / write instruction after address mapping into the command queue; wherein the first address information arrives at the bank management module earlier than the second address information; The bank management module is used to activate the row pointed to by the first address information in response to the first address information, wherein the activated row is used to process the address-mapped data read / write instruction in the command queue after a preset delay.

11. A system on chip, characterized in that: The system on chip includes a processor core, an on-chip network, a DDR controller and a physical layer, wherein: The processor core is used to send data read / write instructions to the DDR controller through the on-chip network; The DDR controller is used to execute the row activation method according to any one of claims 1 to 9 for the received data read / write instruction; The physical layer is used to perform protocol conversion on the instructions output by the DDR controller, and transmit the instructions after protocol conversion to the external memory.

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