A task timestamp recording method for simulating network communication of a multi-core system

Abstract

The application provides a task execution time stamp recording method for simulating data communication of a multi-core system, which comprises the following steps: when an operation state control unit busy signal is valid, a clock timing unit records a current task ID, records a task interval clock timer count value, and stops and clears the task interval clock timer count; a task execution clock timer count is started; when a task execution state signal changes, a task execution clock timer count value is recorded and cleared, and the count value of each state is sent to a time stamp information arrangement unit; when the task execution state jumps from a write-back state to an idle state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and a relative task ID is updated to the current task ID. The application realizes recording of multiple time stamps, and according to the recorded relative time stamp information, the order of task execution of a task in each core and the occupation time of each state can be recovered, thereby assisting in simulating a multi-core system data communication process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of heterogeneous multi-core system simulation devices, in particular to a task timestamp recording method for simulating network communication of a multi-core system. BACKGROUND

[0002] With the increase of the scale and complexity of the heterogeneous multi-core system, the difficulty and time cost of its simulation verification are increasing, so designing a flexible and efficient heterogeneous multi-core system simulation verification platform has become a hot issue in the industry. In order to solve this problem, a scheme for simulating a heterogeneous multi-core system based on software and hardware co-simulation is designed. The software and hardware co-simulator simulates the data communication in the network-on-chip through software, and the hardware is designed as a reconfigurable operation system for simulating data calculation of the multi-core system. Through software and hardware co-communication, the simulation accuracy is guaranteed while the simulation efficiency is effectively improved.

[0003] In order to accurately simulate the data communication process of the network-on-chip, the software end needs to simulate the periodical change of the running state of the real node when executing different tasks. Due to the heterogeneous characteristics of the multi-core, the software end cannot accurately simulate the periodical change of the running state of the operation unit when executing different tasks, and the timestamp information generated by the real operation unit executing the task is needed to simulate the data communication process of the network-on-chip. The traditional absolute timestamp recording method often uses a large bit width global clock counter. When collecting a large number of absolute timestamp information, a large amount of on-chip storage resources and transmission bandwidth will be occupied, which will affect the execution efficiency of the hardware platform. Although the recording of relative timestamp can greatly reduce the bit width of each timestamp, due to the large difference in execution time of different tasks, the counter must reserve a large bit width for timestamp collection, which makes the timestamp generated by the task with shorter execution time occupy a large amount of storage space with leading zeros, so that the on-chip storage resources cannot be effectively utilized. SUMMARY

[0004] The present application proposes a task execution timestamp recording method for simulating data communication of a multi-core system to solve the problem of different periodical changes of the execution state of different cores when executing different tasks, and realizes the recording of multiple timestamps.

[0005] The present application discloses a task execution timestamp recording method for simulating network communication of a multi-core system, which is based on a task execution timestamp recording circuit for simulating data communication of a multi-core system. The task execution timestamp recording circuit includes a task information register unit, an operation state control unit, a clock timing unit, a timestamp information arrangement unit and a write-back management unit. The clock timing unit includes a task interval clock timer and a task execution clock timer.

[0006] The task timestamp recording method for simulating network communication of a multi-core system comprises the following steps:

[0007] Step S1, when the operation state control unit busy signal is valid, the clock timing unit records the current task ID, records the task interval clock timer count value as the relative start timestamp RT of the task, and stops and clears the task interval clock timer count;

[0008] Step S2, start the task execution clock timer count, and when the task execution state generated by the operation state control unit changes, record and clear the task execution clock timer, and send the count value of each state to the timestamp information sorting unit;

[0009] Step S3, when the task execution state jumps back to the idle state from the write-back state, stop and clear the task execution clock timer, start the task interval clock timer, and update the relative task ID to the current task ID;

[0010] Step S4, the timestamp information sorting unit compresses and sorts the current task ID, the registered relative task ID, and the generated relative timestamp into a timestamp information sequence and stores it in the RAM.

[0011] Further, in step 1, after the task information registration unit registers a new task information, a request signal is sent to the operation state control unit, and the operation state control unit busy signal is waited to be valid. The rising edge of the busy signal indicates the start of task execution, the clock timing unit obtains the current task ID from the task information registration unit and records the task interval clock timer, and after recording, clears and stops the timer.

[0012] The count value represents the relative start timestamp RT of the current task relative to the end of the previous task execution; the timestamp and its valid signal, the current task ID and the relative task ID registered during the execution of the previous task are sent to the timestamp information sorting unit together.

[0013] Further, in step 2, the task execution state is controlled by a ring state machine in the operation state control unit, which generates different execution states in different stages of the operation unit executing the task, including idle, node content input, data input, task execution, and data write-back.

[0014] The count value of each state is the relative time of the state relative to the previous state, including node content input timestamp NT, data input timestamp DT, task execution timestamp ET, and data write-back timestamp WT; after recording the timestamp of the next state, the timestamp and its valid signal are sent to the timestamp information sorting unit for registration.

[0015] Further, in step 2, the specific process of timestamp acquisition is as follows:

[0016] S21, after the operation state control unit acquires complete task information, the execution state jumps from the idle state to the content input state, at which time the task execution clock timer is started to count; in the content input state, the address and data size of the configuration information of the operation unit are matched according to the node content register index, the node content such as configuration information or instruction file is acquired from the DDR according to the information, and the node content is written into the operation unit configuration information register and the instruction memory;

[0017] S22, after the node content is written, the operation unit enters the state of accepting calculation source data, at which time the execution state jumps to the data input state, the task execution clock timer count value is recorded and cleared, the count value is the time for the operation node to receive the node content, and serves as the node content input timestamp NT; in the data input state, the calculation source data is acquired according to the address and data size of the calculation source data registered by the calculation source data register, and the data valid signal is written into the operation unit together with the data for calculation;

[0018] S23, after the calculation source data is sent in, the operation unit starts to calculate the data, at which time the execution state jumps to the task execution state, the task execution clock timer count value is recorded and cleared, the count value is the time for the operation node to receive the calculation source data, and serves as the data input timestamp DT; the task execution state indicates that the last calculation source data is input, and the first output data is output from the operation unit;

[0019] S24, when the rising edge of the output data valid signal is detected, the execution state jumps to the data write-back state, the task execution clock timer count value is recorded and cleared, the count value is the time for the operation unit to calculate, and serves as the task execution timestamp ET; in the data write-back state, the data is written back to the corresponding address space according to the write-back address;

[0020] S25, after the write-back is completed, the execution state jumps back to the idle state, the task execution clock timer count value is recorded, the count value is the time for the data to be written back to the DDR, and serves as the data write-back timestamp WT; in the idle state, the execution state continues to wait for a new task execution request.

[0021] Further, in step 3, when the task execution state jumps back to the idle state from the write-back state, the task execution clock timer is stopped and cleared, the task interval clock timer is started to count, and the current task ID is registered; at the moment when the next task starts to be executed, the task ID is written into the timestamp information sequence as the relative task ID together with the ID of the next task.

[0022] The task interval clock timer and the task execution clock timer have enough bit width to count, and when the task execution clock timer generates a count overflow, it is an abnormal situation, and the clock counting unit generates an overflow alarm signal to report the abnormal situation; the task interval clock timer generates an overflow to indicate that the last task has been completed, and the timestamp information arrangement unit will issue a write-back request to write the remaining timestamp information sequence back to the DDR.

[0023] Further, in step 4, the timestamp arrangement process is as follows:

[0024] S41, when the task starts to execute, the current task ID and the relative task ID are registered;

[0025] S42, the clock timer counts n bits, when the relative start timestamp RT of the task arrives, the timestamp is registered; and the highest bit of the timestamp is compared with 1, when the result is 0, it indicates that the current bit is a leading zero, the leading zero counter is incremented by 1, and the value is left shifted by one bit for further judgment, until the comparison result is 1, indicating that the current bit is not a leading zero, the counter stops counting, and the count value is registered, which is the number of leading zeros of the current timestamp RT zero , then the bit width of the timestamp after removing the leading zeros is RT wid :

[0026] RT wid = n-RT zero

[0027] A set of registers Stemp_r with a bit width of 5*n are set, and the 0 to RT wid -1 bits of the timestamp after removing the leading zeros are assigned to the high RT wid bit of Stemp_r;

[0028] S43, repeat S42 to calculate the bit widths of the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET and the data write-back timestamp WT after removing the leading zeros NT wid , DT wid , ET wid and WT wid , and fill the timestamps after removing the leading zeros into the Stemp_r register in order from high to low;

[0029] S44, according to the above calculation, the actual bit width of the timestamp generated by this task is Stemp wid :

[0030] Stemp wid = RT wid + NT wid + DT wid + ETwid +WT wid

[0031] According to Stemp wid The minimum number of bytes occupied by Stemp_r is m, and the first m bytes of Stemp_r are combined with the current task ID and the relative task ID to form a time stamp information sequence and are stored in the RAM;

[0032] S45, the number of bytes stored in the RAM is recorded, and when the number of bytes occupied by one burst is satisfied, a write-back request and a write-back address are sent to the write-back management unit.

[0033] Further, the absolute time when the current task is started is EndT+RT, and the absolute time when the task is ended is EndT:

[0034] EndT=REndT+RT+NT+DT+ET+WT

[0035] REndT is the end time of the relative task, RT is the relative start time stamp of the task, NT is the node content input time stamp, DT is the data input time stamp, ET is the task execution time stamp, and WT is the data write-back time stamp;

[0036] The end time of the current task is also used as the base time for the calculation of the subsequent task, and the absolute time when all the tasks executed by the cores are started, executed and ended can be obtained, and the execution order of the tasks can be restored.

[0037] Further, the absolute time when the data generated by the current task is injected into the network is InjectT, and the time when the current task is emitted is taken as the base time BaseT:

[0038] InjectT=BaseT+NT+DT+ET

[0039] NT is the node content input time stamp, DT is the data input time stamp, and ET is the task execution time stamp;

[0040] When the global clock counter reaches this time, a virtual data packet is generated by the virtual processing unit and injected into the simulation network, so that the data communication simulation of the task is realized.

[0041] The present application has the following beneficial effects:

[0042] According to the above steps, the refined relative time stamp generated by the task execution process can be obtained with minimum storage and transmission bit width cost. According to the calculation, the starting time of all tasks after the end of the previous task and the time of each state of the task in the execution process can be obtained. Assuming that the first task of all operation units is executed at the same time, the order and occupation time of the task execution of the task at each core can be recovered according to the recorded relative time stamp information. The real calculation time generated can help simulate the state change of the multi-core system when executing the task on the real node, and assist in simulating the data communication network of the multi-core system. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 An implementation block diagram of a task execution time stamp recording circuit for simulating data communication of a multi-core system according to the present application;

[0044] Figure 2 An implementation step diagram of a task execution time stamp recording method for simulating data communication of a multi-core system according to the present application;

[0045] Figure 3 A task execution state classification diagram of a task execution time stamp recording method for simulating data communication of a multi-core system according to the present application;

[0046] Figure 4 A sequence structure diagram of time stamp information according to the present application;

[0047] Figure 5 A flowchart of a test algorithm execution in a specific embodiment of a task execution time stamp recording method for simulating data communication of a multi-core system according to the present application. DETAILED DESCRIPTION

[0048] The advantages and characteristics of the present application will become more apparent with the description. However, these embodiments are only exemplary and do not constitute any limitation on the scope of the present application. Those skilled in the art should understand that the details and forms of the technical solutions of the present application can be modified or replaced without departing from the spirit and scope of the present application, and such modifications and replacements fall within the protection scope of the present application.

[0049] As shown in the accompanying Figure 1 A task execution time stamp recording circuit for simulating data communication of a multi-core system is provided, which comprises a task information register unit, an operation state control unit, a clock timing unit, a time stamp information arrangement unit, and a write-back management unit.

[0050] The task control register unit is used to unpack and register the current task information, and initiate a task execution request to the operation control unit when the operation state control unit is idle.

[0051] The operation state control unit is electrically connected with the task information storage unit, and controls the operation unit to realize the task execution process of the operation unit and generates the task execution state information according to the task information stored in the task information storage unit;

[0052] The clock timing unit comprises a task interval clock timer and a task execution clock timer.

[0053] The task interval clock timer is used for recording the time difference between the starting time of the current task and the ending time of the previous task, and the time difference is called the relative starting time stamp RT of the task.

[0054] The task execution clock timer is used for recording the time used by each state of the operation control state machine after the operation unit receives the task information.

[0055] The time stamp information arrangement unit compresses and arranges the time stamp information generated by the time stamp timing unit, the current task number and the relative task number into a task time stamp sequence and stores the task time stamp sequence in the RAM, and sends a write-back signal to the write-back unit when the stored task time slice sequence meets the burst length.

[0056] The write-back management unit writes the data and the time stamp information back to the DDR according to the task information.

[0057] As a preferred embodiment of the present application, refer to Figure 2 The task execution time stamp recording method comprises the following steps:

[0058] S1, when the busy signal of the operation control state unit is valid, the clock timing unit records the current task ID, records the counting value of the task interval clock timer as the relative starting time stamp RT of the task, and stops and clears the counting of the task interval clock timer.

[0059] Specifically, after the task information storage unit stores a new task information, a request signal is sent to the operation state control unit, and the busy signal of the operation state control unit is waited to be valid. The rising edge of the busy signal indicates that the task starts to be executed. The clock timing unit obtains the current task ID from the task information storage unit and records the task interval clock timer. After the recording is completed, the timer is cleared and stopped. The counting value indicates the relative starting time stamp RT of the current task relative to the ending of the previous task execution. The time stamp and its valid signal, and the relative task ID stored by the previous task are sent to the time stamp information arrangement unit.

[0060] In some embodiments, the single task main field includes task ID and dependency between tasks, as listed in Table 1, and the like. When the task meets the launch condition, the processing end writes the information in the task field into the task information register unit for the operation control unit to control the operation unit to execute the task, and generates a task execution state for time stamp recording.

[0061] Table 1

[0062]

[0063] S2, start the task execution clock timer counting, and record and clear the task execution clock timer when the task execution state signal changes. The count value of each state is sent to the time stamp information processing unit.

[0064] Specifically, referring to Figure 3 , the task execution state is generated by the ring state machine in the operation state control unit for controlling the operation unit to execute the task. Different execution states are generated in different stages of the operation unit executing the task, including idle, node content input, data input, task execution, and data write back. The count value of each state is the relative time of the state relative to the previous state, including node content input time stamp NT, data input time stamp DT, task execution time stamp ET, and data write back time stamp WT. When the time stamp of the next state is recorded, the time stamp and its valid signal are sent to the time stamp information processing unit for registration.

[0065] The specific process of time stamp acquisition is as follows:

[0066] S21, after the operation state control unit acquires a complete task information, the execution state jumps from idle state to content input state, and the task execution clock timer counting is started at this time. In this state, the address and data size of the configuration information of the operation unit are matched according to the node content register index, the node content such as configuration information or instruction file is acquired from the DDR according to these information, and the node content is written into the operation unit configuration information register and the instruction memory.

[0067] S22, when the node content is written, the operation unit enters the state of accepting calculation source data, the execution state jumps to the data input state, the task execution clock timer count value is recorded and cleared, and the count value is the time used for the operation node to receive the node content, which is called node content input time stamp NT. In this state, the calculation source data is acquired according to the address and data size of the calculation source data stored in the calculation source data register, and the data valid signal is written into the operation unit together with the data for calculation.

[0068] S23, the calculation source data is sent in, the operation unit starts to calculate data, at this time the execution state jumps to the task execution state, and the task execution clock timer count value is recorded and cleared, which is the time used for the operation node to receive the calculation source data, and is called data input timestamp DT. This state indicates the time when the last calculation source data is input and the first output data is output from the operation unit.

[0069] S24, when the rising edge of the output data valid signal is detected, at this time the execution state jumps to the data write back state, and the task execution clock timer count value is recorded and cleared, which is the time used for the operation unit to calculate, and is called task execution timestamp ET. In this state, the data is written back to the corresponding address space according to the write back address.

[0070] S25, after the write back is completed, the execution state jumps back to the idle state, and the task execution clock timer count value is recorded, which is the time used for the data to be written back to the DDR, and is called data write back timestamp WT. The execution state continues to wait for a new task execution request in the idle state.

[0071] S3, when the task execution state jumps back to the idle state from the write back state, the task execution clock timer is stopped and cleared, the task interval clock timer is started, and the relative task ID is updated to the current task ID.

[0072] Specifically, when the task execution state jumps back to the idle state from the write back state, it indicates that the task execution is completed, at this time the task execution clock timer records the data write back timestamp WT and then is stopped and cleared; the task interval clock timer is started to count, which is used to record the interval time between tasks, and the current task ID is stored. When the next task starts to execute, the task ID is taken as the relative task ID, and is written into the timestamp information sequence together with the ID of the next task.

[0073] The task interval clock timer and the task execution clock timer have sufficient bit width count, and when the task execution clock timer generates count overflow, it is an abnormal situation, and the clock timing unit generates an overflow alarm signal to report the abnormal situation. When the task interval clock timer generates overflow, it indicates that the current task is the last task executed by the core, and the timestamp information arrangement unit will issue a write back request to write the remaining timestamp information sequence back to the DDR.

[0074] S4, the timestamp information arrangement unit compresses and arranges the current task ID, the stored relative task ID, and the generated relative timestamp into a timestamp information sequence and stores it in the RAM. When the stored information meets the byte number of a burst, a write back request, data size and address information are issued to the write back unit, and the write back unit writes the data back to the DDR.

[0075] Specifically, the timestamp arrangement process is as follows:

[0076] S41, register the current task ID and the relative task ID when the task starts to execute.

[0077] S42, set the clock timer to count n bits, when the relative start timestamp RT of the task arrives, register the timestamp. And compare the highest bit of the timestamp with 1, when the result is 0, it means that the current bit is a leading zero, increase the leading zero counter by 1 and left shift the value by 1 bit to judge again until the comparison result is 1, which means that the current bit is not a leading zero, stop the counter and register the count value, which is the number of leading zeros of the current timestamp RT zero , then the bit width of the timestamp after removing the leading zeros is RT wid :

[0078] RT wid =n-RT zero

[0079] Set a group of registers Stemp_r with a bit width of 5*n, assign the 0 to RT wid -1 bit of the timestamp after removing the leading zeros to the high RT wid bit of Stemp_r.

[0080] S43, repeat S42 to calculate the bit width of the node content input timestamp NT, the data input timestamp DT, the task execution timestamp ET and the data write back timestamp WT after removing the leading zeros NT wid , DT wid , ET wid and WT wid , and fill the timestamps after removing the leading zeros into Stemp_r registers in order from high bit to low bit.

[0081] S44, according to the above calculation, the actual bit width of the timestamp generated by this task is Stemp wid :

[0082] Stemp wid =RT wid +NT wid +DT wid +ET wid +WT wid

[0083] According to Stemp wid , the minimum number of bytes occupied by Stemp_r is m, combine the first m bytes of Stemp_r with the current task ID and the relative task ID to form a timestamp information sequence and store it in RAM.

[0084] S45 records the number of bytes stored in RAM. When the number of bytes required for a single burst is met, a write-back request and write-back address are sent to the write-back management unit.

[0085] In some implementation examples, refer to Figure 4 The task ID has a bit width of 16 bits, and the timestamp has a bit width of 16 bits. The timestamp, after removing leading zeros, is concatenated with the current task ID and the relative task ID. After removing leading zeros, the actual effective bit width of the timestamp information sequence register is between 40 bits and 112 bits. Based on this, the minimum number of bytes that can store this value is between 5 and 14 bytes. The value in the timestamp register is then stored in RAM in bytes based on this minimum number of bytes. Simultaneously, the actual bit width value RT of each timestamp is... wid NT wid DT wid ET wid WT wid The data is stored for later recovery of each timestamp value.

[0086] In some implementation examples, after obtaining the timestamp sequence of all tasks, the timestamp information of each task is extracted and written into a task timestamp structure array. Assuming the scheduling time of the first batch of tasks is ignored, the first task of each processing unit starts execution at the same time. Let the relative task end time be EndT, then the absolute time of the current task start is EndT+RT, and the absolute time of the task end is End:

[0087] End = EndT + RT + NT + DT + ET + WT

[0088] The current task's end time is then used as the base time for calculating subsequent tasks. This allows us to obtain the absolute times of start, execution, and end of all tasks executed by all cores, and thus restore the task execution order.

[0089] In some implementation examples, when simulating data communication networks in multi-core systems, the current mission launch completion time is used as the base time BaseT. Therefore, the absolute time InjectT for the data injected into the network by this mission is:

[0090] InjectT = BaseT + NT + DT + ET

[0091] When the global clock counter reaches this time, the virtual processing unit will generate virtual data packets and inject them into the simulated network to realize the data communication simulation of this task.

[0092] In some embodiments, a lower machine for simulating task calculation in a hardware-software cooperative multi-core emulator is a multi-core system carried by an XCZU19EG FPGA chip of Xilinx Company, which adopts AXI as an interconnection bus of an operation unit, an ARM end as a task scheduling control center of the multi-core system, and a system clock of 100Mhz. When the system adopts an absolute timestamp for collecting task execution time stamps, in order to ensure that all times of the execution process of the lower machine can be covered, a 64-bit global counter is used to count the global clock from the start to the stop of the system, and each task records five time stamps of task start, node content input, data input, task execution and data write back, plus task ID information, and the time stamp sequence of a single task is 336 bits, occupying a storage space of 42 bytes. When the method of the application is used, the time stamp timer bit width is 16 bits, and the length of the time stamp of a single task is between 40-112 bits after arrangement, occupying a storage space of 5-14 bytes. After using the recording method of the application, the length of the time stamp information sequence of a single task is reduced by 2-7 times compared with the absolute timestamp recording method.

[0093] In the embodiment, an inverse algorithm of a complex matrix based on LU decomposition is used to simulate the multi-core task execution process of the lower machine. The algorithm is mapped as five batches of tasks on the reference model, and the execution flow of the algorithm is as shown in Figure 5 The 16-order, 32-order and 64-order matrix data sets and the task list are respectively sent to the lower machine for execution calculation, and the execution cycle numbers of the three and the cycle number reduction percentage are listed in Table 2. It can be seen from the table that when the time stamp recording method of the application is used, the system can reduce about 15% of the cycle number for executing the same task, that is, the application can effectively reduce the task execution time of the system and improve the execution efficiency of the multi-core system of the lower machine.

[0094] Table 2

[0095]

[0096] The above is only the specific steps of the application, and does not constitute any limitation on the protection scope of the application; any technical solutions formed by equivalent transformation or equivalent replacement fall within the protection scope of the application; and the parts not described in detail in the application belong to the known technology of those skilled in the art.

Claims

1. A method for recording task execution timestamps for simulating network communication in multi-core systems, characterized in that, The task execution timestamp recording method for simulating network communication in a multi-core system is based on a task execution timestamp recording circuit for simulating data communication in a multi-core system. The task execution timestamp recording circuit includes a task information register unit, an operation status control unit, a clock timing unit, a timestamp information processing unit, and a write-back management unit. The clock timing unit includes a task interval clock timer and a task execution clock timer. The method for recording task timestamps to simulate network communication in a multi-core system includes the following steps: Step S1: When the busy signal of the operation status control unit is valid, the clock timing unit records the current task ID, records the task interval clock timer count value as the relative start timestamp RT of the task, and stops and clears the task interval clock timer count. Step S2: Start the task execution clock timer. When the task execution state generated by the operation state control unit changes, record and clear the task execution clock timer, and send the count value of each state to the timestamp information processing unit. Step S3: When the task execution status changes from write-back to idle, stop and clear the task execution clock timer, start the task interval clock timer, and update the relative task ID to the current task ID; Step S4: The timestamp information processing unit compresses and processes the current task ID, the registered relative task ID, and the generated relative start timestamp into a timestamp information sequence and stores it in RAM. In step S4, timestamp organization also includes: S41, when the task starts execution, store the current task ID and the relative task ID; S42, the clock timer has a bit width of n. When the relative start timestamp RT of the task arrives, the timestamp is registered. The most significant bit of the timestamp is compared with 1. If the result is 0, it means the current bit is a leading zero. The leading zero counter is incremented by one, and the value is shifted left by one bit and the comparison is repeated until the comparison result is 1, indicating that the current bit is not a leading zero. The counter is then stopped, and the count value RT is registered. This count value is the number of leading zeros RT of the current timestamp. zero Then, after removing leading zeros, the bit width of the timestamp is RT. wid : RT wid =n-RT zero Set up a register Stemp_r with a bit width of 5*n, and use the bits from 0 to RT of the timestamp according to the bit width after removing the timestamp. wid -1 bit is assigned to the high RT of Stemp_r wid Bit.

2. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that, In step S1, after the task information register unit registers a new task information, it sends a request signal to the operation status control unit and waits for the busy signal of the operation status control unit to be valid. The rising edge of the busy signal indicates that the task has started to be executed. The clock timing unit obtains the current task ID from the task information register unit and records the count value of the task interval clock timer. After recording is completed, the timer is cleared and stopped. The count value represents the relative start timestamp RT of the current task relative to the end of the previous task's execution; this timestamp and its valid signal, the current task ID, and the relative task ID stored in the previous task's execution process are sent together to the timestamp information processing unit.

3. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that, In step S2, the task execution state is generated by the ring state machine of the computing unit in the computing state control unit. Different execution states are generated at different stages of the computing unit executing the task, including: idle, node content input, data input, task execution, and data write-back. The count value for each state is the relative time of that state with respect to the previous state, including the node content input timestamp NT, data input timestamp DT, task execution timestamp ET, and data write-back timestamp WT. After recording the timestamp of the next state, the timestamp and its valid signal are sent to the timestamp information processing unit for storage.

4. The task timestamp recording method for simulating multi-core system network communication according to claim 3, characterized in that, In step S2, the specific process of obtaining the timestamp is as follows: S21. After the operation state control unit obtains a complete task information, the execution state jumps from the idle state to the node content input state. At this time, the task execution clock timer is started to count. In the node content input state, the address and data size of the configuration information of the operation unit are matched according to the node content register index. Based on this information, the node content is obtained from the DDR. The node content is the configuration information or the instruction file. The node content is written to the operation unit configuration information register and the instruction memory. S22. After the node content is written, the arithmetic unit enters the state of receiving computation source data. At this time, the execution state jumps to the data input state, and the count value of the task execution clock timer is recorded and cleared. This count value is the time taken by the arithmetic node to receive the node content, which is used as the node content input timestamp NT. In the data input state, the computation source data is obtained according to the address and data size of the computation source data stored in the computation source data register, and the data validity signal is written to the arithmetic unit together with the data for calculation. S23. After the source data is completely fed in, the arithmetic unit starts to calculate the data. At this time, the execution state jumps to the task execution state. The count value of the task execution clock timer is recorded and cleared. This count value is the time taken by the arithmetic node to receive the source data and is used as the data input timestamp DT. The task execution state indicates the time when the last source data was input and the first output data was output to the arithmetic unit. S24. When the rising edge of the output data valid signal is detected, the execution state jumps to the data write-back state. The count value of the task execution clock timer is recorded and cleared. This count value is the time used by the arithmetic unit for calculation and is used as the task execution timestamp ET. In the data write-back state, the data is written back to the corresponding address space according to the write-back address. S25. After the write-back is completed, the execution state jumps back to the idle state, and the task execution clock timer count value is recorded. This count value is the time taken to write the data back to DDR, which is used as the data write-back timestamp WT. If the execution state is in the idle state, it continues to wait for new task execution requests.

5. The task timestamp recording method for simulating multi-core system network communication according to claim 1, characterized in that, In step S3, when the task execution state transitions from write-back state to idle state, the task execution clock timer stops and is reset to zero, the task interval clock timer starts counting, and the current task ID is stored; when the next task starts execution, this task ID is used as the relative task ID and written into the timestamp information sequence together with the ID of the next task. The task interval clock timer and the task execution clock timer have sufficient bit width for counting. When the task execution clock timer overflows, it is an abnormal situation. The clock timing unit generates an overflow alarm signal and reports the abnormal situation. When the task interval clock timer overflows, it means that the last task has been completed. The timestamp information processing unit will issue a write-back request to write the remaining timestamp information sequence back to DDR.

6. The task timestamp recording method for simulating network communication in a multi-core system according to claim 1, characterized in that, In step S4, timestamp organization also includes: S43, repeat S42, calculate the node content input timestamp NT, data input timestamp DT, task execution timestamp ET, and data write-back timestamp WT, and the bit width NT after removing leading zeros. wid DT wid ET wid and WT wid And the timestamp after removing leading zeros is filled into the Stemp_r register in order from the most significant bit to the least significant bit; S44, based on the above calculations, the actual bit width of the timestamps generated in this task is Stemp. wid : Stemp wid =RT wid +NT wid +DT wid +ET wid +WT wid According to Stemp wid It can be seen that the minimum number of bytes m occupied by Stemp_r is combined with the current task ID and the relative task ID to form a timestamp information sequence and stored in RAM; S45 records the number of bytes stored in RAM. When the number of bytes required for a single burst is met, a write-back request and write-back address are sent to the write-back management unit.

7. The task execution timestamp recording method for simulating multi-core system data communication according to claim 1, characterized in that, The absolute time at which the current task started is EndT+RT, and the absolute time at which the task ended is EndT. EndT = REndT + RT + NT + DT + ET + WT Where REndT is the relative end time of the task, RT is the relative start timestamp of the task, NT is the timestamp of node content input, DT is the timestamp of data input, ET is the timestamp of task execution, and WT is the timestamp of data write-back. The current task's end time is used as the base time for subsequent tasks, allowing the calculation of the absolute times of the start, execution process, and end of all tasks executed by all cores, and thus restoring the task execution order.

8. The task execution timestamp recording method for simulating multi-core system data communication according to claim 1, characterized in that, Using the current mission launch completion time as the base time BaseT, the absolute time InjectT for the data generated by this mission injected into the network is: InjectT = BaseT + NT + DT + ET NT is the timestamp for node content input, DT is the timestamp for data input, and ET is the timestamp for task execution. When the global clock counter reaches this time, the virtual processing unit will generate virtual data packets and inject them into the simulated network to realize the data communication simulation of this task.

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