Chip welding spot thermal fatigue failure probability prediction method, device, equipment and medium
By obtaining the attribute data of the chip and PCB board and the geometric data of the solder joints, and establishing preset expressions for solving the problem of time-consuming and labor-intensive prediction of the thermal fatigue failure probability of the chip solder joints in the prior art, achieving efficient and low-cost prediction effects.
Patent Information
- Application Number
- CN202510047092.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-10
- Publication Date
- 2025-04-25
AI Technical Summary
The existing method of predicting thermal fatigue failure probability of chip solder joints is time-consuming and labor-intensive, increasing R&D costs and design cycles, making it difficult to make predictions efficiently and at low cost.
By obtaining the attribute data of the target chip and PCB board and the geometric data of the solder joints, establishing a preset expression, using approximate empirical coefficients and parameters of the thermal fatigue failure distribution shape for solving, the thermal fatigue failure probability of the chip solder joints is obtained.
No actual high and low temperature cycle testing or finite element analysis is required, which improves prediction efficiency, reduces costs and simplifies design cycles.
Smart Images
Figure CN119886027A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a method, device, equipment and medium for predicting the probability of thermal fatigue failure of chip solder joints. Background Art
[0002] Ball Grid Array Package (BGA) is an advanced integrated circuit packaging method that forms an array of spherical solder joints at the bottom of the chip. These spherical solder joints are usually arranged in a regular matrix and connected to the pads on the printed circuit board (PCB), thereby achieving electrical connection and physical fixation between the chip and the PCB. The chip is mounted on a substrate, which can be made of plastic, ceramic or other materials to provide support and electrical connection channels for the chip.
[0003] In actual operation, due to the power fluctuations caused by the server's on / off and load, as well as changes in ambient temperature, the PCB and the chip soldered to it through solder joints will generate periodic temperature cycle loads. The difference in thermal expansion coefficients between the PCB and the chip will cause the solder joints to deform, resulting in thermal strain and thermal stress. After repeated cycles, the periodic thermal strain and thermal stress will cause cracks in the solder joints to initiate and expand, eventually leading to fatigue fracture of the solder joints and affecting signal transmission. Therefore, in the overall development and design of the server, the thermal fatigue reliability (high and low temperature cycle reliability) of the solder joints is an important part of the overall reliability design of the server product.
[0004] The existing methods for predicting the probability of thermal fatigue failure of chip solder joints generally use the actual high and low temperature cycle test method of PCBA (Printed Circuit Board Assembly) samples or the method of obtaining strain, strain range and strain energy values by finite element analysis to evaluate the probability of thermal fatigue failure of chip solder joints. This method of evaluating the probability of thermal fatigue failure of chip solder joints through multiple tests is time-consuming and labor-intensive, increasing R&D costs and design cycles.
[0005] Therefore, there is an urgent need for a method that can efficiently and cost-effectively predict the probability of thermal fatigue failure of chip solder joints. Summary of the invention
[0006] In view of this, the present disclosure provides a method, device, equipment and medium for predicting the probability of thermal fatigue failure of chip solder joints.
[0007] According to a first aspect of the present invention, a method for predicting the probability of thermal fatigue failure of a chip solder joint is provided, comprising: Obtain the attribute data of the target chip and the soldered PCB board and obtain the geometric data of the solder joints connecting the two; The thermal fatigue failure distribution data of the solder joints of the target chip are obtained, a preset expression is established based on the data, and the expression is solved according to the attribute data and the geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip.
[0008] In some embodiments, the step of obtaining thermal fatigue failure distribution data of solder joints of the target chip includes: Approximate empirical coefficients and parameters of the thermal fatigue failure distribution shape of the solder joint are obtained.
[0009] In some embodiments, the step of establishing a preset expression based thereon and solving it according to the attribute data and the geometric data includes: Based on the approximate empirical coefficient and the parameters of the thermal fatigue failure distribution shape of the solder joint, a preset expression is established and solved as follows: = ( [ ; , ; ; Among them, the represents the thermal fatigue failure probability of the solder joint of the target chip, It means that the target chip has a failure probability of The corresponding load working times under the condition of represents the parameters of the thermal fatigue failure distribution shape of the solder joint, h represents the height of the solder joint connecting the target chip and the PCB board, L represents the maximum distance between all solder joints and the geometric center of the bottom surface of the target chip, represents the thermal expansion coefficient of the target chip in the horizontal direction, represents the thermal expansion coefficient of the PCB in the horizontal direction. Indicates the ductile fatigue life of the solder, represents the chip temperature of the target chip in the working state, represents the PCB board temperature of the PCB board in the working state, Indicates the component temperature of the target chip and the components corresponding to the PCB board in a non-working state, Indicates the average single duration corresponding to the non-working state. represents the average single duration corresponding to the working state, and c represents the fatigue ductility index.
[0010] In some embodiments, the step of obtaining the attribute data of the target chip and the soldered PCB board includes: Acquire temperature data and time data of the target chip and the PCB board; The thermal expansion coefficient of the target chip in the horizontal direction, the thermal expansion coefficient of the soldered PCB board in the horizontal direction, and the ductile fatigue life of the solder are obtained, and the temperature data and the time data are used as attribute data.
[0011] In some embodiments, the step of obtaining the temperature data and time data of the target chip and the PCB board includes: The temperature data and time data corresponding to the target chip and the PCB board in a non-working state and a working state are obtained respectively.
[0012] In some embodiments, the step of obtaining temperature data and time data of the target chip and the PCB board in a non-working state and a working state includes: Acquire the component temperatures of the target chip and the components corresponding to the PCB board in a non-working state, the chip temperature of the target chip in a working state, and the PCB board temperature of the PCB board in the working state as temperature data; An average single duration corresponding to the working state and an average single duration corresponding to the non-working state are obtained as time data.
[0013] In some embodiments, the step of obtaining geometric data of a welding point connecting the two includes: The height of the solder joints connecting the target chip and the PCB board, and the maximum distance between all the solder joints and the geometric center of the bottom surface of the target chip are obtained as geometric data.
[0014] According to a second aspect of the present invention, a device for predicting the probability of thermal fatigue failure of a chip solder joint is provided, the device comprising: The first module is used to obtain the attribute data of the target chip and the soldered PCB board and obtain the geometric data of the solder joint connecting the two; The second module is used to obtain the thermal fatigue failure distribution data of the solder joints of the target chip, establish a preset expression based on it and solve it according to the attribute data and the geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip.
[0015] According to a third aspect of the present invention, there is further provided an electronic device, the electronic device comprising: At least one processor; and a memory, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, the aforementioned method for predicting the probability of thermal fatigue failure of chip solder joints is executed.
[0016] According to a fourth aspect of the present invention, there is further provided a computer-readable storage medium storing a computer program, which, when executed by a processor, executes the aforementioned method for predicting the probability of thermal fatigue failure of chip solder joints.
[0017] The above-mentioned method for predicting the probability of thermal fatigue failure of chip solder joints obtains the attribute data of the target chip, the soldered PCB board, and the geometric data of the solder joints connecting the two, obtains the thermal fatigue failure distribution data of the solder joints of the target chip, establishes a preset expression based on the thermal fatigue failure distribution data of the solder joints of the target chip, and solves it according to the aforementioned acquired attribute data and geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip. The prediction process does not require actual high and low temperature cycle testing or the use of finite element analysis to obtain strain, strain range and strain energy values for evaluation, and can also predict the probability of thermal fatigue failure of chip solder joints, thereby improving the efficiency of predicting the probability of thermal fatigue failure of chip solder joints, and does not require too many tests, reducing costs.
[0018] In addition, the present invention also provides a device for predicting the probability of thermal fatigue failure of chip solder joints, an electronic device and a computer-readable storage medium, which can also achieve the above-mentioned technical effects and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.
[0020] Figure 1 A flowchart of a method for predicting the probability of thermal fatigue failure of a chip solder joint provided by the first embodiment of the present invention; Figure 2 A schematic diagram of the structure of a device for predicting the probability of thermal fatigue failure of a chip solder joint provided by another embodiment of the present invention; Figure 3 is an internal structure diagram of an electronic device in another embodiment of the present invention; Figure 4 This is a structural diagram of a computer-readable storage medium in another embodiment of the present invention. DETAILED DESCRIPTION
[0021] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0022] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.
[0023] In one embodiment, please refer to Figure 1 As shown, the present invention provides a method 100 for predicting the probability of thermal fatigue failure of chip solder joints, specifically, comprising: Step 101, obtaining attribute data of a target chip and a soldered PCB board and obtaining geometric data of solder joints connecting the two; Specifically, the target chip includes a ball grid array package chip, etc., a solder ball array is installed on the bottom of the substrate, and the solder ball is connected to the PCB as the I / O (Input / Output) end of the circuit. It is soldered to the pad of the PCB through solder during mounting. The thermal fatigue reliability of the solder joints connecting the ball grid array package chip and the PCB board is jointly affected by factors such as chip design, PCBA board design and working environment.
[0024] Specifically, the attribute data of the target chip and the soldered PCB board include the thermal expansion coefficient of the target chip in the horizontal direction. (ppm ), the thermal expansion coefficient of the PCB board in the horizontal direction (ppm ), ductile fatigue life of solder , the temperature data and time data of the target chip and PCB board. Among them, the temperature data of the target chip and PCB board include the component temperature (corresponding to the target chip and PCB board) in the non-working state , chip temperature in stable working state and PCB board temperature ; The time data of the target chip and PCB board include the average single time length of non-working state t i (min), the average single duration of stable working state t0 (min).
[0025] Specifically, the geometric data of the solder joints connecting the target chip and the soldered PCB board include the height h (mils) of the solder joints and the maximum distance L (mils) between all the solder joints and the geometric center of the bottom surface of the chip.
[0026] Step 102 , obtaining the thermal fatigue failure distribution data of the solder joints of the target chip, establishing a preset expression based thereon and solving it according to the attribute data and the geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip.
[0027] Specifically, the thermal fatigue failure distribution data may include the approximate empirical coefficient F, the parameters of the thermal fatigue failure distribution shape of the solder joint, and the parameters of the thermal fatigue failure Weibull distribution shape. .
[0028] Specifically, in the process of establishing and solving the preset expression, some ideal approximations with certain deviations from the actual situation are applied, such as factors that are ignored, including: target chip and PCB warpage, load transient change effect, solder ball shape distortion, solder internal microstructure defects, pad influence, metal material brittleness, etc. These deviations are included in it through the preset approximate empirical coefficient F. F is determined according to actual empirical values. For example, for ceramic ball grid array package chips and lead-free solder, F can be 1.2.
[0029] Specifically, the same failure mechanism and stress release process of the solder joint will produce the same thermal fatigue failure Weibull distribution shape parameters This shape parameter is independent of the operating temperature, operating time and loading frequency. Determine based on actual experience. For example, for plastic ball grid array package chips, when using lead-free solder You can choose 4, when using lead solder You can choose 2.
[0030] Specifically, based on the above approximate empirical coefficient F, the parameters of the thermal fatigue failure distribution shape of the solder joint, and the parameters of the thermal fatigue failure Weibull distribution shape Construct a preset expression, which is as follows: = ( [ (Formula 1) , (Formula 2) (Formula 3) In the above formulas 1-3, is the thermal fatigue failure probability of the target chip solder joint, The failure probability of the target chip is The corresponding load working times under the condition of, F is the approximate empirical coefficient, is the parameter of the thermal fatigue failure distribution shape of the solder joint, h is the height of the solder joint connecting the target chip and the PCB board, L is the maximum distance between all solder joints and the geometric center of the bottom surface of the target chip, Expressed as the thermal expansion coefficient of the target chip in the horizontal direction, Expressed as the thermal expansion coefficient of the PCB board in the horizontal direction, is the ductile fatigue life of the solder, is the chip temperature of the target chip in working state, is the PCB board temperature in the working state, is the component temperature of the target chip and the corresponding components of the PCB board in the non-working state, is the average single duration corresponding to the non-working state, is the average single duration corresponding to the working state, c represents the fatigue ductility index, It indicates the temperature difference between the chip temperature of the target chip in the working state and the component temperature of the target chip and the corresponding component of the PCB board in the non-working state. The temperature difference between the PCB board temperature in the working state and the component temperature of the target chip and the corresponding component of the PCB board in the non-working state is expressed. Combined with the specific values of the above parameters obtained above, the expression is solved to obtain the thermal fatigue failure probability of the solder joint of the target chip.
[0031] The above-mentioned method for predicting the probability of thermal fatigue failure of chip solder joints obtains the attribute data of the target chip, the soldered PCB board, and the geometric data of the solder joints connecting the two, obtains the thermal fatigue failure distribution data of the solder joints of the target chip, establishes a preset expression based on the thermal fatigue failure distribution data of the solder joints of the target chip, and solves it according to the aforementioned acquired attribute data and geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip. The prediction process does not require actual high and low temperature cycle testing or the use of finite element analysis to obtain strain, strain range and strain energy values for evaluation, and can also predict the probability of thermal fatigue failure of chip solder joints, thereby improving the efficiency of predicting the probability of thermal fatigue failure of chip solder joints, and does not require excessive test costs, thereby reducing costs.
[0032] According to some embodiments of the present invention, the step of obtaining thermal fatigue failure distribution data of solder joints of a target chip includes: obtaining approximate empirical coefficients and parameters of thermal fatigue failure distribution shapes of solder joints.
[0033] Specifically, the approximate empirical value can cover the main aspects that affect the probability of thermal fatigue failure of solder joints, while ignoring the minor aspects. Using the approximate empirical coefficient and the parameters of the thermal fatigue failure distribution shape of the solder joints as the thermal fatigue failure distribution data of the solder joints of the target chip can maximize the accuracy of the preset expression established subsequently and avoid deviating too much from the actual situation.
[0034] According to some embodiments of the present invention, the steps of establishing a preset expression based on the preset expression and solving it according to the attribute data and the geometric data include: establishing a preset expression based on the approximate empirical coefficient and the parameters of the thermal fatigue failure distribution shape of the solder joint and solving it to obtain the thermal fatigue failure probability of the solder joint of the target chip. Among them, the preset expression is as described in the above formulas 1-3, which will not be repeated. By solving the above expression, the thermal fatigue failure probability of the solder joint of the target chip can be obtained. The whole process does not require actual high and low temperature cycle testing or the use of finite element analysis to obtain strain, strain range and strain energy values for evaluation. The result obtained by solving the preset expression is in line with the actual situation, which improves the efficiency of predicting the thermal fatigue failure probability of the chip solder joint. The process does not require too many experiments and reduces costs.
[0035] According to some embodiments of the present invention, the step of obtaining attribute data of a target chip and a soldered PCB board includes: obtaining temperature data and time data of the target chip and the PCB board; obtaining the thermal expansion coefficient of the target chip in the horizontal direction, the thermal expansion coefficient of the soldered PCB board in the horizontal direction, and the ductile fatigue life of the solder, and using them together with the temperature data and the time data as attribute data.
[0036] Specifically, for example, when a ball grid array package chip undergoes a small thermal expansion deformation, the shear strain of the solder joint can be roughly regarded as , that is, the horizontal displacement is greater than the vertical height. This approximation converts the calculation involving strain into a calculation involving only size, which greatly reduces the difficulty of data analysis and reduces the number of parameter data that need to be input. Therefore, only a small amount of data parameters (the thermal expansion coefficient of the target chip in the horizontal direction) need to be obtained. , Thermal expansion coefficient of PCB board in horizontal direction , Ductile fatigue life of solder As well as the temperature data and time data of the target chip and PCB board), by solving the preset expression with fewer data parameters, the probability of thermal fatigue failure of the chip solder joint can be obtained, which greatly reduces the complexity of analysis and calculation.
[0037] According to some embodiments of the present invention, the step of obtaining temperature data and time data of a target chip and a PCB board includes: obtaining temperature data and time data corresponding to the target chip and the PCB board in a non-working state and a working state, respectively.
[0038] Specifically, the temperature data and time data of the target chip and PCB board obtained include those in the working state and the non-working state. For example, for a ball grid array packaged chip, in actual work, the temperature cycle load usually includes a rising period, a stable working state, a falling period and a non-working state, and the working environment temperature of the machine is superimposed. The load frequency and waveform (sine wave, square wave or triangle wave, etc.), unless it is extremely fast to cause temperature shock or extremely slow to be much longer than the stress release time, generally will not have a significant impact on the thermal fatigue results of the solder joints, and can be approximately ignored. Therefore, in the case of chip working loads, it is only necessary to obtain the temperature data and time data in the non-working state under the working state, that is, the temperature of the components in the non-working state. , chip temperature in stable working state and PCB board temperature ; Average single non-working time t i , the single duration t0 of the average stable working state reduces the complexity of obtaining temperature and time parameters.
[0039] According to some embodiments of the present invention, the step of obtaining temperature data and time data of a target chip and a PCB board in a non-working state and a working state includes: obtaining component temperatures of components corresponding to the target chip and the PCB board in a non-working state, a chip temperature of the target chip in a working state, and a PCB board temperature of the PCB board in a working state as temperature data; obtaining an average single duration corresponding to the working state and an average single duration corresponding to the non-working state as time data.
[0040] According to some embodiments of the present invention, the step of obtaining geometric data of solder joints connecting the two includes: obtaining the height of solder joints connecting the target chip and the PCB board, and the maximum distance between all solder joints and the geometric center of the bottom surface of the target chip as geometric data.
[0041] In some embodiments, please refer to Figure 2 As shown, the present invention also provides a device 200 for predicting the thermal fatigue failure probability of chip solder joints, the device comprising: a first module 201, for acquiring the attribute data of a target chip and a soldered PCB board and acquiring the geometric data of the solder joints connecting the two; a second module 202, for acquiring the thermal fatigue failure distribution data of the solder joints of the target chip, establishing a preset expression based thereon and solving it according to the attribute data and the geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip.
[0042] It should be noted that each module in the above-mentioned device for predicting the probability of thermal fatigue failure of chip solder joints can be implemented in whole or in part by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of a processor in an electronic device in the form of hardware, or can be stored in a memory in the electronic device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.
[0043] According to another aspect of the present invention, an electronic device is provided. The electronic device may be a server. Figure 3 As shown. The electronic device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the electronic device is used to store data. The network interface of the electronic device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the method for predicting the probability of thermal fatigue failure of a chip solder joint described above is implemented.
[0044] According to another aspect of the present invention, a computer readable storage medium is provided. Figure 4 As shown, a computer program is stored thereon, and when the computer program is executed by a processor, the above-mentioned method for predicting the probability of thermal fatigue failure of chip solder joints is implemented.
[0045] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
[0046] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0047] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. A method for predicting the probability of thermal fatigue failure of chip solder joints, characterized in that: include: Obtain the attribute data of the target chip and the soldered PCB board and obtain the geometric data of the solder joints connecting the two; The thermal fatigue failure distribution data of the solder joints of the target chip are obtained, a preset expression is established based on the data, and the expression is solved according to the attribute data and the geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip.
2. The method for predicting chip solder joint thermal fatigue failure probability according to claim 1, characterized in that: The step of obtaining thermal fatigue failure distribution data of solder joints of the target chip comprises: Approximate empirical coefficients and parameters of the thermal fatigue failure distribution shape of the solder joint are obtained.
3. The method for predicting chip solder joint thermal fatigue failure probability according to claim 2, characterized in that: The step of establishing a preset expression based thereon and solving it according to the attribute data and the geometric data comprises: Based on the approximate empirical coefficient and the parameters of the thermal fatigue failure distribution shape of the solder joint, a preset expression is established and solved as follows: = ( [ ； ， ； ； Among them, the represents the thermal fatigue failure probability of the solder joint of the target chip, It means that the target chip has a failure probability of The corresponding load working times under the condition of represents the parameters of the thermal fatigue failure distribution shape of the solder joint, h represents the height of the solder joint connecting the target chip and the PCB board, L represents the maximum distance between all solder joints and the geometric center of the bottom surface of the target chip, represents the thermal expansion coefficient of the target chip in the horizontal direction, represents the thermal expansion coefficient of the PCB in the horizontal direction. Indicates the ductile fatigue life of the solder, represents the chip temperature of the target chip in the working state, represents the PCB board temperature of the PCB board in the working state, Indicates the component temperature of the target chip and the components corresponding to the PCB board in a non-working state, Indicates the average single duration corresponding to the non-working state. represents the average single duration corresponding to the working state, and c represents the fatigue ductility index.
4. The method for predicting chip solder joint thermal fatigue failure probability according to claim 1, characterized in that: The step of obtaining the attribute data of the target chip and the soldered PCB board comprises: Acquire temperature data and time data of the target chip and the PCB board; The thermal expansion coefficient of the target chip in the horizontal direction, the thermal expansion coefficient of the soldered PCB board in the horizontal direction, and the ductile fatigue life of the solder are obtained, and the temperature data and the time data are used as attribute data.
5. The method for predicting chip solder joint thermal fatigue failure probability according to claim 4, characterized in that: The step of obtaining the temperature data and time data of the target chip and the PCB board includes: The temperature data and time data corresponding to the target chip and the PCB board in a non-working state and a working state are obtained respectively.
6. The method for predicting chip solder joint thermal fatigue failure probability according to claim 5, characterized in that: The step of obtaining the temperature data and time data of the target chip and the PCB board in a non-working state and a working state comprises: Acquire the component temperatures of the target chip and the components corresponding to the PCB board in a non-working state, the chip temperature of the target chip in a working state, and the PCB board temperature of the PCB board in the working state as temperature data; An average single duration corresponding to the working state and an average single duration corresponding to the non-working state are obtained as time data.
7. The method for predicting chip solder joint thermal fatigue failure probability according to claim 1, characterized in that: The step of obtaining geometric data of the welding point connecting the two comprises: The height of the solder joints connecting the target chip and the PCB board, and the maximum distance between all the solder joints and the geometric center of the bottom surface of the target chip are obtained as geometric data.
8. A device for predicting the probability of thermal fatigue failure of chip solder joints, characterized in that: The device comprises: The first module is used to obtain the attribute data of the target chip and the soldered PCB board and obtain the geometric data of the solder joint connecting the two; The second module is used to obtain the thermal fatigue failure distribution data of the solder joints of the target chip, establish a preset expression based on it and solve it according to the attribute data and the geometric data to obtain the thermal fatigue failure probability of the solder joints of the target chip.
9. An electronic device, characterized in that: include: at least one processor; as well as A memory storing a computer program executable in the processor, wherein the processor executes the method for predicting the probability of thermal fatigue failure of a chip solder joint as claimed in any one of claims 1 to 7 when executing the program.
10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for predicting the probability of thermal fatigue failure of a chip solder joint as claimed in any one of claims 1 to 7 is performed.