Quick GPU (Graphics Processing Unit) implementation method, system, equipment and medium for anti-quantum cryptography algorithm

Abstract

The invention discloses a quick GPU (Graphics Processing Unit) implementation method, system and equipment for an anti-quantum cryptography algorithm and a medium. The quick GPU implementation method comprises the following steps: acquiring the anti-quantum cryptography algorithm configured by a user; analyzing parallelism of sub-modules in the anti-quantum cryptography algorithm, and determining parallel parameters of the sub-modules in the anti-quantum cryptography algorithm; setting an anti-quantum cryptography algorithm asynchronous transmission mode; and configuring a task-level memory pool mechanism, and realizing memory layout of the anti-quantum cryptography algorithm on the GPU by setting a storage sequence and an alignment mode of elements. According to the method, the execution efficiency of algorithms on different GPUs is improved to the maximum extent by determining the optimal parallel parameters, a universal memory optimization strategy is provided, the method is suitable for various anti-quantum cryptography algorithms, and the optimization difficulty caused by memory layout differences is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of quantum computing, and in particular relates to a fast GPU implementation method, system, device, and medium for anti-quantum cryptographic algorithms. Background Art

[0002] The rapid development of quantum computing poses an unprecedented threat to traditional cryptographic systems. In particular, public key cryptographic algorithms (such as RSA and ECC) are considered unsafe in a quantum computing environment. This is because Shor's algorithm shows that quantum computers can crack these encryption methods based on difficult mathematical problems in polynomial time. Therefore, researchers have begun to focus on the development of quantum-resistant cryptographic algorithms to ensure the security of information in the quantum computing era.

[0003] Many quantum-resistant cryptographic algorithms, such as lattice-based algorithms and hash-based signature schemes, usually involve complex mathematical operations and data processing, which limits their execution speed on the CPU. In order to achieve the effective execution of quantum-resistant cryptographic algorithms, GPU (Graphics Processing Unit) as a powerful parallel computing platform is receiving more and more attention. GPU has extremely high computing parallel capability and is suitable for processing a large number of computing tasks of the same type. Using GPU to accelerate quantum-resistant cryptographic algorithms has become a general acceleration method.

[0004] Although GPUs can provide powerful computing power, they still face many challenges in the implementation of quantum-resistant cryptographic algorithms. GPU acceleration is generally divided into four categories: parallel computing optimization, memory optimization, algorithm design and reconstruction optimization, and hardware selection and configuration optimization. Among them, algorithm design and reconstruction optimization requires an in-depth understanding of quantum-resistant cryptographic algorithms. Due to their inherent complexity, quantum-resistant cryptographic algorithms have a high entry cost, and each algorithm has different principles and transformation plans, so the optimization time cost is high. Hardware selection and configuration optimization require specific adapter firmware, and different algorithms may have different adapter hardware, so the optimization cost is high. Algorithm design and reconstruction optimization and hardware selection and configuration optimization are more suitable for targeted optimization and transformation of specific quantum-resistant algorithms to obtain optimal performance. Parallel computing optimization reduces the overall time consumption by decomposing computing tasks into multiple subtasks that can be executed in parallel. However, for different GPUs or different algorithm submodules, the performance of parallel computing will also vary greatly due to different degrees of parallelism. How to determine the appropriate number of parallelism to achieve optimal performance is a challenge. In memory optimization, due to the different memory data layouts of different algorithms, how to find common points for universal optimization is the second challenge.

[0005] In summary, in practical applications, how to effectively utilize the advantages of GPU without introducing too much complexity and actual cost and without the need for a deep understanding of quantum cryptographic algorithms is an urgent problem to be solved. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention provides a fast GPU implementation method, system, device, and medium for a quantum-resistant cryptographic algorithm.

[0007] In a first aspect, an embodiment of the present invention provides a fast GPU implementation method for a quantum-resistant cryptographic algorithm, the method comprising:

[0008] Get the quantum-resistant cryptographic algorithm configured by the user;

[0009] Analyze the parallelism of submodules in quantum-resistant cryptographic algorithms and determine the parallel parameters of submodules in quantum-resistant cryptographic algorithms;

[0010] Set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of the elements.

[0011] In a second aspect, an embodiment of the present invention provides a fast GPU implementation system for a quantum-resistant cryptographic algorithm, the system comprising:

[0012] The algorithm interface layer is used to obtain the quantum-resistant cryptographic algorithm configured by the user;

[0013] A parallel processing module is used to analyze the parallelism of submodules in the quantum-resistant cryptographic algorithm and determine the parallel parameters of submodules in the quantum-resistant cryptographic algorithm;

[0014] The memory management module is used to set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements.

[0015] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the above-mentioned fast GPU implementation method for quantum-resistant cryptographic algorithms.

[0016] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-mentioned fast GPU implementation method for quantum-resistant cryptographic algorithms.

[0017] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the above-mentioned fast GPU implementation method for quantum-resistant cryptographic algorithms.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The present invention provides a fast GPU implementation method for a quantum-resistant cryptographic algorithm, which maximizes the execution efficiency of the algorithm on different GPUs by determining the optimal parallel parameters. The present invention also provides a general memory optimization strategy that is applicable to a variety of quantum-resistant cryptographic algorithms, reducing the optimization difficulty caused by differences in memory layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0021] Figure 1 A schematic diagram of a fast GPU implementation system for a quantum-resistant cryptographic algorithm provided by an embodiment of the present invention;

[0022] Figure 2 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] It should be noted that, in the absence of conflict, the features in the following embodiments and implementations may be combined with each other.

[0025] In order to solve the problem that the degree of parallelism of different sub-modules of different quantum-resistant cryptographic algorithms needs to be adapted on different types of GPUs, resulting in inconsistent performance, and the difference in memory layout of different quantum-resistant cryptographic algorithms makes it difficult to unify the common memory optimization strategy within the sub-algorithms, the present invention proposes a universal fast GPU implementation method and system for quantum-resistant cryptographic algorithms.

[0026] At the same time, quantum-resistant cryptographic algorithms are mainly divided into two categories: key encapsulation and digital signature. In actual use, whether it is encryption and decryption or digital signature, the request to the internal implementation of the protocol must be in batch form, so there are two optimization granularities: fine-grained optimization of a single request and batch optimization. The fine-grained optimization of a single request is bound to involve the intrusion of a specific algorithm due to its optimization granularity problem. As a universal framework, this invention does not involve this. The present invention focuses on multi-request GPU performance optimization under batch processing.

[0027] like Figure 1 As shown, an embodiment of the present invention provides a fast GPU implementation method for a quantum-resistant cryptographic algorithm, the method comprising the following steps:

[0028] Get the quantum-resistant cryptographic algorithm configured by the user;

[0029] Analyze the parallelism of submodules in quantum-resistant cryptographic algorithms and determine the parallel parameters of submodules in quantum-resistant cryptographic algorithms;

[0030] Set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of the elements.

[0031] Furthermore, the quantum-resistant cryptographic algorithm includes a quantum-resistant key encapsulation algorithm and a quantum-resistant digital signature algorithm; the quantum-resistant key encapsulation algorithm includes: a key pair generation submodule, a key encapsulation submodule, and a key decapsulation submodule; the quantum-resistant digital signature algorithm includes: a key pair generation submodule, a signature submodule, and a signature verification interface submodule. Among them, the key encapsulation submodule includes: a number theory transformation module and a random number matrix generation module.

[0032] Furthermore, the process of analyzing the parallelism of the submodules in the quantum-resistant cryptographic algorithm and determining the parallel parameters of the submodules in the quantum-resistant cryptographic algorithm includes:

[0033] Get the prop set of the corresponding GPU series property values ​​through the cudaGetDeviceProperties function;

[0034] Set blockSize∈(1, prop.maxThreadsPerBlock); prop.maxThreadsPerBlock represents the maximum number of threads in each block supported by the GPU;

[0035] Set gridSize = (COUNT + blockSize - 1) / blockSize; where blockSize is the number of threads in a block, gridSize is the number of blocks in a grid, and COUNT is the total number of requests in a batch.

[0036] Using the multithreading paradigm func< in CUDA programming<gridSize,blockSize> >(), call the submodules in the quantum-resistant key encapsulation algorithm in parallel with different gridSize and blockSize, and record the calling time;

[0037] The gridSize and blockSize corresponding to the minimum call time are used as the parallel parameters of the submodule.

[0038] Furthermore, setting the asynchronous transmission mode of the quantum-resistant cryptographic algorithm includes:

[0039] Use cudaHostAlloc interface to allocate page-locked memory;

[0040] Use cudaMalloc interface to allocate GPU memory;

[0041] Use the cudaMemcpyAsync interface to perform asynchronous data transmission between CPU and GPU.

[0042] Furthermore, the process of configuring the task-level memory pool mechanism and setting the storage order and alignment of elements to achieve the memory layout of the quantum-resistant cryptographic algorithm on the GPU includes:

[0043] The submodules of quantum-resistant cryptographic algorithms include variable application and variable use;

[0044] Configure the task-level memory pool mechanism, consider the storage order and alignment of elements, apply for memory according to the continuous addresses of the input byte stream, and allocate linear memory by using span allocation to achieve element alignment, thereby realizing the memory layout of quantum-resistant cryptographic algorithms on the GPU.

[0045] like Figure 2 As shown, an embodiment of the present invention provides a fast GPU implementation system for a quantum-resistant cryptographic algorithm, the system comprising:

[0046] The algorithm interface layer is used to receive the quantum-resistant cryptographic algorithm configured by the user and adapt the quantum-resistant cryptographic algorithm to the GPU;

[0047] The parallel processing module is used to analyze the parallelism of submodules in the quantum-resistant cryptographic algorithm and determine the optimal parallel parameters of submodules in the quantum-resistant cryptographic algorithm;

[0048] The memory management module is used to process the memory layout of the quantum-resistant cryptographic algorithm and set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm. It configures the task-level memory pool mechanism and implements the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements to improve data access efficiency.

[0049] Furthermore, a quantum-resistant key encapsulation algorithm sub-interface and a quantum-resistant digital signature algorithm sub-interface are defined in the algorithm interface layer; wherein the quantum-resistant key encapsulation algorithm sub-interface includes: a key pair generation sub-module, a key encapsulation sub-module, and a key decapsulation sub-module; wherein the key pair generation sub-module, the signature sub-module, and the signature verification interface sub-module.

[0050] Furthermore, the definition of the quantum-resistant key encapsulation algorithm sub-interface is as follows:

[0051]

[0052]

[0053] It should be noted that in this example, the crypto_kem_keypair interface is defined to implement the key pair generation submodule; when the user calls the key pair generation submodule interface crypto_kem_keypair, the public key pk and private key sk are generated through the encryption algorithm, and the generated public key pk is output to the public key parameter, and the private key sk is output to the private key parameter for subsequent key encapsulation and decapsulation operations.

[0054] The crypto_kem_enc interface function is defined to implement the key encapsulation submodule; when the user calls the key encapsulation submodule interface crypto_kem_enc, the input parameter is the public key pk, and a ciphertext ct and a shared key ss are generated through the key encapsulation algorithm. The generated ciphertext ct is returned as output to the specified ciphertext parameter, and the generated shared key ss is returned to the shared key parameter. The main function of this interface is to ensure that the communicating parties can securely negotiate a shared key under the protection of the public key.

[0055] The crypto_kem_dec interface function is defined to implement the key decapsulation submodule; when the user calls the key decapsulation submodule interface crypto_kem_dec, the ciphertext ct is decapsulated by the key decapsulation algorithm to recover the corresponding shared key ss. The decapsulated shared key ss will be returned to the specified shared key parameter for encrypted communication with the encapsulation party.

[0056] Through the crypto_kem_keypair interface function, crypto_kem_enc interface function, and crypto_kem_dec interface function, users can generate key pairs, securely encapsulate and decapsulate keys, and ensure secure exchange and sharing of keys during communication.

[0057] Furthermore, the definition of the quantum-resistant digital signature algorithm sub-interface is as follows:

[0058]

[0059] It should be noted that in this example, the crypto_sign_keypair interface function is defined to implement the key pair generation submodule. The user generates a pair of keys by calling the key pair generation submodule interface crypto_sign_keypair, where the public key pk is used to verify the signature and the private key sk is used for the signature operation. The public key pk and the private key sk are passed to the caller through output parameters respectively. The public key pk can be used in the signature verification process, and the private key sk is used to generate the signature.

[0060] The crypto_sign interface function is defined to implement the signature submodule. Users call the signature submodule interface crypto_sign to sign messages. The input message data is processed by the signature algorithm to generate a signature. The user needs to provide the message data and the private key as input. The interface will generate a signature for the message and return the signature. The signature result is passed through the output parameter, and the returned signature length is also returned through a pointer. This interface ensures the integrity and non-repudiation of the message, that is, it ensures that the message is signed by the party holding the private key.

[0061] The crypto_sign_open interface function is defined for the signature verification interface submodule. Users call the signature verification interface submodule crypto_sign_open to verify the signature of the message. The input includes the signed message, the signature, and the corresponding public key. The interface verifies whether the signature matches the message and confirms the source and integrity of the message. If the signature is valid, the interface returns the content of the message and ensures that the message has not been tampered with. If the signature is invalid, an error is returned and the signature verification fails.

[0062] The digital signature mechanism is implemented through the crypto_sign_keypair interface function, crypto_sign interface function, and crypto_sign_open interface function to ensure the legitimacy, integrity, and non-repudiation of the message. Through the generation of key pairs of public and private keys, users can safely sign messages and use public keys to verify signatures to ensure message security during communication.

[0063] Furthermore, in the parallel processing module, on the basis of the unified algorithm layer interface, this example makes the slice processing parallel and determines the degree of parallelism. In GPU programming, especially when using CUDA (NVIDIA's parallel computing platform and programming model), thread, block and grid are three basic concepts used to organize and manage parallel computing tasks. Among them, thread is the basic execution unit in GPU. Each thread independently executes a piece of code (usually called a kernel function, Kernel). A large number of threads is the basis for GPU to achieve large-scale parallel computing. Block is a collection of threads. The number of threads in each block is limited. Threads share some resources in the same block, such as shared memory and synchronization mechanisms, which enables threads in the block to collaborate efficiently. Grid is a larger structure composed of multiple blocks, which can be understood as a collection of blocks. Each block is responsible for processing different subsets of data. When executing, GPU will assign all blocks of a grid to multiple streaming processors (Streaming Multiprocessors, SMs) to let them perform calculations simultaneously.

[0064] Furthermore, the parallel processing module analyzes the parallelism of the submodules in the quantum-resistant cryptographic algorithm, and the process of determining the parallel parameters of the submodules in the quantum-resistant cryptographic algorithm includes:

[0065] Get the prop set of the corresponding GPU series property values ​​through the cudaGetDeviceProperties function;

[0066] Set blockSize∈(1, prop.maxThreadsPerBlock); prop.maxThreadsPerBlock represents the maximum number of threads in each block supported by the GPU;

[0067] Set gridSize = (COUNT + blockSize - 1) / blockSize; where blockSize is the number of threads in a block, gridSize is the number of blocks in a grid, and COUNT is the total number of requests in a batch.

[0068] Using the multithreading paradigm func< in CUDA programming<gridSize,blockSize> >(), call the submodules in the quantum-resistant key encapsulation algorithm in parallel with different gridSize and blockSize, and record the calling time;

[0069] The gridSize and blockSize corresponding to the minimum call time are used as the parallel parameters of the submodule.

[0070] It should be noted that in this example, the parallel parameters of all sub-modules are confirmed in this way in turn. If the user needs to further optimize the parallelism within the sub-algorithm, for example, the key encapsulation sub-algorithm often has NTT (Number Theoretic Transform), random number matrix generation and other sub-modules, the above method can also be used.

[0071] Furthermore, setting the asynchronous transmission mode of the quantum-resistant cryptographic algorithm includes:

[0072] Extracting common elements in the algorithm interface layer; the common elements are public and private keys, shared keys, random seeds in the key encapsulation algorithm, or public and private keys, signatures, messages, random seeds in the digital signature algorithm;

[0073] Use the cudaHostAlloc interface to allocate page-locked memory; use the cudaMalloc interface to allocate GPU memory; use the cudaMemcpyAsync interface to perform asynchronous data transmission between CPU and GPU.

[0074] Among them, the memory management module uses cudaHostAlloc, cudaMalloc, and cudaMemcpyAsync to implement memory allocation and asynchronous transmission of common elements of the algorithm interface layer. The description of the cudaHostAlloc, cudaMalloc, and cudaMemcpyAsync interfaces is shown in Table 1 below:

[0075] Table 1: Memory management data interaction related interface description table

[0076]

[0077] It should be noted that page-locked memory allows asynchronous data transfer, which means that the CPU can exchange data with the GPU while performing other tasks, thereby improving the parallel utilization of the CPU and GPU. Without page-locked memory, cudaMemcpyAsync cannot work asynchronously, resulting in the data transfer having to block the CPU, waiting for the transfer to complete before continuing to perform other tasks. At the same time, page-locked memory allows data to be transferred directly between the GPU and the CPU via DMA, bypassing the operating system's paging mechanism, thereby significantly improving the bandwidth and speed of data transfer, especially for large data transfers. When non-page-locked memory is transferred, the paging mechanism may schedule memory blocks to disk, increasing transmission delays and overhead.

[0078] Furthermore, the task-level memory pool mechanism is configured to set the storage order and alignment of elements, thereby realizing the memory layout of the key pair generation, key encapsulation, key decapsulation interface under the quantum-resistant key encapsulation algorithm sub-interface or the key pair generation, signature, and signature verification interface under the quantum-resistant digital signature algorithm sub-interface on the GPU. The process includes:

[0079] The submodules of quantum-resistant cryptographic algorithms include variable application and variable use;

[0080] Configure the task-level memory pool mechanism, consider the storage order and alignment of elements, apply for memory according to the continuous addresses of the input byte stream, and allocate linear memory by using span allocation to achieve element alignment, thereby realizing the memory layout of quantum-resistant cryptographic algorithms on the GPU.

[0081] It should be noted that in order to ensure effective memory access during concurrent task processing, this example implements a fixed-size task-level memory pool mechanism. The implemented task-level memory pool mechanism involves two important considerations: the storage order of elements and alignment requirements. This example applies for memory according to the continuous addresses of the input byte stream, thereby eliminating the overhead associated with stream concatenation. Secondly, this example allocates linear memory by using span allocation to meet the alignment requirements.

[0082] For example, if a signature algorithm needs to perform Hash operations Hash(A,B) and Hash(C,D) on four elements A, B, C, and D, we will arrange the memory address allocation of A, B, C, and D according to the subsequent access order of A, B, C, and D to ensure sequential reading and priority hits. At the same time, since the L2 memory request granularity is a cache line of 128 bytes, we can reasonably arrange the alignment of A, B, C, and D so that a single element or several elements are aligned to 128 bytes, and the rest are filled with padding bytes to ensure that as few cache lines as possible can be hit when reading.

[0083] By implementing this task-level memory pool mechanism, this example significantly reduces the cost of frequent memory allocation and release during the calculation process, thereby improving performance. This approach further promotes the optimization of memory management, thereby enabling the efficient processing of multiple tasks while maintaining high performance levels.

[0084] According to an embodiment of the present invention, the present invention also provides an electronic device and a readable storage medium.

[0085] Figure 2A schematic block diagram of an electronic device that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0086] The electronic device includes a computing unit 201, which can perform various appropriate actions and processes according to a computer program stored in ROM 202 or a computer program loaded from a storage unit 208 into RAM 203. In RAM 203, various programs and data required for the operation of the electronic device can also be stored. The computing unit 201, ROM 202, and RAM 203 are connected to each other via a bus 204. An I / O interface 205 is also connected to the bus 204.

[0087] A number of components in the electronic device are connected to the I / O interface 205, including: an input unit 206, such as a keyboard, a mouse, etc.; an output unit 207, such as various types of displays, speakers, etc.; a storage unit 208, such as a disk, an optical disk, etc.; and a communication unit 209, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 209 allows the electronic device to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0088] The computing unit 201 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 201 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 201 performs the various methods and processes described above. For example, in some embodiments, the method in the multidimensional early warning system for pressure injuries may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 208. In some embodiments, part or all of the computer program may be loaded and / or installed on an electronic device via ROM 202 and / or a communication unit 209. When the computer program is loaded into RAM 203 and executed by the computing unit 201, one or more steps of the method in the multidimensional early warning system for pressure injuries described above may be executed. Alternatively, in other embodiments, the computing unit 201 may be configured to execute the method in the multidimensional early warning system for pressure injuries by any other appropriate means (e.g., by means of firmware).

[0089] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0090] The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, partially on the machine as a stand-alone software package and partially on a remote machine, or entirely on a remote machine or server.

[0091] In the context of the present invention, a readable storage medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A readable storage medium may be a machine-readable signal medium or a machine-readable storage medium. A readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. More specific examples of readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0092] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0093] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communications network). Examples of communications networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0094] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0095] Those skilled in the art will readily appreciate other embodiments of the present application after considering the description and practicing the contents disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary technical means in the art that are not disclosed in the present application. The description and examples are intended to be exemplary only.

[0096] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A fast GPU implementation method for quantum-resistant cryptographic algorithms, characterized in that: The method comprises: Get the quantum-resistant cryptographic algorithm configured by the user; Analyze the parallelism of submodules in quantum-resistant cryptographic algorithms and determine the parallel parameters of submodules in quantum-resistant cryptographic algorithms; Set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of the elements.

2. A fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 1, characterized in that: The quantum-resistant cryptographic algorithm includes a quantum-resistant key encapsulation algorithm and a quantum-resistant digital signature algorithm; The quantum-resistant key encapsulation algorithm includes: a key pair generation submodule, a key encapsulation submodule, and a key decapsulation submodule; The quantum-resistant digital signature algorithm includes: a key pair generation submodule, a signature submodule, and a signature verification interface submodule.

3. A fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 2, characterized in that: The key encapsulation submodule includes: a number theory transformation module and a random number matrix generation module.

4. A fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 1, characterized in that: The process of analyzing the parallelism of submodules in the quantum-resistant cryptographic algorithm and determining the parallel parameters of submodules in the quantum-resistant cryptographic algorithm includes: Get the prop set of the corresponding GPU series property values ​​through the cudaGetDeviceProperties function; Set blockSize∈(1, prop.maxThreadsPerBlock); prop.maxThreadsPerBlock represents the maximum number of threads in each block supported by the GPU; Set gridSize = (COUNT + blockSize - 1) / blockSize; where blockSize is the number of threads in a block, gridSize is the number of blocks in a grid, and COUNT is the total number of requests in a batch. Using the multithreading paradigm func< in CUDA programming<gridSize,blockSize> >(), call the submodules in the quantum-resistant key encapsulation algorithm in parallel with different gridSize and blockSize, and record the calling time; The gridSize and blockSize corresponding to the minimum call time are used as the parallel parameters of the submodule.

5. The fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 1, characterized in that: Setting up the asynchronous transmission method of quantum-resistant cryptographic algorithms includes: Use cudaHostAlloc interface to allocate page-locked memory; Use cudaMalloc interface to allocate GPU memory; Use the cudaMemcpyAsync interface to perform asynchronous data transmission between CPU and GPU.

6. A fast GPU implementation method for quantum-resistant cryptographic algorithms according to claim 1, characterized in that: The process of configuring the task-level memory pool mechanism to implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of the elements includes: The submodules of quantum-resistant cryptographic algorithms include variable application and variable use; Configure the task-level memory pool mechanism, consider the storage order and alignment of elements, apply for memory according to the continuous addresses of the input byte stream, and allocate linear memory by using span allocation to achieve element alignment, thereby realizing the memory layout of quantum-resistant cryptographic algorithms on the GPU.

7. A fast GPU implementation system for quantum-resistant cryptographic algorithms, characterized in that: The system comprises: The algorithm interface layer is used to obtain the quantum-resistant cryptographic algorithm configured by the user; A parallel processing module is used to analyze the parallelism of submodules in the quantum-resistant cryptographic algorithm and determine the parallel parameters of submodules in the quantum-resistant cryptographic algorithm; The memory management module is used to set the asynchronous transmission mode of the quantum-resistant cryptographic algorithm; configure the task-level memory pool mechanism, and implement the memory layout of the quantum-resistant cryptographic algorithm on the GPU by setting the storage order and alignment of elements.

8. An electronic device, comprising a memory and a processor, characterized in that: The memory is coupled to the processor; wherein the memory is used to store program data, and the processor is used to execute the program data to implement the fast GPU implementation method for quantum-resistant cryptographic algorithms as described in any one of claims 1-6 above.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the fast GPU implementation method for a quantum-resistant cryptographic algorithm as described in any one of claims 1 to 6 is implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by a processor, the fast GPU implementation method for a quantum-resistant cryptographic algorithm described in any one of claims 1 to 6 is implemented.

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