Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a wire-avoiding area, a wiring area and a wire-avoiding area; the array substrate further comprises a substrate and a plurality of pixel driving circuits arranged on the substrate; the array substrate comprises at least one first signal line and at least one second signal line which extend along a first direction and are arranged along a second direction; the first signal line comprises a first wire-avoiding segment in the wire-avoiding area, and the second signal line comprises a second wire-avoiding segment in the wire-avoiding area; wherein the orthographic projection of the first wire-avoiding segment and the second wire-avoiding segment on the substrate which transmit the stage-overlapping conduction level does not overlap, the first direction intersects with the second direction, and the polarity of the conduction level of the threshold compensation module and the data writing module is opposite. The application can improve the display uneven phenomenon of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the development of display technology, the application of array substrates is becoming more and more extensive, and correspondingly, the requirements for array substrates are becoming higher and higher.

[0003] However, display panels made from array substrates in related art are prone to display unevenness (mura), which affects display effects. Summary of the Invention

[0004] The present invention provides an array substrate and a display panel to improve the phenomenon of uneven display of the display panel.

[0005] According to one aspect of the present invention, there is provided an array substrate, comprising a winding avoidance area, a wiring area at least partially surrounding the winding avoidance area, and a winding arrangement area located between the wiring area and the winding avoidance area;

[0006] The array substrate further includes a substrate and at least one pixel driving circuit disposed on the substrate, wherein the pixel driving circuit includes a data writing module and a threshold compensation module;

[0007] The array substrate includes at least one first signal line and at least one second signal line extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line includes a first winding segment located in the winding setting area, and the second signal line includes a second winding segment located in the winding setting area;

[0008] The orthographic projections of the first winding segment and the second winding segment, whose transmission conduction level stages overlap, on the substrate do not overlap, the first direction intersects with the second direction, and the polarity of the conduction levels of the threshold compensation module and the data writing module are opposite.

[0009] Optionally, the first signal line is used to control the conduction state of the threshold compensation module, and the second signal line is used to control the conduction state of the data writing module; the stage in which the first signal line transmits the conduction level includes N1 stages, and the stage in which the second signal line transmits the conduction level includes one stage; N1 ≥ 2;

[0010] Preferably, the orthographic projections of the first winding segment and the second winding segment corresponding to the pixel driving circuits in the same row on the substrate do not overlap; the orthographic projections of the first winding segment corresponding to the pixel driving circuit in the kth row and the second winding segment corresponding to the pixel driving circuit in the k+N2th row on the substrate partially overlap; N2 ≥ N1;

[0011] Preferably, N2 is equal to N1;

[0012] Preferably, the first signal line includes a first straight line segment located in the wiring area, and the second signal line includes a second straight line segment located in the wiring area;

[0013] Preferably, the orthographic projections of the first winding segment and the second winding segment on the substrate, in which the stages of the partial transmission conduction levels do not overlap, partially overlap.

[0014] Optionally, in the winding setting area, projections of the first N2 first winding segments and any second winding segment on the substrate do not overlap;

[0015] The array substrate further includes N2 first compensation signal lines;

[0016] The N2 first compensation signal lines correspond to the first N2 first winding segments, and along the thickness direction of the array substrate, the first compensation signal lines partially overlap with the orthographic projections of the corresponding first winding segments on the substrate;

[0017] Preferably, the first compensation signal line and the second winding segment are in the same layer.

[0018] Optionally, the first compensation signal line is connected to a first fixed potential;

[0019] Preferably, the array substrate includes at least one first power signal line, the first power signal line being used to provide a first power signal to the pixel driving circuit; the N2 first compensation signal lines are connected to the first power signal line;

[0020] Preferably, the first ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line;

[0021] Preferably, the second ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line.

[0022] Optionally, the first winding segment is arranged on a side of the second winding segment away from the substrate;

[0023] The array substrate also includes at least one third signal line extending along the first direction and arranged along the second direction, the third signal line is connected to the pixel driving circuit, and the third signal line includes a third winding segment located in the winding setting area; along the thickness direction of the array substrate, the orthographic projections of the first N2 first winding segments and any of the third winding segments on the substrate do not overlap.

[0024] Optionally, in the winding arrangement area, the orthographic projections of the last N2 second winding segments and any first winding segment on the substrate do not overlap;

[0025] The array substrate further includes N2 second compensation signal lines;

[0026] The N2 second compensation signal lines correspond to the last N2 second winding segments, and along the thickness direction of the array substrate, the second compensation signal lines partially overlap with the orthographic projections of the corresponding second winding segments on the substrate;

[0027] Preferably, the second compensation signal line and the first winding segment are in the same layer.

[0028] Optionally, the N2 second compensation signal lines are connected to a first fixed potential;

[0029] Preferably, the array substrate includes at least one first power signal line, the first power signal line being used to provide a first power signal to the pixel driving circuit; the N2 second compensation signal lines are connected to one of the first power signal lines;

[0030] Preferably, the first ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line;

[0031] Preferably, the second ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line.

[0032] Optionally, the array substrate further includes at least one data line, at least one light emitting control signal line and at least one first power signal line;

[0033] The pixel driving circuit further includes a driving module, a first light emitting control module, a second light emitting control module and a first initialization module;

[0034] A first end of the data writing module is electrically connected to the data line, a second end of the data writing module is electrically connected to the first end of the driving module, and a control end of the data writing module is electrically connected to the first signal line or the second signal line;

[0035] A first end of the first light control module is electrically connected to the first power signal line, a second end of the first light control module is electrically connected to the first end of the driving module, and a control end of the first light control module is electrically connected to the light control signal line;

[0036] The first end of the threshold compensation module is electrically connected to the second end of the driving module, the second end of the threshold compensation module is electrically connected to the control end of the driving module, and the control end of the threshold compensation module is electrically connected to the first signal line or the second signal line;

[0037] The first end of the second light emitting control module is electrically connected to the second end of the driving module, the second end of the second light emitting control module is used to connect to the light emitting structure, and the control end of the second light emitting control module is electrically connected to the light emitting control signal line;

[0038] Preferably, the data writing module and the threshold compensation module have transistor types that are different;

[0039] Preferably, the pixel driving circuit also includes a storage module, a first initialization module, a second initialization module and a third initialization module; the array substrate also includes a first initialization signal line, a first scan signal line, a second initialization signal line, a third initialization signal line and a second scan signal line; the first end of the storage module is electrically connected to the first power signal line, and the second end of the storage module is electrically connected to the control end of the driving module; the first end of the first initialization module is electrically connected to the first initialization signal line, the second end of the first initialization module is electrically connected to the first end of the threshold compensation module, and the control end of the first initialization module is electrically connected to the first scan signal line; the first end of the second initialization module is electrically connected to the second initialization signal line, the second end of the second initialization module is electrically connected to the first end of the light-emitting structure, and the control end of the second initialization module is electrically connected to the second scan signal line; the first end of the third initialization module is electrically connected to the third initialization signal line, the second end of the third initialization module is electrically connected to the second end of the driving module, and the control end of the third initialization module is electrically connected to the second scan signal line.

[0040] Optionally, the array substrate includes a driving circuit layer provided on the substrate, the driving circuit layer including an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence; wherein the active structure of the data writing module is provided in the active layer, the gate of the data writing module is provided in the first conductive layer, and the source and drain of the data writing module are provided in the fourth conductive layer; the gate of the threshold compensation module is provided in the third conductive layer, and the source and drain of the threshold compensation module are provided in the fourth conductive layer;

[0041] Preferably, the first signal line is provided in the third conductive layer, and the second signal line is provided in the first conductive layer.

[0042] According to another aspect of the present invention, a display panel is provided, comprising the array substrate as described above.

[0043] The technical solution of an embodiment of the present invention comprises an array substrate including a winding avoidance area, a wiring area at least partially surrounding the winding avoidance area, and a winding setting area located between the wiring area and the winding avoidance area; the array substrate also includes a substrate and at least one pixel driving circuit disposed on the substrate, the pixel driving circuit including a data writing module and a threshold compensation module; the array substrate includes at least one first signal line and at least one second signal line extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line includes a first winding segment located in the winding setting area, and the second signal line includes a second winding segment located in the winding setting area; wherein the orthographic projections of the first winding segment and the second winding segment whose stages of transmitting conduction levels overlap on the substrate do not overlap; and the orthographic projections of the first winding segment and the corresponding second winding segment whose stages of transmitting conduction levels do not overlap on the substrate partially overlap on the substrate; wherein the first direction intersects the second direction, and the conduction levels of the threshold compensation module and the data writing module have opposite polarities. By setting the first winding segment and the second winding segment of the pixel driving circuit that overlap in the corresponding conduction level stages to not overlap, when one of the overlapping first winding segment and the second winding segment is at the conduction level, the other is at the off level, that is, the polarity of the two is the same, thereby avoiding the reduction of signal quality due to coupling of different polarities, and further avoiding the display unevenness problem caused by the decrease in charging rate.

[0044] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention;

[0047] Figure 2 for Figure 1 A partial enlarged view of

[0048] Figure 3 A schematic diagram of the circuit structure of a pixel driving circuit provided by an embodiment of the present invention;

[0049] Figure 4 for Figure 3 Corresponding timing diagram;

[0050] Figure 5 for Figure 1 Cross-section of the middle wiring area;

[0051] Figure 6 for Figure 2 Cross-section along direction A1A2;

[0052] Figure 7 for Figure 2 Cross-section along the A3A4 direction;

[0053] Figure 8 for Figure 2 Cross-section along the A5A6 direction;

[0054] Figure 9 for Figure 2 Cross-section along A7A8;

[0055] Figure 10 for Figure 2 Another cross-sectional view along the A1A2 direction;

[0056] Figure 11 is a circuit connection diagram of the first compensation signal line;

[0057] Figure 12 for Figure 2 Another cross-section along the A7A8 direction;

[0058] Figure 13 is a circuit connection diagram of the second compensation signal line;

[0059] Figure 14 A schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0060] Figure 15 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] Just as display panels in related technologies suffer from uneven display, the inventors, after extensive research, discovered that the cause of this technical problem is that when a display panel has a hole-punch area, the signal lines in the display panel need to bypass the hole-punch area, resulting in a relatively dense signal line density near the hole-punch area. Some signal lines overlap, causing signal coupling. This in turn affects the driving of the pixel driver circuit, resulting in mura.

[0064] In view of the above technical problems, the present invention proposes the following solutions:

[0065] Figure 1 A schematic structural diagram of an array substrate provided by an embodiment of the present invention is shown. Figure 2 for Figure 1 For a partial enlarged view, refer to Figure 1 and Figure 2In this embodiment, the array substrate includes a winding avoidance area HO, a wiring area AA1 surrounding the winding avoidance area HO, and a winding setting area AA2 located between the wiring area AA1 and the winding avoidance area HO; the array substrate also includes a substrate and a plurality of pixel driving circuits provided on the substrate, the pixel driving circuit including a data writing module and a threshold compensation module; the array substrate includes a plurality of first signal lines SN2 and a plurality of second signal lines SP1 extending along a first direction X and arranged along a second direction Y; one of the first signal line SN2 and the second signal line SP1 is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line SN2 includes The embodiment includes a first winding segment SN2a located in the winding setting area AA2, and the second signal line SP1 includes a second winding segment SP1a located in the winding setting area AA2; wherein, the orthographic projections of the first winding segment SN2a and the second winding segment SP1a, whose stages of transmission conduction levels overlap, on the substrate do not overlap; the orthographic projections of the first winding segment SN2a and the second winding segment SP1a, whose stages of transmission conduction levels do not overlap, on the substrate partially overlap; wherein, the first direction X intersects with the second direction Y, and the polarities of the conduction levels of the threshold compensation module and the data writing module are opposite. It should be noted that the overlapping of the transmission conduction level stages recorded in this application can be understood as the overlapping of the signals during the transmission conduction level.

[0066] Specifically, the array substrate can be used to form a display panel after the light-emitting structure is evaporated and the encapsulation layer is formed. The winding avoidance area HO of the array substrate is not used to set various signal lines (such as scan lines, data lines, power lines, etc.) for driving pixel circuits. The winding avoidance area HO has a high light transmittance and can be used to set optical devices such as image acquisition and case or infrared sensor elements. Exemplarily, the winding avoidance area HO can be a hole area; the winding avoidance area HO can also be used to set part of the light-emitting structure so that the display panel can achieve a full-screen display effect. The shape of the winding avoidance area HO can be circular, square, triangular or other polygonal. The winding avoidance area HO can be located at the top or bottom of the array substrate. The wiring area AA1 of the array substrate can be understood as the main display area. Multiple pixel driving circuits and multiple signal lines are set in the wiring area AA1. The signal lines are used to drive the pixel driving circuits. The signal lines include scan lines, data lines, and power lines, among which the scan lines include first signal lines SN2 and second signal lines SP1. In this embodiment, the first signal line SN2 and the second signal line SP1 refer to scan lines whose extension direction intersects the winding avoidance area HO. It will be understood that, for ease of explanation, scan lines in the array substrate whose extension direction does not intersect the winding avoidance area HO are not defined as first signal lines SN2 or second signal lines SP1, and that multiple scan lines with the same function as the first signal line SN2 or second signal line SP1 exist. In this embodiment, the first direction X is, for example, the row direction, and the second direction Y is, for example, the column direction. Each first signal line SN2 is connected to a row of pixel driver circuits, and each second signal line SP1 is connected to a row of pixel driver circuits. Each row of pixel driver circuits is also connected to a corresponding first signal line SN2 and second signal line SP1. The first signal line SN2 bypasses the winding avoidance area HO via a first winding segment SN2a located in the winding arrangement area AA2, and the second signal line SP1 bypasses the winding avoidance area HO via a second winding segment SP1a located in the winding arrangement area AA1. The shape of the winding segment can be a broken line; or it can follow the shape of the winding avoidance area HO, that is, when the shape of the winding avoidance area HO is circular, the shape of the winding segment is an arc. It is understandable that the winding arrangement area AA2 can also be provided with a pixel driving circuit and / or a light-emitting structure.

[0067] The data writing module in the pixel driving circuit is used to write the data voltage into the driving module in the pixel driving circuit, and the threshold compensation module is used to compensate for the threshold voltage of the driving module. During the charging phase of the pixel driving circuit, the data writing module and the threshold compensation module need to be turned on at the same time to complete the writing of the data voltage and the compensation of the threshold voltage. The polarity of the on-level of the data writing module and the threshold compensation module is opposite, that is, if the on-level of the data writing module is low, the on-level of the threshold compensation module is high; at the same time, the polarity of the off-level of the data writing module and the threshold compensation module is also opposite, that is, if the off-level of the data writing module is high, the off-level of the threshold compensation module is low.

[0068] There are a large number of signal lines in the winding setting area AA2. In order to reduce the area of ​​the winding setting area AA2, the signal lines can be overlapped, that is, the orthographic projections of the signal lines on the substrate are overlapped. It can be understood that the overlap of two signal lines will form a coupling capacitor, and the closer to the winding avoidance area, the larger the coupling capacitor. For the pixel driving circuit driven simultaneously, if the corresponding first winding segment SN2a overlaps with the corresponding second winding segment SP1a, then when the pixel driving circuit is driven, the first winding segment SN2a and the second winding segment SP1a are both at the on-level, and the polarities of the two on-levels are opposite. The mutual coupling through the coupling capacitor will affect the quality of the on-signal, thereby affecting the on-state of the corresponding module, making the data voltage charging rate lower than the data voltage charging rate corresponding to the normal scanning line, and ultimately causing uneven display, resulting in poor display effect. In this embodiment, the first winding segment SN2a and the second winding segment SP1a, which overlap in the stages of transmitting the on-level, do not overlap. Then, when one of the signal lines is at the on-level, the other signal line is at the off-level. Since the polarities of the on-levels of the data writing module and the threshold compensation module are opposite, the on-level of one of them is the same as the off-level polarity of the other. That is to say, the polarity of the levels on the overlapping first signal line SN2a and the second signal line SP1a is the same, both are high levels or both are low levels, thus avoiding the problem of signal quality degradation caused by mutual coupling and improving the display unevenness phenomenon.

[0069] In addition, since the positive projections of the first winding segment SN2a and the corresponding second winding segment SP1a on the substrate do not overlap in the stages of some transmission conduction levels, the area of ​​the winding setting area AA2 can be greatly reduced, so that the array substrate can achieve a higher pixel density.

[0070] The technical solution of this embodiment adopts an array substrate including a winding avoidance area, a wiring area surrounding the winding avoidance area, and a winding setting area located between the wiring area and the winding avoidance area; the array substrate also includes a substrate and a plurality of pixel driving circuits arranged on the substrate, the pixel driving circuits including a data writing module and a threshold compensation module; the array substrate includes a plurality of first signal lines and a plurality of second signal lines extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line includes a first winding segment located in the winding setting area, and the second signal line includes a second winding segment located in the winding setting area; wherein the orthographic projections of the first winding segment and the second winding segment whose transmission conduction level stages overlap on the substrate do not overlap; and the orthographic projections of the first winding segment and the corresponding second winding segment whose transmission conduction level stages do not overlap on the substrate partially overlap on the substrate; wherein the first direction intersects the second direction, and the conduction level polarities of the threshold compensation module and the data writing module are opposite. By setting the first winding segment and the second winding segment of the pixel driving circuit that overlap in the corresponding conduction level stages to not overlap, when one of the overlapping first winding segment and the second winding segment is at the conduction level, the other is at the off level, that is, the polarity of the two is the same, thereby avoiding the reduction of signal quality due to coupling of different polarities, and further avoiding the display unevenness problem caused by the decrease in charging rate.

[0071] The above is the core idea of ​​the present invention. To facilitate the subsequent description, the structure of the pixel driving circuit and the film layer structure of the array substrate are briefly described below. Figure 3 and Figure 4 As shown, Figure 3 A schematic diagram of the circuit structure of a pixel driving circuit provided by an embodiment of the present invention is shown. Figure 4 for Figure 3 The corresponding timing diagram is: Figure 5 for Figure 1 Cross-sectional view of the wiring area, refer to Figures 3 to 5The pixel driving circuit includes a driving module 801, a data writing module 802, a threshold compensation module 803, a first initialization module 804, a first light-emitting control module 805, a second light-emitting control module 806, a second initialization module 807, a third initialization module 808 and a storage module 809; a first end of the data writing module 802 is electrically connected to the data line Data, a second end of the data writing module 802 is electrically connected to the first end of the driving module 801, and a control end of the data writing module 802 is electrically connected to the first signal line SN2 or the second signal line SP1. In this embodiment, the second signal line SP1 is used to control the data writing module, and the first signal line SN2 is used to control the data writing module. Taking the control threshold compensation module as an example, the control end of the data writing module 802 is electrically connected to the second signal line SP2; the first end of the first light-emitting control module 805 is electrically connected to the first power signal line ELVDD, the second end of the first light-emitting control module 805 is electrically connected to the first end of the driving module 801, and the control end of the first light-emitting control module 805 is electrically connected to the light-emitting control signal line EM; the first end of the threshold compensation module 803 is electrically connected to the second end of the driving module 801, the second end of the threshold compensation module 803 is electrically connected to the control end of the driving module 801, and the control end of the threshold compensation module 803 is electrically connected to the first signal line SN2; the second light-emitting control module 805 is electrically connected to the first power signal line ELVDD, the second end of the first light-emitting control module 805 is electrically connected to the first end of the driving module 801, and the control end of the threshold compensation module 803 is electrically connected to the first signal line SN2; The first end of the control module 806 is electrically connected to the second end of the driving module 801, the second end of the second light-emitting control module 806 is used to connect to the light-emitting structure 810, and the control end of the second light-emitting control module 806 is electrically connected to the light-emitting control signal line EM; the first end of the storage module 809 is electrically connected to the first power signal line ELVDD, and the second end of the storage module 809 is electrically connected to the control end of the driving module 801; the first end of the first initialization module 804 is electrically connected to the first initialization signal line Vrefn1, the second end of the first initialization module 804 is electrically connected to the first end of the threshold compensation module 803, and the control end of the first initialization module 804 is electrically connected to the first scanning signal line Vrefn1. The signal line SN1 is electrically connected; the first end of the second initialization module 807 is electrically connected to the second initialization signal line Vrefn2, the second end of the second initialization module 807 is electrically connected to the first end of the light-emitting structure 810, and the control end of the second initialization module 807 is electrically connected to the second scanning signal line SP2; the first end of the third initialization module 808 is electrically connected to the third initialization signal line Vrefp, the second end of the third initialization module 808 is electrically connected to the second end of the driving module 801, the control end of the third initialization module 808 is electrically connected to the second scanning signal line SP2, and the second end of the light-emitting structure 810 is electrically connected to the second power supply signal line ELVSS.

[0072] The operation process of the pixel driving circuit may include an initialization phase t1 , a charging phase t2 and a light emitting phase t3 .

[0073] During initialization phase t1, the first scanning signal line SN1 controls the first initialization module 804 to turn on, the first signal line SN2 controls the threshold compensation module 803 to turn on, and the initialization signal on the first initialization signal line Vrefn1 initializes the control terminal of the driving module 801. The second scanning signal line SP2 controls the second initialization module 807 and the third initialization module 808 to turn on, the second initialization signal line Vrefn2 initializes the light-emitting structure, and the third initialization signal line Vrefp initializes the second terminal of the driving module 801.

[0074] During charging phase t2, the second signal line SP2 controls the data writing module 802 to be turned on, and the first signal line SN2 controls the threshold compensation module 803 to be turned on. The data voltage on the data line Data passes through the data writing module 802, the driver module 801, and the threshold compensation module 803, and is written to the control terminal of the driver module 801. When the potential difference between the first terminal and the control terminal of the driver module 801 reaches the threshold voltage of the driver module 801, the driver module 801 is turned off. At this phase, the threshold compensation process of the driver module 801 is completed.

[0075] During light-emitting phase t3, the light-emitting control signal line EM turns on the first light-emitting control module 804 and the second light-emitting control module 805. The driver module 801 generates a driving current, and the storage module 809 maintains the potential at the control terminal of the driver module 801. The driving current is transmitted to the light-emitting structure 810, which then emits light in response to the driving current. Optionally, during light-emitting phase t3, the second scanning signal line SP2 and the light-emitting control signal line EM have opposite polarities and are periodically turned on, causing the light-emitting structure to periodically initialize and emit light, further enhancing the display effect.

[0076] From the above analysis, we can see that the conduction level transmission phases on the first signal line SN2 are initialization phase t1 and charging phase t2. Due to the row scanning drive mode, the initialization phase t1 of the current row is the charging phase t2 of the previous row. Therefore, in this embodiment, the conduction level of the first signal line SN2 not only overlaps with the conduction level of the second signal line SP1 corresponding to the current row, but also overlaps with the conduction level of the second signal line SP1 of the previous row.

[0077] Exemplarily, the driving module 801 includes a first transistor T1 , a first end of the first transistor T1 serving as the first end of the driving module 801 , a second end of the first transistor T1 serving as the second end of the driving module 801 , and a control end of the first transistor T1 serving as the control end of the driving module 801 .

[0078] The data writing module 802 includes a second transistor T2 , a first end of the second transistor T2 serving as the first end of the data writing module 802 , a second end of the second transistor T2 serving as the second end of the data writing module 802 , and a control end of the second transistor T2 serving as the control end of the data writing module 802 .

[0079] The threshold compensation module 803 includes a third transistor T3 , a first end of the third transistor T3 serving as the first end of the threshold compensation module 803 , a second end of the third transistor T3 serving as the second end of the threshold compensation module 803 , and a control end of the third transistor T3 serving as the control end of the threshold compensation module 803 .

[0080] The first initialization module 804 includes a fourth transistor T4 , a first end of the fourth transistor T4 serving as the first end of the first initialization module 804 , a second end of the fourth transistor T4 serving as the second end of the first initialization module 804 , and a control end of the fourth transistor T4 serving as the control end of the first initialization module 804 .

[0081] The first light-emitting control module 805 includes a fifth transistor T5, the first end of the fifth transistor T5 serves as the first end of the first light-emitting control module 805, the second end of the fifth transistor T5 serves as the second end of the first light-emitting control module 805, and the control end of the fifth transistor T5 serves as the control end of the first light-emitting control module 805.

[0082] The second light emitting control module 806 includes a sixth transistor T6, a first end of the sixth transistor T6 serves as the first end of the second light emitting control module 806, a second end of the sixth transistor T6 serves as the second end of the second light emitting control module 806, and a control end of the sixth transistor T6 serves as the control end of the second light emitting control module 806.

[0083] The second initialization module 807 includes a seventh transistor T7, a first end of the seventh transistor T7 serving as the first end of the second initialization module 807, a second end of the seventh transistor T7 serving as the second end of the second initialization module 807, and a control end of the seventh transistor T7 serving as the control end of the second initialization module 807.

[0084] The third initialization module 808 includes an eighth transistor T8, a first end of the eighth transistor T8 serves as the first end of the third initialization module 808, a second end of the eighth transistor T8 serves as the second end of the third initialization module 808, and a control end of the eighth transistor T8 serves as the control end of the third initialization module 808.

[0085] The storage module 809 includes a storage capacitor Cst, a first end of the storage capacitor Cst serves as a first end of the storage module 809 , and a second end of the storage capacitor Cst serves as a second end of the storage module 809 .

[0086] Among the above transistors, the transistor type of the third transistor T3 is different from the transistor type of the second transistor T2. Furthermore, the third transistor T3 and the fourth transistor T4 can be N-type transistors, such as indium gallium zinc oxide transistors; and the remaining transistors can be P-type transistors, such as polysilicon or single crystal silicon transistors.

[0087] like Figure 5 As shown, the array substrate includes a substrate Sub, a driving circuit layer, and a pixel definition layer PDL stacked in sequence. A first buffer layer Buf1 may also be provided between the substrate Sub and the driving circuit layer. The driving circuit layer specifically includes an active layer Act, a first conductive layer M1, a second conductive layer M2, an indium gallium zinc oxide layer IGZO, a third conductive layer GATO, a fourth conductive layer M3, and a fifth conductive layer M4 stacked in sequence. The active layer Act is used to set the active structure of the P-type transistor, the first conductive layer M1 is used to set the gate of the P-type transistor and the second end of the storage capacitor; the second conductive layer M2 is used to set the first end of the storage capacitor; the indium gallium zinc oxide layer IGZO is used to set the active structure of the N-type transistor; the third conductive layer GATO is used to set the gate of the N-type transistor; the fourth conductive layer M3 is used to set the source and drain of each transistor; and the fifth conductive layer M4 can be used to set the data line, etc. A first gate insulating layer GI1 is also provided between the active layer Act and the first conductive layer M1. An interlayer insulating layer CI is provided between the first conductive layer M1 and the second conductive layer M2. A second buffer layer Buf2 is provided between the second conductive layer M2 and the indium gallium zinc oxide layer IGZO. A second gate insulating layer GI2 is provided between the indium gallium zinc oxide layer IGZO and the third conductive layer GATO. An inorganic layer ILD is provided between the third conductive layer GATO and the fourth conductive layer M3. A first planarization layer PLN1 is provided between the fourth conductive layer M3 and the fifth conductive layer M4. A second planarization layer PLN2 is provided between the fifth conductive layer M4 and the pixel defining layer PDL. The pixel defining layer PDL defines multiple openings, and light-emitting structures are provided within the openings. The light-emitting structures are connected to the pixel driving circuit via corresponding anodes Ano.

[0088] Optionally, the first signal line SN2 is used to control the conduction state of the threshold compensation module, and the second signal line is used to control the conduction state of the data writing module; the stage in which the first signal line SN2 transmits the conduction level includes N1 stages, and the stage in which the second signal line SP1 transmits the conduction level includes one stage; N1≥2.

[0089] Specifically, the phases described in this embodiment include an initialization phase, a charging phase, and a light-emitting phase. When the threshold compensation module is only on during the charging phase, N1 is equal to 2; when the threshold compensation module is on during both the charging and initialization phases, N1 is greater than 2. The data writing module is only on during the charging phase.

[0090] Optionally, Figure 6 for Figure 2 Cross-section along the A1A2 direction, Figure 7 for Figure 2 Cross-section along the A3A4 direction, Figure 8 for Figure 2 Cross-section along the A5A6 direction, Figure 9 for Figure 2 Cross-section along the A7A8 direction, combined with Figure 2 , Figures 6 to 9 The orthographic projections of the first winding segment SN2a and the corresponding second winding segment SP1a corresponding to the pixel driving circuits in the same row on the substrate Sub do not overlap; the orthographic projections of the first winding segment SN2a corresponding to the pixel driving circuit in the k-th row and the second winding segment SP1a corresponding to the pixel driving circuit in the k+N2-th row on the substrate Sub partially overlap; N2 ≥ N1. It should be noted that k here can be a positive integer greater than or equal to 1.

[0091] Specifically, in this embodiment, taking N1 as 2 as an example, the pixel driving circuit performs row scanning drive sequentially from the first row to the last row. At this time, the stage in which the first signal line SN2 transmits a conduction level overlaps not only with the stage in which the second signal line SP1 corresponding to the row transmits a conduction level, but also with the stage in which the second signal line SP1 in the previous row transmits a conduction level. The stage in which the first signal line SN2 in the kth row transmits a conduction level does not overlap with the stage in which the second signal line SP1 in the k+N1th row and above transmits a conduction level. Therefore, this embodiment prevents overlapping first signal lines SN2 and second signal lines SP1 from transmitting a conduction level simultaneously, thereby improving display unevenness.

[0092] The arrangement of this embodiment, relative to the overlapping arrangement of the first signal line SN2 and the second signal line SP1 corresponding to the same row of pixel driving circuits, can be understood as moving the first signal line SN2 forward as a whole by N2 rows.

[0093] Optionally, N2 is equal to N1. This configuration reduces the overall forward movement distance of the first signal line SN2, which facilitates wiring without increasing the area of ​​the winding arrangement area AA2 too much.

[0094] Alternatively, as Figure 1 As shown, the portion of the first signal line SN2 located in the wiring area AA1 can be understood as a first straight line segment, and the portion of the second signal line SP1 located in the wiring area AA1 can be understood as a second straight line segment.

[0095] It should be noted that Figure 6 In the example, the first winding segment SN2a and the first second winding segment SP1a are numbered M, and Figures 6 to 9Although the signal lines are numbered in ascending order (i.e. SN2a(M)-SN2a(M+9), SP1a(M)-SP1a(M+9)), Figure 6 and Figure 7 、 Figure 8 and Figure 9 Corresponding to Figure 2 A plurality of first signal lines and second signal lines are also arranged between the positions.

[0096] Optionally, in the above embodiment, the first winding segment SN2a is disposed in the third conductive layer GATO, and the second winding segment SP1a is disposed in the first conductive layer M1. The first scan signal line SN1 can be disposed in the second conductive layer M2, and the emission control signal line EM and the second scan signal line SP2 can be disposed in the fourth conductive layer M3. The emission control signal lines EM and the second scan signal lines SP2 can be arranged alternately.

[0097] Depend on Figure 6 and Figure 9 As can be seen, in this embodiment, the first winding segment SN2a is shifted forward two rows. The first first winding segment SN2a(M) and the second first winding segment SN2a(M+1) do not overlap with any second winding segment SP1. However, the remaining first winding segments SN2a overlap with one second winding segment SP1a, resulting in overlapping capacitance. During display, the first first winding segment SN2a(M) and the second first winding segment SN2a(M+1) experience missing overlapping capacitance, affecting display uniformity. Similarly, the remaining N2 second winding segments SP1a also experience missing overlapping capacitance, affecting display uniformity.

[0098] Therefore, optionally, Figure 10 for Figure 2 Another cross-sectional view along the A1A2 direction, refer to Figure 2 and Figure 10 In the winding arrangement area, the projections of the first N2 first winding segments SN2a and any second winding segment SP1a on the substrate Sub do not overlap. The array substrate further includes N2 first compensation signal lines Comp1. The N2 first compensation signal lines Comp1 correspond one-to-one with the first N2 first winding segments, and along the thickness direction of the array substrate, the orthographic projections of the first compensation signal lines Comp1 and the corresponding first winding segments SN2a on the substrate Sub partially overlap.

[0099] Specifically, the first compensation signal line Comp1 is used to form an overlapping capacitor with the corresponding first winding segment SN2a to compensate for the lack of overlapping capacitors. Each first winding segment SN2a forms an overlapping capacitor with a signal line (the first compensation signal line Comp1 or the second winding segment SP1a). During display, the display is affected by the overlapping capacitor, thereby improving display uniformity. Of course, it will be understood that the overlapping capacitors formed in this embodiment do not reduce the charging rate.

[0100] Optionally, the first compensation signal line Comp1 and the second winding segment SP1a are placed on the same layer. This arrangement allows the distances between the first compensation signal line Comp1 and the corresponding first winding segment SN1a, and between the second winding segment SP1a and the first winding segment SN1a, to be close, resulting in similar overlap capacitances. This in turn allows for similar effects on the display, further improving display uniformity.

[0101] Optionally, the first compensation signal line Comp1 is connected to a fixed potential, which can avoid the problem of potential instability caused by the first compensation signal line Comp1 being suspended, and can also prevent the first compensation signal line Comp1 from forming an antenna structure and affecting signal transmission on the corresponding first winding segment SN2a.

[0102] Optionally, the array substrate includes a plurality of first power signal lines, the first power signal lines are used to provide a first power signal for the pixel driving circuit, and N2 first compensation signal lines are connected to one first power signal line.

[0103] Specifically, the first power signal line, ie Figure 3 The first power signal line ELVDD is shown in FIG. By connecting the first power signal line to the first compensation signal line, a fixed first power signal can be connected to the first compensation signal line Comp1. Of course, in other embodiments, the first compensation signal line Comp1 can also be connected to an initialization signal line or a second power signal line. It should be noted that since the first compensation signal line Comp1 is connected to a fixed potential, the potential does not fluctuate. Even if the connected potential has the opposite polarity to the conduction level on the first signal line, the impact on the signal on the first signal line is minimal.

[0104] Alternatively, as Figure 11 As shown, Figure 11 This is the circuit connection diagram of the first compensation signal line, refer to Figure 11The first ends of N2 first compensation signal lines Comp1 are connected in series and then connected to the first power signal line ELVDD. The second ends of N2 first compensation signal lines Comp1 are connected in series and then connected to the first power signal line ELVDD. In this embodiment, the first ends of all first compensation signal lines are connected in series, and the second ends of all first compensation signal lines are connected in series and then respectively connected to the first power signal line ELVDD. This can reduce the signal voltage drop on the first compensation signal line Comp1 and simplify the connection between the first compensation signal line Comp1 and the first power signal line ELVDD.

[0105] Optionally, the first winding segment SN2a is arranged on the side of the second winding segment SP1a away from the substrate; the array substrate also includes a plurality of third signal lines extending along the first direction X and arranged along the second direction Y, the third signal line is connected to the pixel driving circuit, and the third signal line includes a third winding segment located in the winding setting area AA2; along the thickness direction of the array substrate, the first N2 first winding segments SN2a do not overlap with the orthographic projection of any third winding segment on the substrate.

[0106] Specifically, the third signal lines described in this embodiment include a first scanning signal line SN1, a second scanning signal line SP2, and a light-emission control signal line EM. The first N2 first winding segments do not overlap with any third winding segments. In other words, the first signal line SN2 of this embodiment is shifted N2 rows forward relative to the pixel driving circuit in the corresponding row.

[0107] Optionally, Figure 12 for Figure 2 Another cross-sectional view along the A7A8 direction, refer to Figure 2 and Figure 11 In the winding arrangement area, the projections of the last N2 second winding segments SP1a and any first winding segment SN2a on the substrate Sub do not overlap. The array substrate further includes N2 second compensation signal lines Comp2. The N2 second compensation signal lines Comp2 correspond one-to-one to the last N2 second winding segments, and along the thickness direction of the array substrate, the second compensation signal lines Comp2 partially overlap with the orthographic projections of the corresponding second winding segments SP1a on the substrate Sub.

[0108] Specifically, the second compensation signal line Comp2 is used to form an overlap capacitor with the corresponding second winding segment SP1a to compensate for the lack of overlap capacitors. Each second winding segment SP1a forms an overlap capacitor with a signal line (the second compensation signal line Comp2 or the first winding segment SN2a). During display, all signals are affected by the overlap capacitor, resulting in better display uniformity. It should be understood that the overlap capacitors formed in this embodiment do not reduce the charging rate.

[0109] Optionally, the second compensation signal line Comp2 and the first winding segment SN2a are placed on the same layer. This arrangement allows the distances between the second compensation signal line Comp2 and the corresponding second winding segment SP1a, and between the second winding segment SP1a and the first winding segment SN1a, to be close, resulting in similar overlap capacitances. This in turn allows for similar effects on the display, further improving display uniformity.

[0110] Optionally, the second compensation signal line Comp2 is connected to a fixed potential, which can avoid the problem of potential instability caused by the second compensation signal line Comp2 being suspended in the air, and can also prevent the second compensation signal line Comp2 from forming an antenna structure and affecting signal transmission on the corresponding second winding segment SP1a.

[0111] Optionally, the array substrate includes a plurality of first power signal lines, the first power signal lines are used to provide a first power signal for the pixel driving circuit, and N2 second compensation signal lines are connected to one first power signal line.

[0112] Specifically, the first power signal line, ie Figure 3 The first power signal line ELVDD is shown in FIG. By connecting the first power signal line to the second compensation signal line, a fixed first power signal can be connected to the second compensation signal line Comp2. Of course, in other embodiments, the second compensation signal line Comp2 can also be connected to an initialization signal line or a second power signal line. It should be noted that since the second compensation signal line Comp2 is connected to a fixed potential, the potential does not fluctuate. Even if the connected potential has the opposite polarity to the conduction level on the first signal line, the impact on the signal on the first signal line is minimal.

[0113] Alternatively, as Figure 13 As shown, Figure 13 This is the circuit connection diagram of the second compensation signal line, refer to Figure 11 The first ends of N2 second compensation signal lines Comp2 are connected in series and then connected to the first power signal line ELVDD. The second ends of N2 second compensation signal lines Comp2 are connected in series and then connected to the first power signal line ELVDD. In this embodiment, the first ends of all second compensation signal lines are connected in series, and the second ends of all second compensation signal lines are connected in series and then respectively connected to the first power signal line ELVDD. This can reduce the signal voltage drop on the second compensation signal lines Comp2 and simplify the connection between the second compensation signal lines Comp2 and the first power signal line ELVDD.

[0114] Optionally, in the above embodiment, although the first winding segment SN2a is entirely moved forward by two rows as an example, in other embodiments, the second winding segment SP1a may be moved backward by two rows. Alternatively, the first winding segment SN2a may be moved backward by at least one row, or the second winding segment SP1a may be moved forward by at least one row, so as to achieve the effect that the orthographic projections of the first and second winding segments, whose transmission conduction level stages overlap, on the substrate do not overlap.

[0115] The embodiment of the present invention further provides a display panel, such as Figure 14 As shown, Figure 14 This is a schematic structural diagram of a display panel provided in an embodiment of the present invention. The display panel includes an array substrate provided in any embodiment of the present invention, and further includes a light-emitting structure. Because the display panel provided in an embodiment of the present invention includes the array substrate provided in an embodiment of the present invention, it also has the same beneficial effects, and therefore will not be further described here.

[0116] The embodiment of the present invention further provides a display device, such as Figure 15 As shown, Figure 15 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device includes the display panel provided in any embodiment of the present invention. The display device can be a mobile phone, tablet computer, MP3 player, MP4 player, smart watch, smart helmet, or other wearable device. Since the display device provided in an embodiment of the present invention includes the display panel provided in an embodiment of the present invention, it also has the same beneficial effects and will not be described in detail here.

[0117] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0118] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. An array substrate, characterized in that: The array substrate comprises a winding avoidance area, a wiring area at least partially surrounding the winding avoidance area, and a winding arrangement area located between the wiring area and the winding avoidance area; The array substrate further includes a substrate and at least one pixel driving circuit disposed on the substrate, wherein the pixel driving circuit includes a data writing module and a threshold compensation module; The array substrate includes at least one first signal line and at least one second signal line extending along a first direction and arranged along a second direction; one of the first signal line and the second signal line is used to control the conduction state of the data writing module of the pixel driving circuit, and the other is used to control the conduction state of the threshold compensation module of the pixel driving circuit; the first signal line includes a first winding segment located in the winding setting area, and the second signal line includes a second winding segment located in the winding setting area; wherein the orthographic projections of the first winding segment and the second winding segment, whose transmission conduction level stages overlap, on the substrate do not overlap; wherein the first direction intersects the second direction, and the polarities of the conduction levels of the threshold compensation module and the data writing module are opposite; The first signal line is used to control the conduction state of the threshold compensation module, and the second signal line is used to control the conduction state of the data writing module; the stage in which the first signal line transmits the conduction level includes N1 stages, and the stage in which the second signal line transmits the conduction level includes one stage; N1≥2; the orthographic projections of the first winding segment and the corresponding second winding segment corresponding to the pixel driving circuits in the same row on the substrate do not overlap; the orthographic projections of the first winding segment corresponding to the pixel driving circuit in the kth row and the second winding segment corresponding to the pixel driving circuit in the k+N2th row on the substrate partially overlap; k, N1 and N2 are all positive integers, and N2≥N1.

2. The array substrate according to claim 1, wherein: The first signal line includes a first straight line segment located in the wiring area, and the second signal line includes a second straight line segment located in the wiring area.

3. The array substrate according to claim 1, wherein: The orthographic projections of the first winding segment and the second winding segment on the substrate, in which the phases of the partial transmission conduction levels do not overlap, partially overlap.

4. The array substrate according to claim 1, wherein: In the winding arrangement area, projections of the first N2 first winding segments and any second winding segment on the substrate do not overlap; The array substrate further includes N2 first compensation signal lines; The N2 first compensation signal lines correspond to the first N2 first winding segments, and along the thickness direction of the array substrate, the first compensation signal lines partially overlap with the orthographic projections of the corresponding first winding segments on the substrate.

5. The array substrate according to claim 4, wherein: The first compensation signal line and the second winding segment are in the same layer.

6. The array substrate according to claim 4, wherein: The first compensation signal line is connected to a first fixed potential.

7. The array substrate according to claim 6, wherein: The array substrate includes at least one first power signal line, and the first power signal line is used to provide a first power signal for the pixel driving circuit; the N2 first compensation signal lines are connected to one of the first power signal lines.

8. The array substrate according to claim 7, wherein: The first ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line.

9. The array substrate according to claim 7, wherein: The second ends of the N2 first compensation signal lines are connected in series and then connected to the first power signal line.

10. The array substrate according to claim 4, wherein: The first winding segment is arranged on a side of the second winding segment away from the substrate; The array substrate also includes at least one third signal line extending along the first direction and arranged along the second direction, the third signal line is connected to the pixel driving circuit, and the third signal line includes a third winding segment located in the winding setting area; along the thickness direction of the array substrate, the orthographic projections of the first N2 first winding segments and any of the third winding segments on the substrate do not overlap.

11. The array substrate according to claim 1, wherein: In the winding arrangement area, the orthographic projections of the last N2 second winding segments and any first winding segment on the substrate do not overlap; The array substrate further includes N2 second compensation signal lines; The N2 second compensation signal lines correspond to the next N2 second winding segments, and along the thickness direction of the array substrate, the second compensation signal lines partially overlap with the orthographic projections of the corresponding second winding segments on the substrate.

12. The array substrate according to claim 11, wherein: The second compensation signal line is on the same layer as the first winding segment.

13. The array substrate according to claim 11, wherein: The N2 second compensation signal lines are connected to a first fixed potential.

14. The array substrate according to claim 13, wherein: The array substrate includes at least one first power signal line, and the first power signal line is used to provide a first power signal for the pixel driving circuit; the N2 second compensation signal lines are connected to one of the first power signal lines.

15. The array substrate according to claim 14, wherein: The first ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line.

16. The array substrate according to claim 14, wherein: The second ends of the N2 second compensation signal lines are connected in series and then connected to the first power signal line.

17. The array substrate according to claim 1, wherein: The array substrate further comprises at least one data line, at least one light emitting control signal line and at least one first power signal line; The pixel driving circuit further includes a driving module, a first light emitting control module, a second light emitting control module and a first initialization module; The first end of the data writing module is electrically connected to the data line, the second end of the data writing module is electrically connected to the first end of the driving module, and the control end of the data writing module is electrically connected to the first signal line or the second signal line; A first end of the first light control module is electrically connected to the first power signal line, a second end of the first light control module is electrically connected to the first end of the driving module, and a control end of the first light control module is electrically connected to the light control signal line; The first end of the threshold compensation module is electrically connected to the second end of the driving module, the second end of the threshold compensation module is electrically connected to the control end of the driving module, and the control end of the threshold compensation module is electrically connected to the first signal line or the second signal line; The first end of the second light emitting control module is electrically connected to the second end of the driving module, the second end of the second light emitting control module is used to connect to the light emitting structure, and the control end of the second light emitting control module is electrically connected to the light emitting control signal line.

18. The array substrate according to claim 17, wherein: The data writing module and the threshold compensation module have transistors of different types.

19. The array substrate according to claim 17, wherein: The pixel driving circuit also includes a storage module, a first initialization module, a second initialization module and a third initialization module; the array substrate also includes a first initialization signal line, a first scan signal line, a second initialization signal line, a third initialization signal line and a second scan signal line; the first end of the storage module is electrically connected to the first power signal line, and the second end of the storage module is electrically connected to the control end of the driving module; the first end of the first initialization module is electrically connected to the first initialization signal line, the second end of the first initialization module is electrically connected to the first end of the threshold compensation module, and the control end of the first initialization module is electrically connected to the first scan signal line; the first end of the second initialization module is electrically connected to the second initialization signal line, the second end of the second initialization module is electrically connected to the first end of the light-emitting structure, and the control end of the second initialization module is electrically connected to the second scan signal line; the first end of the third initialization module is electrically connected to the third initialization signal line, the second end of the third initialization module is electrically connected to the second end of the driving module, and the control end of the third initialization module is electrically connected to the second scan signal line.

20. The array substrate according to claim 1, wherein: The array substrate includes a driving circuit layer arranged on the substrate, and the driving circuit layer includes an active layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence; wherein, the active structure of the data writing module is arranged in the active layer, the gate of the data writing module is arranged in the first conductive layer, and the source and drain of the data writing module are arranged in the fourth conductive layer; the gate of the threshold compensation module is arranged in the third conductive layer, and the source and drain of the threshold compensation module are arranged in the fourth conductive layer.

21. The array substrate according to claim 20, wherein: The first signal line is disposed in the third conductive layer, and the second signal line is disposed in the first conductive layer.

22. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 21.

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