Display panel

Abstract

The invention discloses a display panel. The display panel comprises a substrate; the multiple conductive layers are arranged on one side of the substrate in a stacked mode and comprise the first conductive layer and the second conductive layer; the active layer is positioned on one side, far away from the substrate, of the second conductive layer; the active layer and the multiple conductive layers form at least one light-emitting control circuit, the light-emitting control circuit comprises a first output module, the first output module comprises a first transistor and a first capacitor, a first pole plate of the first capacitor is located on the first conductive layer, and a second pole plate of the first capacitor is located on the second conductive layer; a first grid of the first transistor is located on the second conductive layer; a second pole plate of the first capacitor is connected with the first grid of the first transistor; the ratio of the area of the first capacitor to the second area is between 0.2 and 1.0; and the second area is an overlapped area of the orthographic projection of the active layer on the substrate and the orthographic projection of the first grid electrode of the first transistor on the substrate. The display panel can solve the problem that the light-emitting control signal is unstable.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel. Background Art

[0002] With the development of display technology, medium and large-sized display panels have broad application prospects in the fields of automotive, tablets, laptops, televisions, etc. Display panels usually include a light-emitting control circuit for providing a light-emitting control signal to a pixel circuit. The light-emitting control circuit usually includes a pull-up module and a pull-down module to output a light-emitting control signal.

[0003] The light emitting control signal in the existing medium and large-sized display panels has the problem of instability, which affects the display effect. Summary of the invention

[0004] The present invention provides a display panel to solve the problem of unstable light emitting control signals in the existing display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising:

[0006] substrate;

[0007] A plurality of conductive layers stacked on one side of the substrate, the plurality of conductive layers comprising a first conductive layer and a second conductive layer, wherein the second conductive layer is located on a side of the first conductive layer away from the substrate;

[0008] an active layer, the active layer being located on a side of the second conductive layer away from the substrate;

[0009] The active layer and the multi-layer conductive layer constitute at least one light-emitting control circuit, the light-emitting control circuit comprises a first output module, the first output module comprises a first transistor and a first capacitor, the first electrode plate of the first capacitor is located in the first conductive layer, and the second electrode plate of the first capacitor is located in the second conductive layer;

[0010] The first gate of the first transistor is located in the second conductive layer, and the second plate of the first capacitor is connected to the first gate of the first transistor;

[0011] The ratio of the first area to the second area is between 0.2 and 1.0; wherein the first area is an overlapping area of ​​an orthographic projection of the first plate of the first capacitor on the substrate and an overlapping area of ​​an orthographic projection of the second plate of the first capacitor on the substrate, and the second area is an overlapping area of ​​an orthographic projection of the active layer on the substrate and an overlapping area of ​​an orthographic projection of the first gate of the first transistor on the substrate.

[0012] In the technical solution of the embodiment of the present invention, the light-emitting control circuit includes a first transistor for outputting a first potential, and a first capacitor connected to the first gate of the first transistor. By setting the area of ​​the first capacitor and the area where the positive projection of the active layer on the substrate overlaps with the positive projection of the first gate of the first transistor on the substrate within a reasonable range, that is, by specifying the size ratio of the first capacitor and the first transistor, the first capacitor can increase the potential of the first gate through coupling, thereby increasing the driving ability of the first transistor, while limiting the size of the first capacitor to avoid the first capacitor being too large and being easily coupled by other signals, thereby affecting the potential of the first gate of the first transistor, thereby affecting the first potential of the output light-emitting control signal. Therefore, in the present application, the size ratio of the first capacitor and the first transistor is set within a reasonable range, taking into account the suppression of the output light-emitting control signal from being affected by coupling, as well as the driving ability of the output level, so that the output light-emitting control signal is more stable and reliable.

[0013] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0015] Figure 1 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention;

[0016] Figure 2 A cross-sectional view of a display panel provided by an embodiment of the present invention;

[0017] Figure 3 A plan view of a first transistor provided by an embodiment of the present invention;

[0018] Figure 4 A schematic diagram of the structure of a light emitting control circuit provided by an embodiment of the present invention;

[0019] Figure 5 A schematic plan view of another display panel provided by an embodiment of the present invention;

[0020] Figure 6 A partial enlarged view of a display panel provided by an embodiment of the present invention;

[0021] Figure 7A plan view of a first conductive layer, a second conductive layer and an active layer in a display panel provided by an embodiment of the present invention;

[0022] Figure 8 A schematic plan view of a second conductive layer, an active layer and a third conductive layer in a display panel provided by an embodiment of the present invention;

[0023] Fig. 9 A schematic plan view of a fourth transistor in a display panel provided by an embodiment of the present invention;

[0024] Fig.10 A cross-sectional view of another display panel provided by an embodiment of the present invention;

[0025] Fig.11 A signal waveform diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Figure 1 A schematic diagram of a planar structure of a display panel provided by an embodiment of the present invention, Figure 2 A cross-sectional view of a display panel provided by an embodiment of the present invention, Figure 2 For along Figure 1 AA' section view, see Figure 1 and Figure 2 , the display panel comprises:

[0029] Substrate 10;

[0030] A plurality of conductive layers stacked on one side of the substrate, the plurality of conductive layers comprising a first conductive layer 11 and a second conductive layer 12, wherein the second conductive layer 12 is located on a side of the first conductive layer 11 away from the substrate 10;

[0031] An active layer 13, where the active layer 13 is located on a side of the second conductive layer 12 away from the substrate;

[0032] The active layer 13 and the multi-layer conductive layer constitute at least one light emitting control circuit, the light emitting control circuit comprises a first output module, the first output module comprises a first transistor T1 and a first capacitor C1, a first plate 101 of the first capacitor C1 is located on the first conductive layer 11, and a second plate 102 of the first capacitor C1 is located on the second conductive layer 12;

[0033] The first gate of the first transistor T1 is located in the second conductive layer 12 , and the second electrode 102 of the first capacitor C1 is connected to the first gate of the first transistor T1 .

[0034] The ratio of the first area to the second area is between 0.2 and 1.0; wherein the first area is the area where the orthographic projection of the first plate 101 of the first capacitor C1 on the substrate 10 overlaps with the orthographic projection of the second plate 102 of the first capacitor C1 on the substrate 10, and the second area is the area where the orthographic projection of the first active layer on the substrate 10 overlaps with the orthographic projection of the first gate of the first transistor T1 on the substrate 10. The channel region of the first transistor T1 is located in the active layer, and the second area can be regarded as the area of ​​the channel region of the first transistor T1.

[0035] Specifically, the substrate 10 is used to provide protection and support for the display panel, wherein the substrate 10 can be a flexible substrate formed of materials such as polyimide (PI), polyethylene naphthalate (PEN) or polyethylene terephthalate (PET), or a hard substrate formed of materials such as glass. A multi-layer conductive layer is arranged on one side of the substrate 10, and the multi-layer conductive layers are isolated from each other by an insulating layer. A plurality of light-emitting control circuits and pixel circuits are formed in the display panel, and the pixel circuit is used to respond to the light-emitting control signal in the light-emitting stage, transmit the driving current to the light-emitting element, so as to drive the light-emitting element to emit light, and the light-emitting control circuit is used to provide the light-emitting control signal to the pixel circuit. Among them, the light-emitting control circuit includes a first output module for outputting a first potential, and also includes a second output module for outputting a second potential, wherein the first potential and the second potential are high and low potentials to each other, the first potential is a high level, and the second potential is a low level. Optionally, the first pole of the first transistor T1 is connected to the first potential, and the second pole of the first transistor T1 is connected to the output terminal OUT of the light-emitting control circuit. The first transistor T1 includes a first gate and a second gate. The first gate may be a bottom gate and the second gate may be a top gate, or the first gate is a top gate and the second gate is a bottom gate. In this embodiment, the first gate is a bottom gate and the second gate is a top gate. The first transistor T1 is used to transmit the first potential to the output terminal OUT of the light emitting control circuit in response to the potential of the second gate. The first gate G11 of the first transistor T1 is connected to the first capacitor C1.

[0036] The first gate G11 of the first transistor T1 is connected to the second electrode plate 102 of the first capacitor C1 . The first gate and the second electrode plate 102 are located in the same layer and can be connected through a thirty-sixth connection line L36 located in the second conductive layer 12 .

[0037] The orthographic projection of the first plate 101 of the first capacitor C1 on the substrate 10 overlaps at least partially with the orthographic projection of the second plate 102 of the first capacitor C1 on the substrate 10, and the overlapping area of ​​the two constitutes the effective capacitance of the first capacitor C1. Optionally, the orthographic projection of the first plate 101 of the first capacitor C1 on the substrate 10 covers the orthographic projection of the second plate 102 of the first capacitor C1 on the substrate 10, and the area of ​​the first capacitor C1 is equal to the area of ​​the second plate 102 of the first capacitor C1. Optionally, the material of the active layer 13 includes metal oxide, which is conducive to reducing the leakage current of the light emitting control circuit.

[0038] By setting the ratio of the area of ​​the first capacitor C1 to the area of ​​the channel region of the first transistor T1 within a reasonable range, it is possible to take into account both the suppression of the light-emitting control signal output by the light-emitting control circuit from being affected by the coupling and the driving capability of the first transistor T1, and ensure that the output light-emitting control signal is more stable and reliable. Specifically, if the ratio of the area of ​​the first capacitor C1 to the area of ​​the channel region of the first transistor T1 is too large, the area of ​​the first capacitor C1 is relatively large, so that the coupling effect of the first capacitor C1 is relatively strong, resulting in the first capacitor C1 being very likely to affect the potential of the first gate G11 of the first transistor T1 due to the potential change of other signals, and under the action of the parasitic capacitance of the first transistor T1, the potential of the second electrode of the first transistor T1 is further affected, and the second electrode of the first transistor T1 is connected to the output terminal OUT, that is, the potential of the output light-emitting control signal is affected, resulting in the light-emitting control signal being unstable and the waveform fluctuating greatly. If the ratio of the area of ​​the first capacitor C1 to the channel area of ​​the first transistor T1 is too small, the coupling effect of the first capacitor C1 is small, and the degree to which the potential of the first plate 101 is raised by the potential change of the second plate 102 of the first capacitor C1 is small, resulting in a small degree of raising the potential of the first gate of the first transistor T1, and the driving ability of the first transistor T1 is reduced. Therefore, the ratio of the area of ​​the first capacitor C1 to the area of ​​the channel region of the first transistor T1 is set between 0.2-1.0, such as setting the ratio of the two to 0.4, 0.6 or 0.8. Preferably, the ratio of the area of ​​the first capacitor C1 to the area of ​​the channel region of the first transistor T1 is set to 0.6, so that the first transistor T1 has a higher driving ability and can also reduce the coupling effect of other signals on the output light-emitting control signal.

[0039] In the technical solution of the embodiment of the present invention, the light-emitting control circuit includes a first transistor for outputting a first potential, and a first capacitor connected to the first gate of the first transistor. By setting the area of ​​the first capacitor and the area where the positive projection of the active layer on the substrate overlaps with the positive projection of the first gate of the first transistor on the substrate within a reasonable range, that is, by specifying the size ratio of the first capacitor and the first transistor, the first capacitor can increase the potential of the first gate through coupling, thereby increasing the driving ability of the first transistor, while limiting the size of the first capacitor to avoid the first capacitor being too large and being easily coupled by other signals, thereby affecting the potential of the first gate of the first transistor, thereby affecting the first potential of the output light-emitting control signal. Therefore, in the present application, the size ratio of the first capacitor and the first transistor is set within a reasonable range, taking into account the suppression of the output light-emitting control signal from being affected by coupling, as well as the driving ability of the output level, so that the output light-emitting control signal is more stable and reliable.

[0040] Continue to refer Figure 1 and Figure 2, Optionally, the first transistor T1 is used to transmit the first potential VGH to the output terminal OUT of the light emitting control circuit;

[0041] The multilayer conductive layer also includes a third conductive layer and a fourth conductive layer 15, the third conductive layer is located on the side of the active layer 13 away from the substrate, the fourth conductive layer 15 is located on the side of the third conductive layer away from the substrate 10, and the fourth conductive layer includes a first clock signal line ECK1 for transmitting a first clock signal and a second power line for transmitting a second potential, and the second potential is less than the first potential; wherein the first clock signal line ECK1 and the second power line both extend along the second direction Y, and along the first direction X, the first clock signal line ECK1 and the second power line are respectively located on both sides of the first transistor.

[0042] The first output module also includes a second transistor T2, a first electrode of the second transistor T2 is connected to the second power line, a second electrode of the second transistor T2 is connected to the second plate of the first capacitor C1 through a first connecting line L1 located on the fourth conductive layer, and a gate of the second transistor T2 is connected to the first clock signal line ECK1 through a second connecting line L2 located on the fourth conductive layer, a third connecting line L3 located on the second conductive layer, and a fourth connecting line L4 located on the second conductive layer in sequence.

[0043] The display panel includes a first type via 1 and a second type via 2. The first type via 1 is a via extending from the fourth conductive layer 15 to the active layer 13 or from the fourth conductive layer 15 to the third conductive layer. The second type via 2 is a via extending from the fourth conductive layer 15 to the first conductive layer 11 or the second conductive layer 12. The first electrode and the second electrode of the second transistor T2 are both located in the fourth conductive layer. The source region and the drain region of the second transistor T2 are both located in the active layer 13. The first electrode (source electrode) of the second transistor T2 is connected to the source region of the second transistor T2 through the first type via 1 extending from the fourth conductive layer 15 to the active layer 13. The second electrode (drain electrode) of the second transistor T2 is connected to the drain region of the second transistor T2 through the first type via 1 extending from the fourth conductive layer 15 to the active layer 13. In the following, the first electrode and the second electrode of each transistor are connected to the source region and the drain region corresponding to the transistor in the active layer through the first type via 1 described above, and no further description is given. The first electrode of the second transistor T2 is connected to the second power line, which can be connected through at least one connection line located in the fourth conductive layer 15. When the second electrode of the second transistor T2 is connected to the second plate of the first capacitor C1 through the first connection line L1 located in the fourth conductive layer, specifically, the second electrode of the second transistor T2 is overlapped with one end of the first connection line L1. Since the second electrode of the second transistor T2 and the first connection line L1 are both located in the fourth metal layer 15, the connection can be achieved by overlapping the two. The other end of the first connection line L1 is connected to the second plate 102 of the first capacitor C1 through the second type of via 2 that runs through the fourth conductive layer 15 to the second conductive layer 12, so that the second plate 102 of the first capacitor C1 is connected to the first connection line L1.

[0044] The second transistor T2 can be a dual-gate transistor, including a top gate and a bottom gate, the bottom gate of the second transistor T2 is located in the second conductive layer 12, the top gate of the second transistor T2 is located in the third conductive layer 14, and the top gate and bottom gate of the second transistor T2 are connected through a via. Each transistor except the fourth transistor and the first transistor that appears below is also a dual-gate transistor as described in the second transistor T2, and the gate structure is similar to that of the second transistor T2, and will not be repeated later. In an optional embodiment, the connection method of the top gate and the bottom gate of the second transistor T1 can be: the bottom gate and the top gate of the second transistor T2 are both connected to the same structure of the fourth conductive layer through a via, thereby realizing the connection of the top gate and the bottom gate. Specifically, the bottom gate of the second transistor T2 is connected to the forty-fourth connection line L44 located in the fourth conductive layer 15 through the second type via 2 that penetrates from the fourth conductive layer 15 to the second conductive layer 12, and the top gate of the second transistor T2 is connected to the forty-fourth connection line L44 through the first type via 1 that penetrates from the fourth conductive layer 15 to the third conductive layer 14. The forty-fourth connection line L44 is overlapped with one end of the second connection line L2, and the other end of the second connection line L2 is connected to one end of the third connection line L3 through the second type via 2 that penetrates from the fourth conductive layer 15 to the second conductive layer 12, and the other end of the third connection line L3 is overlapped to one end of the fourth connection line L4 through a routing on the same layer as the third connection line L3, and the other end of the fourth connection line L4 is connected to the first clock signal line ECK1 through the second type via 2 that penetrates from the fourth conductive layer 15 to the second conductive layer 12.

[0045] The second potential is a potential lower than the low level of the high and low levels output by the light-emitting control signal. The gate of the second transistor T2 is connected to the first clock signal. The first clock signal is a pulse signal that alternately outputs high and low levels. After the second transistor T2 is turned on in response to the high level of the first clock signal, the second potential is transmitted to the first gate of the first transistor T1 to adjust the threshold voltage of the first transistor T1, so that the threshold voltage of the first transistor T1 is greater than zero, and then when the gate-source difference of the first transistor T1 is 0, the first transistor T1 can be completely turned off to suppress the off-state current of the first transistor T1.

[0046] Figure 3 A plan view of a first transistor provided by an embodiment of the present invention, referring to Figure 1 , Figure 2 and Figure 3 Optionally, the light emitting control circuit also includes a first output control module, which is connected to the second gate of the first transistor T1, and is used to control the potential of the second gate of the first transistor T1. The first transistor T1 is turned on or off in response to the potential of its own second gate.

[0047] The second gate of the first transistor T1 is located in the third conductive layer 14, and the first gate and the second gate of the first transistor T1 are insulated. The orthographic projection of the first gate of the first transistor T1 on the substrate 10 at least partially overlaps with the orthographic projection of the second gate of the first transistor T1 on the substrate, so that the threshold voltage of the first transistor T1 can be adjusted by the potential of the first gate. Preferably, the orthographic projection of the first gate of the first transistor T1 on the substrate covers the orthographic projection of the second gate of the first transistor T1 on the substrate.

[0048] Continue to refer Figure 1 , Figure 2 and Figure 3 Optionally, the first transistor and each transistor mentioned below include an active region located in the active layer, and the active region includes: a channel region, a source region, and a drain region; the orthographic projections of the top gate and the bottom gate of the first transistor and any transistor mentioned below on the substrate overlap at least partially with the orthographic projection of the channel region of the transistor on the substrate. For any transistor, the orthographic projection of the top gate of the transistor on the substrate overlaps at least partially with the orthographic projection of the active region of the transistor on the substrate, and a channel region is formed at the overlap, and the active regions located at both ends of the channel region form a source region and a drain region. The active layer includes the active region of the first transistor, and the active region of the first transistor includes at least two source-drain portions extending along the first direction X, and at least two source-drain portions are arranged along the second direction Y, and along the second direction Y, each source-drain portion is spaced apart to prevent the current flowing through the first transistor from being too large to break through the active layer during operation.

[0049] Furthermore, the first gate and the second gate of the first transistor T1 each include a first sub-portion, a second sub-portion, and a third sub-portion connected in sequence, the first sub-portion and the third sub-portion extend along the first direction X, the second sub-portion extends along the second direction Y, the first sub-portion and the third sub-portion are arranged along the second direction Y, the first direction X and the second direction Y intersect, and the third sub-portion 123 of the first gate of the first transistor T1 is connected to the second plate 102 of the first capacitor C1.

[0050] The first sub-portion 121 of the first gate of the first transistor T1, the second sub-portion 122 of the first gate of the first transistor T1, and the third sub-portion 123 of the first gate of the first transistor T1 are connected in sequence to form a U-shaped structure, and the first sub-portion 121 and the third sub-portion 123 of the first gate of the first transistor T1 are parallel. The first sub-portion 141 of the second gate of the first transistor T1, the second sub-portion 142 of the second gate of the first transistor T1, and the third sub-portion 143 of the second gate of the first transistor T1 are connected in sequence to form a U-shaped structure, and the first sub-portion 141 and the third sub-portion 143 of the second gate of the first transistor T1 are parallel. The third sub-portion 123 of the first gate of the first transistor T1 and the second electrode plate 102 of the first capacitor C1 are located in the same layer, both located in the second conductive layer 12, so the two can be overlapped through the routing located in the second conductive layer 12, thereby connecting the first gate of the first transistor T1 to the second electrode plate 102 of the first capacitor C1.

[0051] The fourth conductive layer includes a first power line VGH for transmitting a first potential, and also includes a first source-drain portion 151, a second source-drain portion 152 and a third source-drain portion 153, all of which extend along the first direction X, and a fourth source-drain portion 154, all of which extend along the second direction Y. The first source-drain portion 151, the second source-drain portion 152 and the third source-drain portion 153 are arranged in sequence along the second direction Y. Both the first sub-portion 121 of the first gate of the first transistor T1 and the first sub-portion 141 of the second gate are located between the first source-drain portion 151 and the second source-drain portion 152. Both the third sub-portion 123 of the first gate of the first transistor T1 and the third sub-portion 143 of the second gate are located between the second source-drain portion 152 and the third source-drain portion 153. Both the first source-drain portion 151 and the third source-drain portion 153 are connected to the fourth source-drain portion 154, and the second source-drain portion 152 is connected to the first power line VGH via a fifth connecting line L5 located in the fourth conductive layer.

[0052] In this embodiment, the first transistor T1 may be composed of two transistors connected in parallel, the first source-drain portion 151, the first sub-portion, and the second source-drain portion 152 constitute one transistor, and the second source-drain portion 152, the third sub-portion, and the third source-drain portion 153 constitute another transistor. The second source-drain portion 152, as the first electrode, i.e., the source electrode of the first transistor T1, is connected to the first power line VGH through the fifth connection line L5. The first source-drain portion 151 and the third source-drain portion 153, as the second electrode, i.e., the drain electrode of the first transistor T1, are connected to the output terminal OUT of the light emitting control circuit, wherein the fourth source-drain portion 154 may serve as the output terminal OUT of the light emitting control circuit.

[0053] Continue to refer Figure 1 , Figure 2 and Figure 3Optionally, the orthographic projection of the first sub-portion 121 of the first gate of the first transistor T1 on the substrate covers the orthographic projection of the first sub-portion 141 of the second gate of the first transistor T1 on the substrate, the orthographic projection of the second sub-portion 122 of the first gate of the first transistor T1 on the substrate covers the orthographic projection of the second sub-portion 142 of the second gate of the first transistor T1 on the substrate, and the orthographic projection of the third sub-portion 123 of the first gate of the first transistor T1 on the substrate covers the orthographic projection of the third sub-portion 143 of the second gate of the first transistor T1 on the substrate. The orthographic projection of the first gate of the first transistor T1 on the substrate at least covers the orthographic projection of the second gate on the substrate, so that the threshold voltage of the first transistor T1 can be better adjusted by adjusting the potential of the first gate. Further, the length of the first sub-portion 121 of the first gate of the first transistor T1 along the first direction X exceeds the length of the first sub-portion 141 of the second gate of the first transistor T1 along the first direction X by a first preset length a1, and / or the length of the first sub-portion 121 of the first gate of the first transistor T1 along the second direction Y exceeds the length of the first sub-portion 141 of the second gate of the first transistor T1 along the second direction Y by a second preset length, and / or the length of the second sub-portion 122 of the first gate of the first transistor T1 along the first direction X exceeds the length of the second sub-portion 142 of the second gate of the first transistor T1 along the first direction X by a third preset length. degree, and / or, a length of the second subportion 122 of the first gate of the first transistor T1 along the second direction Y exceeds a length of the second subportion 142 of the second gate of the first transistor T1 along the second direction Y by a fourth preset length, and / or, a length of the third subportion 123 of the first gate of the first transistor T1 along the first direction X exceeds a length of the third subportion 143 of the second gate of the first transistor T1 along the first direction X by a fifth preset length, and / or, a length of the third subportion 123 of the first gate of the first transistor T1 along the second direction Y exceeds a length of the third subportion 143 of the second gate of the first transistor T1 along the second direction Y by a sixth preset length.

[0054] Preferably, each sub-portion of the first gate of the first transistor is greater than the length of the corresponding sub-portion of the second gate in both the first direction X and the second direction Y, so as to ensure that the orthographic projection of the first gate of the first transistor T1 on the substrate completely covers the orthographic projection of the second gate of the first transistor T1 on the substrate. Figure 3The first preset length a1 is exemplarily shown in the figure, and other preset lengths can refer to the first preset length and are not shown again. Optionally, along the first direction X, the length of the first sub-portion 121 of the first gate of the first transistor T1 and the third sub-portion 123 of the first gate of the first transistor T1 are equal, and along the second direction Y, the length of the first sub-portion 121 of the first gate of the first transistor T1 and the third sub-portion 123 of the first gate of the first transistor T1 are equal; along the first direction X, the length of the first sub-portion 141 of the second gate of the first transistor T1 and the third sub-portion 143 of the second gate of the first transistor T1 are equal, and along the second direction Y, the length of the first sub-portion 141 of the second gate of the first transistor T1 and the third sub-portion 143 of the second gate of the first transistor T1 are equal. Optionally, the first preset length, the second preset length, the third preset length, the fourth preset length, the fourth preset length, the fifth preset length and the sixth preset length are all greater than or equal to 1 micron and less than or equal to 3 microns. Preferably, the first preset length to the sixth preset length are all equal to 2 microns. Optionally, the length of the first sub-portion 121 of the first gate of the first transistor T1 along the first direction X is greater than the length of the first sub-portion 121 of the first gate along the second direction Y, and the length of the first sub-portion 141 of the second gate of the first transistor T1 along the first direction X is greater than the length of the first sub-portion 141 of the second gate along the second direction Y. The second direction Y is the direction of the source-drain connection of the first transistor T1, that is, the channel length direction of the first transistor T1, the first direction X is the channel width direction of the first transistor T1, the width-to-length ratio of the first transistor T1 is equal to the ratio of the channel width to the channel length, and the channel width of the first transistor T1 is equal to the sum of the length of the first sub-portion 141 of the second gate along the first direction X and the length of the third sub-portion 143 along the first direction X, and the channel length of the first transistor T1 is equal to the length of the first sub-portion 141 or the third sub-portion 143 of the second gate along the second direction Y. As for the second gate of the first transistor T1, the length of the first sub-portion 141 along the first direction X is much greater than the length of the first sub-portion 141 along the second direction Y, so that the width-to-length ratio of the first transistor T1 is relatively large, thereby allowing the scan line transmitting the light control signal in the display panel to jump quickly.

[0055] Figure 4 A schematic diagram of a light emitting control circuit according to an embodiment of the present invention is provided. Figure 4Optionally, the light emitting control circuit includes a first output module 3, a second output module 4, a first output control module, and a second output control module 5. The second output control module 5 is connected to the control end of the second output module 4 and is used to control the potential of the control end of the second output module 4. The first output control module further includes a forward transmission unit 6 and a gate control unit 7. The output end N2 of the forward transmission unit 6 is directly or indirectly connected to the second gate of the first transistor T1 and is used to transmit a start signal SIN to the second gate of the first transistor T1. The gate control unit 7 is connected to the second gate of the first transistor T1. The gate control unit 7 includes a second capacitor C2, which is used to increase the potential of the second gate of the first transistor T1 through the coupling effect of the second capacitor C2.

[0056] Optionally, the gate control unit 7 also includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13 and a fourteenth transistor T14, the first electrode of the eleventh transistor T11 is connected to the second gate of the first transistor T1, the second electrode of the eleventh transistor T11 is connected to the second electrode plate of the second capacitor C2, the second electrode of the eleventh transistor T11 is also connected to the gate of the eleventh transistor T11, the first electrode of the tenth transistor T10 is connected to the second clock signal line ECK2 transmitting the second clock signal, the second electrode of the tenth transistor T10 is connected to the first electrode plate of the second capacitor C2, the first electrode of the fourteenth transistor T14 is connected to the third power line VGL, the gate of the fourteenth transistor T14 is connected to the control end of the second output module 4, and the tenth The second electrodes of the four transistors T12 are respectively connected to the second electrodes of the tenth transistor T10 and the first electrode plate of the second capacitor C2, the first electrode of the twelfth transistor T12 is connected to the start signal line SIN for transmitting the start signal, the second electrode is connected to the first electrode of the thirteenth transistor T13, the gate of the twelfth transistor T12 is connected to the first clock signal line ECK1 for transmitting the first clock signal, the second stage of the thirteenth transistor T13 is respectively connected to the gate and the second electrode of the eleventh transistor T11, and the second electrode plate of the second capacitor C2, the gate of the thirteenth transistor T13 is connected to the first power line, the first electrode of the ninth transistor T9 is connected to the output terminal N2 of the forward transmission unit 6, the second electrode of the ninth transistor T9 is connected to the second gate of the first transistor T1, and the gate of the ninth transistor T9 is connected to the first power line VGH. The structures of the other modules are as follows: Figure 4 As shown, no further details are given.

[0057] Figure 5 A schematic plan view of another display panel provided by an embodiment of the present invention, Figure 6 A partial enlarged view of a display panel provided by an embodiment of the present invention, wherein: Figure 6 For Figure 5 The enlarged view of the local area 8 in the figure, Figure 7 A plan view of a first conductive layer, a second conductive layer and an active layer in a display panel provided by an embodiment of the present invention, Figure 8 A schematic plan view of a second conductive layer, an active layer and a third conductive layer in a display panel provided by an embodiment of the present invention, Fig. 9 A schematic plan view of a fourth transistor in a display panel provided by an embodiment of the present invention, referring to Figure 4-Figure 9 , Optionally, the first electrode plate of the second capacitor C2 is located in the first conductive layer, and the second electrode plate of the second capacitor C2 is located in the second conductive layer;

[0058] The difference between the area of ​​the second capacitor C2 and the first area is less than a preset threshold; wherein the area of ​​the second capacitor C2 is the area of ​​the overlapping part of the orthographic projection of the first plate of the second capacitor C2 on the substrate and the orthographic projection of the second plate of the second capacitor C2 on the substrate.

[0059] In order to save layout space, in this embodiment, the orthographic projection of the first plate of the second capacitor C2 on the substrate covers the orthographic projection of the second plate of the second capacitor C2 on the substrate, so as to ensure that the area of ​​the second capacitor C2 is large. When the first clock signal jumps from a low potential to a high potential, the second capacitor C2 raises the potential of the second gate of the first transistor T1 through the eleventh transistor T11 under its own coupling effect to improve the driving ability of the first transistor T1. The larger the area of ​​the second capacitor C2, the more conducive it is to improve the driving ability of the first transistor T1. Therefore, the role of the second capacitor C2 is the same as that of the first capacitor C1, and both are used to improve the driving ability of the first transistor T1. The difference between the area of ​​the second capacitor C2 and the area of ​​the first capacitor C1 is less than the preset threshold value to ensure that the area of ​​the second capacitor C2 is similar to the area of ​​the first capacitor C1. In an optional embodiment, the area of ​​the second capacitor C2 is the same as the area of ​​the first capacitor C1.

[0060] The first output module 3 also includes a third transistor T3, the fourth conductive layer includes a second clock signal line ECK2 for transmitting a second clock signal, and the first electrode of the third transistor T3 is connected to the second clock signal line ECK2 through the sixth connection line L6 located on the fourth conductive layer and the seventh connection line L7 located on the first conductive layer in sequence. Specifically, the first electrode of the third transistor T3 is located on the fourth conductive layer, and is directly overlapped with one end of the sixth connection line L6, and the other end of the sixth connection line L6 is connected to one end of the seventh connection line L7 through the second type via 2 that penetrates from the fourth conductive layer to the first conductive layer, and the other end of the seventh connection line L7 is connected to the second clock signal line ECK2 through the second type via 2 that penetrates from the fourth conductive layer to the first conductive layer, thereby realizing the connection between the first electrode of the third transistor T3 and the second clock signal line ECK2. The second electrode of the third transistor T3 is connected to the first electrode plate of the first capacitor C1 through the second type via 2 that penetrates from the fourth conductive layer to the first conductive layer, and the gate of the third transistor T3 is connected to the output terminal N2 of the forward transmission unit through the eighth connection line L8 located in the fourth conductive layer, the thirty-seventh connection line L37 located in the second conductive layer, and the ninth connection line L9 located in the second conductive layer. Specifically, the gate of the third transistor T3 is directly connected to one end of the eighth connection line L8, and the other end of the eighth connection line L8 is connected to the thirty-seventh connection line L37 through the second type via 2 that penetrates from the fourth conductive layer to the second conductive layer, and the thirty-seventh connection line L37 is connected to one end of the ninth connection line L9, and the other end of the ninth connection line L9 is connected to the output terminal N2 of the forward transmission unit 6. Wherein, reference Figure 4 In the circuit shown, the gate of the seventh transistor T7 serves as the output terminal N2 of the forward transmission unit 6.

[0061] Continue to refer Figure 4-Figure 9 Optionally, the light emitting control circuit further includes a second output module 4, the second output module 4 includes a fourth transistor T4, the fourth transistor T4 is used to output a third potential to an output terminal OUT of the light emitting control circuit, the third potential is greater than the second potential, and the first potential is greater than the third potential;

[0062] The first gate of the fourth transistor T4 is located in the second conductive layer, and the first gate of the fourth transistor T4 is connected to the second power line VGLL through the thirty-eighth connecting line L38. Specifically, the first gate of the fourth transistor T4 is overlapped with one end of the thirty-eighth connecting line L38, and the other end of the thirty-eighth connecting line L38 is connected to the second power line VGLL through the second type via 2 that runs from the fourth conductive layer to the second conductive layer, and finally the first gate of the fourth transistor T4 is connected to the second potential. The fourth transistor T4 also includes a second gate, the second gate of the fourth transistor T4 is located in the third conductive layer, and the first gate and the second gate of the fourth transistor T4 are insulated, and the first gate of the fourth transistor T4 is connected to the second potential to regulate the threshold voltage of the fourth transistor T4, so that its threshold voltage is positively biased and greater than zero, to ensure that when the potential of the second gate of the fourth transistor T4 is at a low level, the fourth transistor T4 can be completely turned off.

[0063] Optionally, the active layer includes a fourth transistor active area, the fourth transistor active area includes at least two source-drain portions extending along the first direction X, at least two source-drain portions are arranged along the second direction Y, and along the second direction Y, each source-drain portion is spaced apart to prevent the current flowing through the fourth transistor from being too large to break through the active layer during operation. Among them, at least one source-drain portion included in the fourth transistor active area is shared with at least one source-drain portion included in the first transistor active area, so that at least part of the drain area of ​​the fourth transistor active area is shared with at least part of the drain area of ​​the first transistor active area.

[0064] The first gate and the second gate of the fourth transistor T4 both include a fourth sub-portion, a fifth sub-portion, a sixth sub-portion, and a seventh sub-portion. The fourth sub-portion, the fifth sub-portion, and the sixth sub-portion all extend along the first direction X, and the seventh sub-portion extends along the second direction Y. The fourth sub-portion, the fifth sub-portion, and the sixth sub-portion are arranged in sequence along the second direction Y, and the fourth sub-portion, the fifth sub-portion, and the sixth sub-portion are all connected to the seventh sub-portion. Any two of the fourth sub-portion 124, the fifth sub-portion 125, and the sixth sub-portion 126 of the first gate of the fourth transistor T4 are parallel to each other, and each of the fourth sub-portion 124 to the sixth sub-portion 126 is directly overlapped with the seventh sub-portion 127 of the first gate of the fourth transistor T4. Any two of the fourth sub-portion 144, the fifth sub-portion 145, and the sixth sub-portion 146 of the second gate of the fourth transistor T4 are parallel to each other, and each of the fourth sub-portion 144 to the sixth sub-portion 146 is directly overlapped with the seventh sub-portion 147 of the second gate of the fourth transistor T4. The fourth sub-portion 124 of the first gate of the fourth transistor T4 is connected to the second power line VGLL through the thirty-eighth connection line L38, thereby realizing that the first gate of the fourth transistor T4 is connected to the second potential. The sixth sub-portion 126 of the first gate of the fourth transistor T4 is located on a side of the fifth sub-portion 125 of the first gate of the fourth transistor T4 close to the first sub-portion 121 of the first gate of the first transistor T1, and the sixth sub-portion 146 of the second gate of the fourth transistor T4 is located on a side of the fifth sub-portion 145 of the second gate of the fourth transistor T4 close to the first sub-portion 141 of the second gate of the first transistor T1.

[0065] The fourth conductive layer includes a fifth source drain portion 155, a sixth source drain portion 156, a seventh source drain portion 157 and an eighth source drain portion 158 arranged in sequence along the second direction Y, a ninth source drain portion 159 and a tenth source drain portion 1510 extending along the second direction Y, the fifth source drain portion 155, the sixth source drain portion 156, the seventh source drain portion 157 and the eighth source drain portion 158 are all located between an extension line of the ninth source drain portion 159 along the second direction Y and an extension line of the tenth source drain portion 1510 along the second direction Y, the fifth source drain portion 155 and the seventh source drain portion 157 are both connected to the ninth source drain portion 159, and the sixth source drain portion 156 and the eighth source drain portion 158 are both connected to the tenth source drain portion 1510. Any two of the fifth source drain portion 155, the sixth source drain portion 156, the seventh source drain portion 157 and the eighth source drain portion 158 are parallel to each other.

[0066] Both the fourth sub-portion 124 of the first gate and the fourth sub-portion 144 of the second gate of the fourth transistor T4 are located between the fifth source-drain portion 155 and the sixth source-drain portion 156, both the fifth sub-portion 125 of the first gate and the fifth sub-portion 145 of the second gate of the fourth transistor T4 are located between the sixth source-drain portion 156 and the seventh source-drain portion 157, and both the sixth sub-portion 126 of the first gate and the sixth sub-portion 146 of the second gate of the fourth transistor T4 are located between the seventh source-drain portion 157 and the eighth source-drain portion 158. The fourth transistor T4 can be regarded as being composed of three transistors connected in parallel, wherein the fifth source-drain portion 155, the fourth sub-portion and the sixth source-drain portion 156 constitute one transistor, the sixth source-drain portion 156, the fifth sub-portion and the seventh source-drain portion 157 constitute one transistor, and the seventh source-drain portion 157, the sixth sub-portion and the eighth source-drain portion 158 constitute one transistor.

[0067] The fourth conductive layer also includes a third power line VGL for transmitting a third potential, and the third power line VGL is connected to the seventh source-drain portion 157 via the tenth connection line L10 located in the first conductive layer. Specifically, the third power line VGL is connected to one end of the tenth connection line L10 via a second type via 2 that penetrates from the fourth conductive layer to the first conductive layer, and the other end of the tenth connection line L10 is connected to the seventh source-drain portion 157 via a second type via 2 that penetrates from the fourth conductive layer to the first conductive layer, that is, the fifth source-drain portion 155 or the seventh source-drain portion 157 is connected to the third potential as the first electrode of the fourth transistor T4. The tenth source-drain portion 1510 is connected to the output terminal OUT of the light-emitting control circuit, wherein the sixth source-drain portion 156 or the eighth source-drain portion 158 can be connected to the output terminal OUT of the light-emitting control circuit as the second electrode of the fourth transistor T4. Among them, Figure 3 The first source-drain portion 151 in the embodiment may be reused as the eighth source-drain portion 158 .

[0068] Optionally, the length of the fourth subportion 124 of the first gate of the fourth transistor T4 along the first direction X exceeds the length of the fourth subportion 144 of the second gate of the fourth transistor T4 along the first direction X by a first preset length, and / or the length of the fourth subportion 124 of the first gate of the fourth transistor T4 along the second direction Y exceeds the length of the fourth subportion 144 of the second gate of the fourth transistor T4 along the second direction Y by a second preset length, and / or the length of the fifth subportion 125 of the first gate of the fourth transistor T4 along the first direction X exceeds the length of the fifth subportion 145 of the second gate of the fourth transistor T4 along the first direction X by a third preset length, And / or, the length of the fifth sub-portion 125 of the first gate of the fourth transistor T4 along the second direction Y exceeds the length of the fifth sub-portion 145 of the second gate of the fourth transistor T4 along the second direction Y by a fourth preset length, and / or, the length of the sixth sub-portion 126 of the first gate of the fourth transistor T4 along the first direction X exceeds the length of the sixth sub-portion 146 of the second gate of the fourth transistor T4 along the first direction X by a fifth preset length, and / or, the length of the sixth sub-portion 126 of the first gate of the fourth transistor T4 along the second direction Y exceeds the length of the sixth sub-portion 146 of the second gate of the fourth transistor T4 along the second direction Y by a sixth preset length.

[0069] Each sub-portion of the first gate of the fourth transistor T4 is greater than the length of the corresponding sub-portion of the second gate, whether along the first direction X or along the second direction Y, to ensure that the orthographic projection of the first gate of the fourth transistor T4 on the substrate completely covers the orthographic projection of the second gate of the fourth transistor T4 on the substrate. Optionally, along the first direction X, the fourth sub-portion 124, the fifth sub-portion 125, and the sixth sub-portion 126 of the first gate of the fourth transistor T4 are equal in length, and along the second direction Y, the fourth sub-portion 124, the fifth sub-portion 125, and the sixth sub-portion 126 of the first gate of the fourth transistor T4 are equal in length. Along the first direction X, the fourth sub-portion 144, the fifth sub-portion 145, and the sixth sub-portion 146 of the second gate of the fourth transistor T4 are equal in length, and along the second direction Y, the fourth sub-portion 144, the fifth sub-portion 145, and the sixth sub-portion 146 of the second gate of the fourth transistor T4 are equal in length. Optionally, the first preset length, the second preset length, the third preset length, the fourth preset length, the fourth preset length, the fifth preset length and the sixth preset length are all greater than or equal to 1 micron and less than or equal to 3 microns. Preferably, the first preset length to the sixth preset length are all equal to 2 microns. Optionally, the length of any sub-portion of the fourth transistor T4 along the first direction X is greater than the length along the second direction Y. The second direction Y is the direction of the source-drain connection of the fourth transistor T4, that is, the channel length direction of the fourth transistor T4. The first direction X is the channel width direction of the fourth transistor T4. The width-to-length ratio of the fourth transistor T4 is equal to the ratio of the channel width to the channel length. The channel width of the fourth transistor T4 is equal to the sum of the length of the fourth sub-portion 144 of the second gate thereof along the first direction X, the length of the fifth sub-portion 145 along the first direction X, and the length of the sixth sub-portion 146 along the first direction X. The channel length of the fourth transistor T4 is equal to the length of the fourth sub-portion 144, the fifth sub-portion 145 or the sixth sub-portion 146 of the second gate of the fourth transistor T4 along the second direction Y. The length of the fourth sub-portion 144 along the first direction X is much greater than the length along the second direction Y, so that the width-to-length ratio of the fourth transistor T4 is relatively large, thereby making the scanning line transmitting the light-emitting control signal in the display panel jump faster, ensuring normal display of the display panel.

[0070] Optionally, the second output module 4 further includes a third capacitor C3, a first electrode plate of the third capacitor C3 is located at the first conductive layer, and a second electrode plate of the third capacitor C3 is located at the second conductive layer;

[0071] The first electrode plate of the third capacitor C3 is connected to the ninth source-drain portion 159 through the eleventh connection line L11 located in the fourth conductive layer. Specifically, the first electrode plate of the third capacitor C3 is connected to one end of the eleventh connection line L11 through the second type via 2 penetrating from the fourth conductive layer to the first conductive layer, and the other end of the eleventh connection line L11 is directly overlapped with the ninth source-drain portion 159, thereby realizing that the first electrode plate of the third capacitor C3 is connected to the first electrode of the fourth transistor T4 through the ninth source-drain portion 159. The second electrode plate of the third capacitor C2 is connected to the fourth sub-portion 144 of the second gate of the fourth transistor T4 through the twelfth connection line L12 located in the third conductive layer. Specifically: the second electrode plate of the third capacitor C3 is first connected to the forty-fifth connection line located in the fourth conductive layer through the via penetrating from the fourth conductive layer to the second conductive layer, and the forty-fifth connection line is connected to the twelfth connection line L12 through the first type via penetrating from the fourth conductive layer to the third conductive layer, so as to realize that the second electrode plate of the third capacitor is connected to the twelfth connection line L12. The twelfth connection line L12 is connected to the fourth sub-portion 144 of the second gate of the fourth transistor T4, and finally the second electrode plate of the third capacitor C3 is connected to the second gate of the fourth transistor T4.

[0072] Optionally, the area of ​​the third capacitor C3 is smaller than the first area, that is, the area of ​​the first capacitor C1, and the area of ​​the third capacitor C3 is the area where the orthographic projection of the first plate of the third capacitor C3 on the substrate overlaps the orthographic projection of the second plate of the third capacitor C3 on the substrate. In order to save the layout area, the orthographic projection of the first plate of the third capacitor C3 on the substrate in this embodiment covers the orthographic projection of the second plate of the third capacitor C3 on the substrate, that is, the area of ​​the third capacitor C3 is equal to the area of ​​the second plate of the third capacitor C3. The third capacitor C3 is only used to store the potential of the second gate of the fourth transistor T4, so the area does not need to be too large to save the layout. Optionally, the ratio of the area of ​​the third capacitor C3 to the area of ​​the first capacitor C1 is greater than or equal to 0.4 and less than or equal to 0.6, preferably 0.5 times.

[0073] In this embodiment, the first electrode of the second transistor T2 is connected to the seventh sub-portion 127 of the first gate of the fourth transistor T4 through the thirteenth connection line L13 located in the second conductive layer. Specifically, the first electrode of the second transistor T2 is connected to one end of the thirteenth connection line L13 through the second type via 2 that penetrates from the fourth conductive layer to the second conductive layer, and the other end of the thirteenth connection line L13 is overlapped with the seventh sub-portion 127 of the first gate of the fourth transistor T4, thereby realizing that the first electrode of the second transistor T2 is connected to the second power line through the seventh sub-portion 127 of the first gate of the fourth transistor T4 and the fourth sub-portion 124.

[0074] Continue to refer Figure 4-Figure 9Optionally, the light emitting control circuit further includes a second output control module 5, and the second output control module 5 is used to transmit an inverted signal of the start signal to the second gate of the fourth transistor T4;

[0075] The second output control module includes a fifth transistor T5 and a fourth capacitor C4, wherein the first plate of the fourth capacitor C4 is located in the first conductive layer, the second plate of the fourth capacitor T4 is located in the second conductive layer, and the first plate of the fourth capacitor C4 is connected to the gate of the fifth transistor T5. Specifically, the first plate of the fourth capacitor C4 is overlapped with the thirty-ninth connecting line L39 located in the first conductive layer, and the thirty-ninth connecting line L39 is connected to one end of the fortieth connecting line L40 located in the fourth conductive layer through the second type via 2 that runs through the fourth conductive layer to the first conductive layer, and the fortieth connecting line L40 is connected to the gate of the fifth transistor T5 through the via, so as to finally realize the connection between the first plate of the fourth capacitor C4 and the gate of the fifth transistor T5. The second plate of the fourth capacitor C4 is connected to the first clock signal line ECK1 through the third connecting line L3 and the fourth connecting line L4 in sequence. Specifically, the second plate of the fourth capacitor C4 is overlapped with the third connecting line L3, the third connecting line L3 is overlapped with the fourth connecting line L4 through the gates of the subsequent eighth transistor T8 and the twelfth transistor T12, and the fourth connecting line L4 is connected to the first clock signal line ECK1 through the second type via 2 that runs through the fourth conductive layer to the second conductive layer, thereby finally realizing the second plate of the fourth capacitor C4 being connected to the first clock signal.

[0076] The first electrode of the fifth transistor T5 is connected to one end of the seventeenth connection line L17 located on the second conductive layer through the second type via 2, and the other end of the seventeenth connection line L17 is overlapped with the second electrode plate of the fourth capacitor C4, thereby realizing that the first electrode of the fifth transistor T5 is connected to the second electrode plate of the fourth capacitor C4 through the seventeenth connection line L17 located on the second conductive layer. The second electrode of the fifth transistor T5 is connected to the fourth sub-portion 144 of the second gate of the fourth transistor T4 through the fourteenth connection line L14 located on the fourth conductive layer, the fifteenth connection line L15 located on the fourth conductive layer, the sixteenth connection line L16 located on the fourth conductive layer, and the twelfth connection line L12 in sequence. Specifically, the second electrode of the fifth transistor T5 is overlapped with one end of the fourteenth connection line L14, the other end of the fourteenth connection line L14 is overlapped with one end of the fifteenth connection line L15, the other end of the fifteenth connection line L15 is overlapped with one end of the sixteenth connection line L16, and the other end of the sixteenth connection line L16 is connected to the twelfth connection line L12 through the first type via 1 that penetrates from the fourth conductive layer to the third conductive layer, and finally the second electrode of the fifth transistor T5 is connected to the second gate of the fourth transistor T4. In this embodiment, the twelfth connection line L12 is connected to the gate of the fourteenth transistor T14 described later, and the sixteenth connection line L16 is connected to the twelfth connection line L12 through the gate of the fourteenth transistor T14.

[0077] The area of ​​the fourth capacitor C4 is smaller than the first area, that is, smaller than the area of ​​the first capacitor C1; the area of ​​the fourth capacitor C4 is the area where the orthographic projection of the first plate of the fourth capacitor C4 on the substrate overlaps the orthographic projection of the second plate of the fourth capacitor C4 on the substrate. In order to save the area of ​​the layout, the orthographic projection of the first plate of the fourth capacitor C4 on the substrate covers the orthographic projection of the second plate of the fourth capacitor C4 on the substrate, and the area of ​​the fourth capacitor C4 is the area of ​​the second plate. The fifth transistor T5 does not need to have a driving capability as strong as the first transistor T1. Therefore, in order to save the layout area, the area of ​​the fourth capacitor C4 can be set to be smaller than the area of ​​the first capacitor C1 to reduce the layout space. Optionally, the ratio of the area of ​​the fourth capacitor C4 to the first area is greater than or equal to 0.5 and less than or equal to 0.7. If the area of ​​the fourth capacitor C4 is too large, the first clock signal will charge and discharge it more, resulting in increased power consumption. If the area of ​​the fourth capacitor C4 is too small, when the first clock signal jumps to a high level, the potential of the gate of the fifth transistor T5 is small due to the weak coupling ability of the fourth capacitor C4, resulting in a weak driving ability of the fifth transistor T5, which leads to insufficient low-level driving ability of the output signal. Therefore, the area of ​​the fourth capacitor C4 needs to be set within a reasonable range to take into account both the layout size and the driving ability. Preferably, the ratio of the area of ​​the fourth capacitor C4 to the first area is equal to 0.6.

[0078] Continue to refer Figure 4-Figure 9Optionally, the fourth conductive layer includes a start signal line EIN for transmitting a start signal, and the second output control module 5 also includes a sixth transistor T6, and the first electrode of the sixth transistor T6 is sequentially connected to the first electrode plate of the third capacitor C3 through the eighteenth connection line L18 located on the fourth conductive layer and the forty-first connection line L41 located on the first conductive layer. Specifically, the first electrode of the sixth transistor T6 is overlapped with one end of the eighteenth connection line L18, and the other end of the eighteenth connection line L18 is connected to one end of the forty-first connection line L41 through the second type via 2 that runs from the fourth conductive layer to the first conductive layer, and the other end of the forty-first connection line L41 is overlapped with the first electrode plate of the third capacitor C3, and finally the first electrode of the sixth transistor T6 is connected to the third power line VGL through the first electrode plate of the third capacitor C3. The second electrode of the sixth transistor T6 is connected to the first electrode plate of the fourth capacitor C4 through the nineteenth connection line L19 located in the fourth conductive layer and the forty-second connection line L42 located in the first conductive layer. Specifically, the second electrode of the sixth transistor T6 is overlapped with one end of the nineteenth connection line L19, and the other end of the nineteenth connection line L19 is connected to the forty-second connection line L42 through the second type via 2 that runs from the fourth conductive layer to the first conductive layer. The forty-second connection line L42 is overlapped with the first electrode plate of the fourth capacitor C4, and finally the second electrode of the fourth transistor T4 is respectively connected to the first electrode plate of the fourth capacitor C4 and the gate of the fifth transistor T5. The gate of the sixth transistor T6 is connected to the start signal line EIN through the twentieth connection line L20 located in the fourth conductive layer. Specifically, the sixth transistor T6 is a dual-gate transistor, the bottom gate is located in the second conductive layer and connected to the twentieth connecting line L20 through a via, the top gate is located in the third conductive layer and connected to the twentieth connecting line L20 through a via, and the twentieth connecting line L20 is overlapped with the start signal line EIN, thereby realizing that the gate of the sixth transistor T6 is connected to the start signal.

[0079] The channel regions of the fifth transistor T5, the sixth transistor T6, the second transistor T2, and the third transistor T3 are all located in the active layer, and the channel length of the sixth transistor T6 is greater than the channel length of each transistor in the fifth transistor T5, the second transistor T2, and the third transistor T3. The directions of the channel lengths of the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are all in the second direction Y, and the direction of the channel length of the third transistor T3 is the first direction X. The channel length is the first and second poles of the transistor, that is, the connection direction of the source and the drain. Since each transistor in this embodiment is a dual-gate transistor, the channel length can be considered to be the length of the overlapped part of the positive projection of the active layer on the substrate and the positive projection of the top gate of the transistor on the substrate along the connection direction of the source and the drain. The channel length is positively correlated with the threshold voltage of the transistor. If the channel length is set larger, the threshold voltage of the transistor will be positively biased to ensure that the sixth transistor T6 can be completely turned off, so as to avoid the leakage current affecting the potential of the gate of the fifth transistor T5 when the sixth transistor T6 cannot be completely turned off, causing the fifth transistor T5 to be turned off when it is turned on. Under the influence of the irrelevant current, the coupling effect of the fourth capacitor C4 is relatively strong. When the first clock signal is at a high level, the gate potential of the fifth transistor T5 is raised due to the coupling effect of the fourth capacitor C4, so that the fifth transistor T5 is fully turned on, and the high level of the first clock signal is quickly transmitted to the gate of the fourth transistor T4, and the fourth transistor T4 is controlled to be turned on, so that the signal outputted from the output terminal outputs a low level, and the downward jump speed of the signal outputted from the output terminal of the light emitting control circuit is enhanced. Optionally, the channel length of the sixth transistor T6 is greater than or equal to 6 microns and less than or equal to 8 microns, preferably 7 microns.

[0080] Continue to refer Figure 4-Figure 9 Optionally, the second output control module 5 further includes a seventh transistor T7, the forward transmission unit 6 includes an eighth transistor T8, and the gate control unit 7 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13 and a fourteenth transistor T14;

[0081] The first electrode of the seventh transistor T7 is connected to the first electrode plate of the third capacitor C3 through the eighteenth connection line L18 and the forty-first connection line L41 in sequence, and the first electrode plate is connected to the seventh source drain part 157 through the eleventh connection line L11 and the ninth source drain part 159, and the seventh source drain part 157 is connected to the third power line VGL, so that the first electrode of the seventh transistor T7 is finally connected to the third potential. The second electrode of the seventh transistor T7 is connected to the fourth sub-portion 144 of the second gate of the fourth transistor T4 through the fifteenth connection line L15, the sixteenth connection line L16, and the twelfth connection line L12 in sequence, so that the second electrode of the seventh transistor T7 is finally connected to the second gate of the fourth transistor T4. The gate of the seventh transistor T7 is connected to the gate of the third transistor T3 through the ninth connection line L9 and the eighth connection line L8 in sequence.

[0082] The first electrode of the eighth transistor T8 is connected to the start signal line EIN through the twenty-first connection line L21 located on the fourth conductive layer, and the twenty-first connection line L21 is respectively connected to the first electrode of the eighth transistor T8 and the start signal line EIN, thereby realizing the first electrode of the eighth transistor T8 accessing the start signal through the twenty-first connection line L21. The second electrode of the eighth transistor T8 is sequentially connected to the gate of the seventh transistor T7 through the twenty-second connection line L22 located on the fourth conductive layer, the twenty-third connection line L23 located on the fourth conductive layer, and the twenty-fourth connection line L24 located on the third conductive layer. Specifically, the second electrode of the eighth transistor T8 is overlapped with one end of the twenty-second connection line L22, the other end of the twenty-second connection line L22 is overlapped with the twenty-third connection line L23, the twenty-third connection line L23 is connected to the twenty-fourth connection line L24 through the first type via 1 that penetrates from the fourth conductive layer to the third conductive layer, and the twenty-fourth connection line L24 is overlapped with the gate of the seventh transistor T7, specifically the top gate, and finally the second electrode of the eighth transistor T8 is connected to the gate of the seventh transistor T7, wherein the second electrode of the eighth transistor T8 serves as the output terminal N2 of the forward transmission unit 6. The gate of the eighth transistor T8 is specifically the bottom gate, which is overlapped with the fourth connection line L4, and the fourth connection line L4 is connected to the first clock signal line ECK1, and further connected to the first clock signal line ECK1 through the fourth connection line L4.

[0083] The first electrode of the ninth transistor T9 is connected to the gate of the seventh transistor T7, specifically the top gate, through the twenty-third connection line L23 and the fourteenth connection line L14 in sequence, and the first electrode of the ninth transistor T9 is directly connected to the twenty-third connection line L23, thereby realizing that the first electrode of the ninth transistor T9 is respectively connected to the gate of the seventh transistor T7 and the second electrode of the eighth transistor T8. The second electrode of the ninth transistor T9 is connected to the second gate of the first transistor T1 through the forty-third connection line L43 located in the fourth conductive layer and the twenty-fifth connection line L25 located in the third conductive layer in sequence. Specifically, the second electrode of the ninth transistor T9 is connected to the forty-third connection line L43, and the forty-third connection line L43 is connected to one end of the twenty-fifth connection line L25 through the first type via 1 that runs from the fourth conductive layer to the third conductive layer, and the other end of the twenty-fifth connection line L25 is connected to the third sub-portion 143 of the second gate of the first transistor T1, thereby realizing that the second electrode of the ninth transistor T9 is connected to the second gate of the first transistor T1. The gate of the ninth transistor T9 is specifically a bottom gate which is sequentially connected to the first power line VGH through the twenty-sixth connection line L26 and the fifth connection line L5 located in the second conductive layer. Specifically, the bottom gate of the ninth transistor T9 is directly connected to the twenty-sixth connection line L26, the twenty-sixth connection line L26 is connected to the fifth connection line L5 through the second type via 2 that penetrates from the fourth conductive layer to the second conductive layer, and the fifth connection line L5 is connected to the first power line VGH, and finally the gate of the ninth transistor T9 is connected to the first potential.

[0084] The first electrode of the tenth transistor T10 is connected to the second clock signal line ECK2 through the sixth connection line L6 and the seventh connection line L7 in sequence, so that the first electrode of the tenth transistor T10 is connected to the second clock signal. The second electrode of the tenth transistor T10 is connected to the first electrode plate of the second capacitor C2 through the twenty-seventh connection line L27 located in the fourth conductive layer. Specifically, the twenty-seventh connection line L27 is directly overlapped with the second electrode of the tenth transistor T10, and the twenty-seventh connection line L27 is connected to the first electrode plate of the second capacitor C2 through the second type of via 2 that runs through the fourth conductive layer to the first conductive layer, so that the second electrode of the tenth transistor T10 is connected to the first electrode plate of the second capacitor C2. The gate of the tenth transistor T10 is connected to the second electrode plate of the second capacitor C2 through the twenty-eighth connection line L28 located in the second conductive layer. Specifically, the bottom gate of the tenth transistor T10 is directly overlapped with the twenty-eighth connection line L28, and the twenty-eighth connection line L28 is overlapped with the second electrode plate of the second capacitor C2, so as to realize the connection between the gate of the tenth transistor T10 and the second electrode plate of the second capacitor C2.

[0085] The first electrode of the eleventh transistor T11 is connected to the second gate of the first transistor T1 through the forty-third connection line L43 and the twenty-fifth connection line L25 in sequence, the first electrode of the eleventh transistor T11 is directly connected to the forty-third connection line L43, and the forty-third connection line L43 is connected to the twenty-fifth connection line L25, and the twenty-fifth connection line L25 is connected to the second gate of the first transistor T1, and finally the first electrode of the eleventh transistor T11 is connected to the second gate of the first transistor T1. The second electrode of the eleventh transistor T11 is connected to the second plate of the second capacitor C2 through the twenty-ninth connection line L29 located on the fourth conductive layer and the thirtieth connection line L30 located on the fourth conductive layer in sequence, specifically, the second electrode of the eleventh transistor T11 is connected to the twenty-ninth connection line L29, and the twenty-ninth connection line L29 is connected to one end of the thirtieth connection line L30, and the other end of the thirtieth connection line L30 is connected to the second plate of the second capacitor C2 through the second type of via that runs through the fourth conductive layer to the second conductive layer, and finally the second electrode of the eleventh transistor T11 is connected to the second plate of the second capacitor C2. The gate of the eleventh transistor T11, specifically the bottom gate, is respectively connected to the gate of the tenth transistor T10, specifically the bottom gate, and the second plate of the second capacitor C2 through the twenty-eighth connecting line L28. The twenty-eighth connecting line L28 is respectively connected to the gate of the eleventh transistor T11, the gate of the tenth transistor T10, and the second plate of the second capacitor C2.

[0086] The first electrode of the twelfth transistor T12 is directly connected to the start signal line EIN by means of a lap connection, the second electrode of the twelfth transistor T12 is connected to the first electrode of the thirteenth transistor T13 by means of a thirty-first connection line L31 located in the fourth conductive layer, and the thirty-first connection line L31 is respectively lapped with the second electrode of the twelfth transistor T12 and the first electrode of the thirteenth transistor T13. The gate of the twelfth transistor T12 is connected to the first clock signal line ECK1 by means of a fourth connection line L4. Specifically, the gate of the twelfth transistor T12 is directly lapped with the fourth connection line L4, and the fourth connection line L4 is connected to the first clock signal line ECK1 by means of a second type via 2, and finally the gate of the twelfth transistor T12 is connected to the first clock signal.

[0087] The second electrode of the thirteenth transistor T13 is connected to the second electrode plate of the second capacitor C2 through the thirty-second connection line L32 located on the fourth conductive layer and the thirty-third connection line L33 located on the second conductive layer. Specifically, the second electrode of the thirteenth transistor T13 is directly connected to the thirty-second connection line L32, the thirty-second connection line L32 is connected to the thirty-third connection line L33 through the second type via 2 that runs from the fourth conductive layer to the second conductive layer, and the thirty-third connection line L33 is connected to the second electrode plate of the second capacitor C2, and finally the thirteenth transistor T13 is connected to the second electrode plate of the second capacitor C2. The gate of the thirteenth transistor T13 is specifically the bottom gate, which is connected to the first power line VGH through the twenty-sixth connection line L26 and the fifth connection line L5.

[0088] The first electrode of the fourteenth transistor T14 is connected to the first electrode plate of the third capacitor C3 through the eighteenth connection line L18 and the forty-first connection line L41 in sequence. Specifically, the first electrode of the fourteenth transistor T14 is directly connected to the eighteenth connection line L18, the eighteenth connection line L18 is connected to the forty-first connection line L41 through the second type via 2, the forty-first connection line L41 is connected to the first electrode plate of the third capacitor C1, and the first electrode plate of the third capacitor C3 is connected to the third power line VGL, so that the first electrode of the fourteenth transistor T14 is finally connected to the third power line VGL. The second electrode of the fourteenth transistor T14 is connected to the first electrode plate of the second capacitor C2 through the thirty-fourth connection line L34 located on the fourth conductive layer, the thirty-fifth connection line L35 located on the second conductive layer, and the twenty-seventh connection line L27 in sequence. Specifically, the second electrode of the fourteenth transistor T14 is overlapped with one end of the thirty-fourth connection line L34, the other end of the thirty-fourth connection line L34 is connected to the thirty-fifth connection line L35 through the second type via 2, the thirty-fifth connection line L35 is connected to the twenty-seventh connection line L27 through the second type via 2, and the twenty-seventh connection line L27 is connected to the first electrode plate of the second capacitor C2, and finally the second electrode of the fourteenth transistor T14 is connected to the first electrode plate of the second capacitor C2. The gate of the fourteenth transistor T14 is connected to the seventh sub-portion 147 of the second gate of the fourth transistor T4 through the twelfth connection line L12.

[0089] Fig.10 A cross-sectional view of another display panel provided by an embodiment of the present invention, Fig.10 For along Figure 6 Cross-section of BB', see Figure 6 and Fig.10The second transistor T2 is a dual-gate transistor, the bottom gate is located in the second conductive layer 12, the top gate is located in the third conductive layer 14, the active layer 13 is located between the second conductive layer 12 and the third conductive layer 14, the source and drain of the second transistor T2 are both located in the fourth conductive layer 15, the source (first electrode) of the second transistor T2 is connected to the active layer 13 through a first type via 1 that penetrates from the fourth conductive layer 15 to the third conductive layer 14, and the drain (second electrode) of the second transistor T2 is connected to the active layer 13 through a first type via 1 that penetrates from the fourth conductive layer to the third conductive layer 14. The second electrode of the second transistor T2 is also connected to the active layer 13 through a second type via 2 that penetrates from the fourth conductive layer 15 to the second conductive layer 12. Figure 7 The thirteenth connecting line L13 shown in FIG.

[0090] refer to Figure 5 and Figure 6 Optionally, the fourth conductive layer includes a routing setting area, the routing setting area includes a first power line VGH, a start signal line EIN, a first clock signal line ECK1, and a second clock signal line ECK2, the first power line VGH, the start signal line EIN, the first clock signal line ECK1, and the second clock signal line ECK2 all extend along the second direction Y and are arranged along the first direction X.

[0091] The second transistor T2, the third transistor T3, the fifth transistor T5 to the fourteenth transistor T14 all include active regions located in the active layer, and the active regions of the second transistor T2, the third transistor T3, the fifth transistor T5 to the fourteenth transistor T14 are all located between the first transistor active region and the wiring setting region. Among them, the active regions of the third transistor T3, the fifth transistor T5, the ninth transistor T9, the eleventh transistor T11, and the thirteenth transistor T13 all extend along the first direction X, and the active regions of the second transistor T2, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12, and the fourteenth transistor T14 all extend along the second direction Y. Among them, the twelfth transistor T12 and the eighth transistor T8 share a source region and a drain region, and along the second direction Y, the length of the active regions of the two are the same. In order to save the area of ​​the first capacitor C1, the first capacitor C1 includes a first capacitor sub-portion and a second capacitor sub-portion, the orthographic projection of the first capacitor sub-portion on the substrate is located between the orthographic projection of the tenth transistor T10 on the substrate and the orthographic projection of the second transistor T2 on the substrate, and the orthographic projection of the second capacitor sub-portion on the substrate is located between the orthographic projection of the third transistor T3 on the substrate and the orthographic projection of the first transistor T1 on the substrate.

[0092] The first transistor T1 and the fourth transistor T4 are both located on one side of the wiring arrangement area close to the display area;

[0093] The sixth transistor T6 , the eighth transistor T8 , and the twelfth transistor T12 are all located between the first transistor T1 or the fourth transistor T4 and the wiring arrangement area.

[0094] Since the first transistor T1 and the fourth transistor T4 are output transistors, in order to drive the scanning line to jump quickly, their width-to-length ratio is relatively large and they are arranged on the side closer to the display area. The sixth transistor T6, the eighth transistor T8 and the twelfth transistor T12 all need to be connected to the start signal, so compared with the first transistor T1 and the fourth transistor T4, they need to be arranged at a position closer to the wiring setting area.

[0095] Optionally, the sixth transistor T6 and the eighth transistor T8 are arranged along the second direction Y, and the twelfth transistor T12 and the eighth transistor T8 are arranged along the first direction X;

[0096] Along the first direction X, the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are all located between the eighth transistor T8 and the first transistor T1. And along the first direction X, the first capacitor C1 and the third capacitor C3 are all located on the side of the second capacitor C2 or the fourth capacitor C4 close to the display area. Because the first capacitor C1 needs to be connected to the first transistor T1 and the third capacitor C3 needs to be connected to the fourth transistor T4, the first capacitor C1 and the third capacitor C3 also need to be set near the display area, that is, near the first transistor T1 and the fourth transistor T4, so as to make the layout better. In which, in this embodiment, the display panel includes a gate driving circuit, the gate driving circuit includes a plurality of cascade-connected shift registers, each stage of the shift register includes the light-emitting control circuit in the above-mentioned embodiment, and the odd-numbered shift registers are connected to the first clock signal line ECK1 and the second clock signal line ECK2, and the even-numbered shift registers are connected to the third clock signal line ECK3 for transmitting the third clock signal and the fourth clock signal line ECK2 for transmitting the fourth clock signal, wherein the third clock signal is the same as the first clock signal ECK1, and the fourth clock signal is the same as the second clock signal ECK2.

[0097] This embodiment adopts Figure 5 The light-emitting control circuit prepared by the layout shown in the figure outputs the light-emitting control signal and conducts an experiment. Fig.11 A signal waveform diagram of a display panel provided by an embodiment of the present invention, comprising Fig.11 It can be seen that the light control signal is a shifted waveform of the start signal, and the time difference of the shift is equal to the phase difference between the second clock signal and the first clock signal. Fig.11 It can be seen that during the high level period of the light emitting control signal EM output by the existing n-type 9T3C light emitting control circuit, the waveform of the signal fluctuates greatly and jumps to a low level relatively slowly. Figure 5During the high level period of the light emitting control signal EM' output by the light emitting control circuit prepared in the middle layout, the waveform has almost no fluctuation, and the jump to the low level is relatively fast. Since the capacitor size of the circuit layout in this embodiment is set within a certain range, and the layout of the transistor conforms to the input and output directions, and the influence of the transistor size design on the characteristics is considered, therefore, the light emitting control circuit in this embodiment can enhance the speed of the light emitting control signal to jump down, and the signal is more stable and reliable.

[0098] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0099] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: substrate; A plurality of conductive layers stacked on one side of the substrate, the plurality of conductive layers comprising a first conductive layer and a second conductive layer, wherein the second conductive layer is located on a side of the first conductive layer away from the substrate; an active layer, the active layer being located on a side of the second conductive layer away from the substrate; The active layer and the multi-layer conductive layer constitute at least one light-emitting control circuit, the light-emitting control circuit comprises a first output module, the first output module comprises a first transistor and a first capacitor, the first electrode plate of the first capacitor is located in the first conductive layer, and the second electrode plate of the first capacitor is located in the second conductive layer; The first gate of the first transistor is located in the second conductive layer, and the second plate of the first capacitor is connected to the first gate of the first transistor; The ratio of the first area to the second area is between 0.2 and 1.0; wherein the first area is an overlapping area of ​​an orthographic projection of the first plate of the first capacitor on the substrate and an overlapping area of ​​an orthographic projection of the second plate of the first capacitor on the substrate, and the second area is an overlapping area of ​​an orthographic projection of the active layer on the substrate and an overlapping area of ​​an orthographic projection of the first gate of the first transistor on the substrate.

2. The display panel according to claim 1, characterized in that: The first transistor is used to transmit the first potential to the output end of the light emitting control circuit; The multi-layer conductive layer further includes a third conductive layer and a fourth conductive layer, wherein the third conductive layer is located on a side of the active layer away from the substrate, the fourth conductive layer is located on a side of the third conductive layer away from the substrate, and the fourth conductive layer includes a first clock signal line for transmitting a first clock signal and a second power supply line for transmitting a second potential, wherein the second potential is less than the first potential; The first output module further includes a second transistor, a first electrode of the second transistor is connected to the second power line, a second electrode of the second transistor is connected to the second plate of the first capacitor via a first connecting line located on the fourth conductive layer, and a gate of the second transistor is connected to the first clock signal line via a second connecting line located on the fourth conductive layer, a third connecting line located on the second conductive layer, and a fourth connecting line located on the second conductive layer in sequence; Preferably, the second electrode of the second transistor is connected to the first end of the first connecting line, and the second electrode plate of the first capacitor is connected to the second end of the first connecting line through a second type via.

3. The display panel according to claim 2, characterized in that: The light emitting control circuit further comprises a first output control module, wherein the first output control module is connected to the second gate of the first transistor; The second gate of the first transistor is located in the third conductive layer, and an orthographic projection of the first gate of the first transistor on the substrate at least partially overlaps with an orthographic projection of the second gate of the first transistor on the substrate; Preferably, an orthographic projection of the first gate of the first transistor on the substrate covers an orthographic projection of the second gate of the first transistor on the substrate.

4. The display panel according to claim 3, characterized in that: The first gate of the first transistor and the second gate of the first transistor each include a first sub-portion, a second sub-portion and a third sub-portion connected in sequence, the first sub-portion and the third sub-portion extend along a first direction, the second sub-portion extends along a second direction, the first sub-portion and the third sub-portion are arranged along the second direction, the first direction and the second direction intersect, and the third sub-portion of the first gate of the first transistor is connected to the second plate of the first capacitor; Preferably, the fourth conductive layer includes a first power line for transmitting a first potential, and also includes a first source-drain portion, a second source-drain portion and a third source-drain portion, all extending along the first direction, and a fourth source-drain portion extending along the second direction, the first source-drain portion, the second source-drain portion and the third source-drain portion are sequentially arranged along the second direction, the first sub-portion is located between the first source-drain portion and the second source-drain portion, the third sub-portion is located between the second source-drain portion and the third source-drain portion, the first source-drain portion and the third source-drain portion are both connected to the fourth source-drain portion, and the second source-drain portion is connected to the first power line via a fifth connecting line located in the fourth conductive layer; Preferably, the orthographic projection of the first sub-portion of the first gate of the first transistor on the substrate covers the orthographic projection of the first sub-portion of the second gate of the first transistor on the substrate, the orthographic projection of the second sub-portion of the first gate of the first transistor on the substrate covers the orthographic projection of the second sub-portion of the second gate of the first transistor on the substrate, and the orthographic projection of the third sub-portion of the first gate of the first transistor on the substrate covers the orthographic projection of the third sub-portion of the second gate of the first transistor on the substrate; Preferably, the length of the first sub-portion of the first gate of the first transistor along the first direction exceeds the length of the first sub-portion of the second gate of the first transistor along the first direction by a first preset length, and / or the length of the first sub-portion of the first gate of the first transistor along the second direction exceeds the length of the first sub-portion of the second gate of the first transistor along the second direction by a second preset length, and / or the length of the second sub-portion of the first gate of the first transistor along the first direction exceeds the length of the second sub-portion of the second gate of the first transistor along the first direction by a third preset length, and / or the length of the second sub-portion of the first gate of the first transistor along the second direction exceeds the length of the second sub-portion of the second gate of the first transistor along the second direction by a fourth preset length, and / or the length of the third sub-portion of the first gate of the first transistor along the first direction exceeds the length of the third sub-portion of the second gate of the first transistor along the first direction by a fifth preset length, and / or the length of the third sub-portion of the first gate of the first transistor along the second direction exceeds the length of the third sub-portion of the second gate of the first transistor along the second direction by a sixth preset length; Preferably, the first preset length, the second preset length, the third preset length, the fourth preset length, the fifth preset length and the sixth preset length are all greater than or equal to 1 micron and less than or equal to 3 microns; Preferably, along the first direction, the lengths of the first sub-portion and the third sub-portion are equal, and along the second direction, the lengths of the first sub-portion and the third sub-portion are equal; A length of the first sub-portion along the first direction is greater than a length of the first sub-portion along the second direction.

5. The display panel according to claim 4, characterized in that: The first output control module includes a forward transmission unit and a gate control unit, the output end of the forward transmission unit is connected to the second gate of the first transistor, and is used to transmit a start signal to the second gate of the first transistor, the gate control unit is connected to the second gate of the first transistor, and the gate control unit includes a second capacitor, and is used to increase the potential of the second gate of the first transistor through the coupling effect of the second capacitor; The first electrode plate of the second capacitor is located on the first conductive layer, and the second electrode plate of the second capacitor is located on the second conductive layer; The difference between the area of ​​the second capacitor and the first area is less than a preset threshold; wherein the area of ​​the second capacitor is the area of ​​the overlapping portion of the orthographic projection of the first electrode plate of the second capacitor on the substrate and the orthographic projection of the second electrode plate of the second capacitor on the substrate; Preferably, the first output module also includes a third transistor, the fourth conductive layer includes a second clock signal line for transmitting a second clock signal, the first electrode of the third transistor is connected to the second clock signal line via a sixth connecting line located on the fourth conductive layer and a seventh connecting line located on the first conductive layer in sequence, the second electrode of the third transistor is connected to the first electrode plate of the first capacitor through a second type of via, and the gate of the third transistor is connected to the output end of the forward transmission unit via an eighth connecting line located on the fourth conductive layer, a thirty-seventh connecting line located on the second conductive layer, and a ninth connecting line located on the second conductive layer in sequence.

6. The display panel according to claim 5, characterized in that: The light emitting control circuit further includes a second output module, the second output module includes a fourth transistor, the fourth transistor is used to output a third potential to an output end of the light emitting control circuit, the third potential is greater than the second potential, and the first potential is greater than the third potential; The first gate of the fourth transistor is located in the second conductive layer, and the first gate of the fourth transistor is connected to the second power line through a thirty-eighth connecting line; Preferably, the second gate of the fourth transistor is located in the third conductive layer; Preferably, the first gate and the second gate of the fourth transistor each include a fourth sub-portion, a fifth sub-portion, a sixth sub-portion and a seventh sub-portion, the fourth sub-portion, the fifth sub-portion and the sixth sub-portion each extend along the first direction, the seventh sub-portion extends along the second direction, the fourth sub-portion, the fifth sub-portion and the sixth sub-portion are sequentially arranged along the second direction, the first direction and the second direction intersect, the fourth sub-portion, the fifth sub-portion and the sixth sub-portion are all connected to the seventh sub-portion, and the sixth sub-portion is located on a side of the fifth sub-portion close to the first sub-portion; The fourth sub-portion of the first gate of the fourth transistor is connected to the second power line through the thirty-eighth connection line; The fourth conductive layer includes a fifth source drain portion, a sixth source drain portion, a seventh source drain portion and an eighth source drain portion sequentially arranged along the second direction, and a ninth source drain portion and a tenth source drain portion extending along the second direction, the fifth source drain portion, the sixth source drain portion, the seventh source drain portion and the eighth source drain portion are all located between an extension line of the ninth source drain portion along the second direction and an extension line of the tenth source drain portion along the second direction, the fifth source drain portion and the seventh source drain portion are both connected to the ninth source drain portion, and the sixth source drain portion and the eighth source drain portion are both connected to the tenth source drain portion; The fourth sub-portion is located between the fifth source-drain portion and the sixth source-drain portion, the fifth sub-portion is located between the sixth source-drain portion and the seventh source-drain portion, and the sixth sub-portion is located between the seventh source-drain portion and the eighth source-drain portion; The fourth conductive layer further includes a third power line for transmitting the third potential, the third power line is connected to the seventh source-drain portion via a tenth connecting line located in the first conductive layer, and the tenth source-drain portion is connected to the output end of the light emitting control circuit; Preferably, the length of the fourth sub-portion of the first gate of the fourth transistor along the first direction exceeds the length of the fourth sub-portion of the second gate of the fourth transistor along the first direction by a first preset length, and / or, the length of the fourth sub-portion of the first gate of the fourth transistor along the second direction exceeds the length of the fourth sub-portion of the second gate of the fourth transistor along the second direction by a second preset length, and / or, the length of the fifth sub-portion of the first gate of the fourth transistor along the first direction exceeds the length of the fifth sub-portion of the second gate of the fourth transistor along the first direction by a third preset length, and / or, the length of the fifth sub-portion of the first gate of the fourth transistor along the second direction exceeds the length of the fifth sub-portion of the second gate of the fourth transistor along the second direction by a fourth preset length, and / or, the length of the sixth sub-portion of the first gate of the fourth transistor along the first direction exceeds the length of the sixth sub-portion of the second gate of the fourth transistor along the first direction by a fifth preset length, and / or, the length of the sixth sub-portion of the first gate of the fourth transistor along the second direction exceeds the length of the sixth sub-portion of the second gate of the fourth transistor along the second direction by a sixth preset length; Preferably, the first preset length, the second preset length, the third preset length, the fourth preset length, the fifth preset length and the sixth preset length are all greater than or equal to 1 micron and less than or equal to 3 microns; Preferably, the second output module further includes a third capacitor, wherein a first electrode plate of the third capacitor is located on the first conductive layer, and a second electrode plate of the third capacitor is located on the second conductive layer; The first electrode plate of the third capacitor is connected to the ninth source-drain portion through an eleventh connecting line located in the fourth conductive layer, and the second electrode plate of the third capacitor is connected to the fourth sub-portion of the second gate of the fourth transistor through a twelfth connecting line located in the third conductive layer; Preferably, the area of ​​the third capacitor is smaller than the first area, and the area of ​​the third capacitor is the overlapping area of ​​the orthographic projection of the first electrode plate of the third capacitor on the substrate and the orthographic projection of the second electrode plate of the third capacitor on the substrate; Preferably, a ratio of an area of ​​the third capacitor to an area of ​​the first capacitor is greater than or equal to 0.4 and less than or equal to 0.6; Preferably, the first electrode of the second transistor is connected to the seventh sub-portion of the first gate of the fourth transistor through a thirteenth connecting line located in the second conductive layer.

7. The display panel according to claim 6, characterized in that: The light emitting control circuit further comprises a second output control module, wherein the second output control module is used to transmit an inverted signal of the start signal to the second gate of the fourth transistor; The second output control module includes a fifth transistor and a fourth capacitor, wherein a first plate of the fourth capacitor is located on the first conductive layer, a second plate of the fourth capacitor is located on the second conductive layer, the first plate of the fourth capacitor is connected to the gate of the fifth transistor, and the second plate of the fourth capacitor is connected to the first clock signal line through the third connecting line and the fourth connecting line; The first electrode of the fifth transistor is connected to the second electrode plate of the fourth capacitor through the seventeenth connecting line located on the second conductive layer, and the second electrode of the fifth transistor is connected to the fourth sub-portion of the second gate of the fourth transistor through the fourteenth connecting line located on the fourth conductive layer, the fifteenth connecting line located on the fourth conductive layer, the sixteenth connecting line located on the fourth conductive layer, and the twelfth connecting line in sequence; The area of ​​the fourth capacitor is smaller than the first area; the area of ​​the fourth capacitor is the overlapping area of ​​the orthographic projection of the first electrode plate of the fourth capacitor on the substrate and the orthographic projection of the second electrode plate of the fourth capacitor on the substrate; Preferably, a ratio of an area of ​​the fourth capacitor to the first area is greater than or equal to 0.5 and less than or equal to 0.

7.

8. The display panel according to claim 7, characterized in that: The fourth conductive layer includes a start signal line for transmitting a start signal, the second output control module also includes a sixth transistor, a first electrode of the sixth transistor is sequentially connected to the first electrode plate of the third capacitor through an eighteenth connection line located on the fourth conductive layer and a forty-first connection line located on the first conductive layer, a second electrode of the sixth transistor is sequentially connected to the first electrode plate of the fourth capacitor through a nineteenth connection line located on the fourth conductive layer and a forty-second connection line located on the first conductive layer, and a gate of the sixth transistor is connected to the start signal line through a twentieth connection line located on the fourth conductive layer; The channel length of the sixth transistor is greater than the channel length of each of the fifth transistor, the second transistor and the third transistor; Preferably, a channel length of the sixth transistor is greater than or equal to 6 microns and less than or equal to 8 microns.

9. The display panel according to claim 8, characterized in that: The second output control module further includes a seventh transistor, the forward transmission unit includes an eighth transistor, and the gate control unit includes a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor; The first electrode of the seventh transistor is connected to the first electrode plate of the third capacitor through the eighteenth connecting line and the forty-first connecting line in sequence, the second electrode of the seventh transistor is connected to the fourth sub-portion of the second gate of the fourth transistor through the fifteenth connecting line, the sixteenth connecting line and the twelfth connecting line in sequence, and the gate of the seventh transistor is connected to the gate of the third transistor T3 through the ninth connecting line and the eighth connecting line in sequence; The first electrode of the eighth transistor is connected to the start signal line through a twenty-first connection line located in the fourth conductive layer, the second electrode of the eighth transistor is connected to the gate of the seventh transistor through a twenty-second connection line located in the fourth conductive layer, a twenty-third connection line located in the fourth conductive layer, and a twenty-fourth connection line located in the third conductive layer in sequence, and the gate of the eighth transistor T8 is connected to the first clock signal line through the fourth connection line; The first electrode of the ninth transistor is connected to the twenty-third connecting line, the second electrode of the ninth transistor is connected to the second gate of the first transistor via the forty-third connecting line located on the fourth conductive layer and the twenty-fifth connecting line located on the third conductive layer in sequence, and the gate of the ninth transistor is connected to the first power line via the twenty-sixth connecting line located on the second conductive layer and the fifth connecting line in sequence; The first electrode of the tenth transistor is connected to the second clock signal line through the sixth connection line and the seventh connection line in sequence, the second electrode of the tenth transistor is connected to the first electrode plate of the second capacitor through the twenty-seventh connection line located on the fourth conductive layer, and the gate of the tenth transistor is connected to the second electrode plate of the second capacitor through the twenty-eighth connection line located on the second conductive layer; The first electrode of the eleventh transistor is connected to the second gate of the first transistor through the forty-third connecting line and the twenty-fifth connecting line in sequence, the second electrode of the eleventh transistor is connected to the second plate of the second capacitor through the twenty-ninth connecting line located on the fourth conductive layer and the thirtieth connecting line located on the fourth conductive layer in sequence, and the gate of the eleventh transistor is connected to the gate of the tenth transistor and the second plate of the second capacitor respectively through the twenty-eighth connecting line; A first electrode of the twelfth transistor is connected to the start signal line, a second electrode of the twelfth transistor is connected to a first electrode of the thirteenth transistor via a thirty-first connection line located in the fourth conductive layer, and a gate of the twelfth transistor is connected to the first clock signal line via the fourth connection line; The second electrode of the thirteenth transistor is connected to the second electrode plate of the second capacitor via the thirty-second connecting line located on the fourth conductive layer and the thirty-third connecting line located on the second conductive layer in sequence, and the gate of the thirteenth transistor is connected to the first power line via the twenty-sixth connecting line and the fifth connecting line; The first electrode of the fourteenth transistor is connected to the first electrode plate of the third capacitor through the eighteenth connecting line and the fourteenth connecting line in sequence, the second electrode of the fourteenth transistor is connected to the first electrode plate of the second capacitor through the thirty-fourth connecting line located on the fourth conductive layer, the thirty-fifth connecting line located on the second conductive layer and the twenty-seventh connecting line in sequence, and the gate of the fourteenth transistor is connected to the second gate of the fourth transistor through the twelfth connecting line.

10. The display panel according to claim 9, characterized in that: The fourth conductive layer includes a wiring arrangement area, the wiring arrangement area includes a first power line, a start signal line, a first clock signal line, and a second clock signal line, the first power line, the start signal line, the first clock signal line, and the second clock signal line all extend along the second direction and are arranged along the first direction; The first transistor and the fourth transistor are both located on a side of the wiring arrangement area close to the display area; The sixth transistor, the eighth transistor and the twelfth transistor are all located between the first transistor or the fourth transistor and the wiring setting area; Preferably, the sixth transistor and the eighth transistor are arranged along the second direction, and the twelfth transistor and the eighth transistor are arranged along the first direction; Along the first direction, the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are all located between the eighth transistor and the first transistor, and along the first direction, the first capacitor and the second capacitor are both located on a side of the third capacitor or the fourth capacitor close to the display area.

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