A Test Method and Circuit for Design for Testability Based on Delay Line

Abstract

The present application discloses a test method and circuit for design for testability based on a delay line. The method includes: obtaining a test point provided at an input end of the delay line and an observation point provided at an output end thereof; inserting a first control logic designed based on the test point and a second control logic designed based on the observation point into a preset design for testability test to obtain test vectors according to the design for testability test; testing the delay line based on the test vectors to obtain a test result, where the test result is used to characterize the damage condition of the delay line. The technical solution of the present application can simplify the operation process of delay line testing through automated control logic, making the testing of the delay line more convenient and easy to operate, thereby reducing the labor cost.

Description

Technical Field

[0001] This application relates to the technical field of chip circuit design, and in particular, to a test method and circuit for design for testability based on a delay line. Background Art

[0002] DDR (Double Data Rate) PHY (physical interface) adjusts the delay line at the sending end so that the DRAM (dynamic random-access memory) particles can successfully sample the control signal and data signal at the receiving end; correspondingly, at the DDR PHY end, by adjusting the delay line at the internal receiving end, the DDR PHY can successfully sample the output signal of the DRAM particles.

[0003] DFT (Design for Testability) is used to test the quality of the chip to see if there are any problems with the chip being damaged due to the physical manufacturing process during the production process.

[0004] Generally, DFT testing is performed on the delay line to determine whether the chip is damaged based on the test results. However, the conventional delay line test process is relatively cumbersome and the labor cost is relatively high. Summary of the Invention

[0005] To solve the above technical problems, embodiments of the present application provide a test method and circuit for design for testability based on a delay line.

[0006] According to one aspect of the embodiments of the present application, a test method for design for testability based on a delay line is provided. The method includes: obtaining a test point provided at the input end of the delay line and an observation point provided at the output end; inserting a first control logic designed based on the test point and a second control logic designed based on the observation point into a preset design for testability test to obtain test vectors according to the design for testability test; testing the delay line based on the test vectors to obtain test results, where the test results are used to characterize the damage condition of the delay line.

[0007] In some embodiments of the present application, based on the above technical solution, the test vectors include test stimuli and expected results. Testing the delay line based on the test vectors to obtain test results includes: inputting the test stimuli into the delay line so that the delay line outputs an excitation result according to the test stimuli; comparing the excitation result with the expected result to obtain the damage condition of the delay line according to the comparison result.

[0008] In some embodiments of the present application, based on the above technical solutions, the step of inputting the test stimulus into the delay line so that the delay line outputs an excitation result according to the test stimulus includes: correlating the test stimulus with the clock signal of the test point to obtain a test clock for characterizing the test stimulus; inputting the test clock corresponding to the test stimulus into the delay line so that the delay line outputs an excitation result according to the test clock.

[0009] In some embodiments of the present application, based on the above technical solutions, there are multiple test points. The step of comparing the excitation result with the expected result to obtain the damage condition of the delay line according to the comparison result includes: obtaining the comparison results of the excitation results and the expected results corresponding to all test points on the delay line; if the comparison results of the excitation results and the expected results corresponding to all test points indicate normal, obtaining a test result that the delay line is not damaged; if at least one of the comparison results of the excitation results and the expected results corresponding to all test points indicates abnormal, obtaining a test result that the delay line is damaged.

[0010] In some embodiments of the present application, based on the above technical solutions, the method further includes:

[0011] When generating test vectors according to the design for testability (DFT) test, generating a coverage rate of test points on the delay line according to the test content of the DFT test, and increasing the number of test points when the coverage rate is less than a preset threshold.

[0012] In some embodiments of the present application, based on the above technical solutions, there are multiple test points. The method includes: determining whether the first control logic of all test points and the second control logic of all observation points are successfully inserted according to the coverage rate; if not, reinserting the first control logic of the test points and the second control logic of the observation points until the first control logic of all test points and the second control logic of all observation points are successfully inserted.

[0013] In some embodiments of the present application, based on the above technical solutions, the method further includes: obtaining a selection signal on the test point; when the selection signal is in the DFT test mode, performing a DFT test on the corresponding test point.

[0014] According to one aspect of the embodiments of the present application, there is provided a design for testability (DFT) test circuit based on a delay line, including: a delay line for delaying the transmission time of an electrical signal; a test point provided at an input end of the delay line for testing whether the delay line is damaged; and an observation point provided at an output end of the delay line for obtaining a test result of whether the delay line is damaged.

[0015] In some embodiments of the present application, based on the above technical solutions, the test point includes: a test data selector, an output end of the test data selector is connected to an input end of the delay line; a first trigger, an output end of the first trigger is connected to an input end of the test data selector; wherein, the input ends of the test data selector are respectively used for obtaining a selection signal, a preset input clock signal and an output signal of the first trigger at the test point; the input ends of the first trigger are respectively used for obtaining a ground signal and a test clock signal of the test point.

[0016] In some embodiments of the present application, based on the above technical solutions, the observation point includes: a second trigger, an input end of the second trigger is connected to an output end of the delay line; wherein, the input ends of the second trigger are respectively used for obtaining the test clock signal of the test point and the output signal of the delay line.

[0017] In the technical solutions of the embodiments of the present application, the following beneficial effects can be brought at least by the above invention content:

[0018] The technical solution of the present application inserts the generation process of test vectors into the logic program of the design for testability test, so as to improve the coherence of the generation and use of test vectors through an automated control process. Based on the automated control logic of the delay line damage test, the operation process of the delay line damage test is simplified, making the damage test of the delay line more convenient and easy to operate, thereby reducing the labor cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. In the drawings:

[0020] Figure 1 It is a schematic block diagram of the overall circuit of a level converter shown in an exemplary embodiment of the present application.

[0021] Figure 2 It is a schematic diagram of the structure of a design for testability test circuit of a delay line shown in an exemplary embodiment of the present application.

[0022] Figure 3 It is a flowchart of a method for design for testability test based on a delay line shown in an exemplary embodiment of the present application.

[0023] Figure 4 It is a flowchart of a detection method for the damage situation of a delay line shown in an exemplary embodiment of the present application.

[0024] Figure 5 The flowchart shows the process of obtaining the excitation result for an exemplary embodiment of the present application.

[0025] Figure 6 The flowchart shows the detection method for the damaged situation of the delay line for another exemplary embodiment of the present application.

[0026] Figure 7 The flowchart shows the process of inserting the first control logic and the second control logic into the design for testability (DFT) test for an exemplary embodiment of the present application.

[0027] Figure 8 The flowchart shows the process of detecting the delay line for an exemplary embodiment of the present application. Detailed implementation manners

[0028] To make the purpose and implementation manners of the present application clearer, the following will clearly and completely describe the exemplary implementation manners of the present application in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only a part of the embodiments of the present application, rather than all of the embodiments.

[0029] It should be noted that the brief description of the terms in the present application is only for facilitating the understanding of the subsequent described implementation manners, rather than intending to limit the implementation manners of the present application. Unless otherwise specified, these terms should be understood in their ordinary and common meanings.

[0030] The terms "first", "second", "third", etc. in the specification, claims and the above drawings of the present application are used to distinguish similar or like objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that such terms can be interchanged under appropriate circumstances.

[0031] The terms "comprising" and "having" and any variations thereof are intended to cover but not exclude inclusion. For example, a product or device comprising a series of components does not necessarily have to be limited to all the clearly listed components, but may include other components not clearly listed or inherent to these products or devices.

[0032] It should be noted that: "a plurality of" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0033] During the chip production process of the prior art, due to the physical manufacturing process, some physical damages may be caused to the chip. In order to test whether similar damage occurs during the chip production process, the prior art tests the produced chips through the DFT test method. The main purpose of the DFT test is to provide an effective method to detect and diagnose faults in integrated circuits to ensure the normal operation and reliability of the circuit. By considering the test requirements at the design stage and taking corresponding measures, high-quality testing can be ensured during the circuit manufacturing process, thereby improving the quality and competitiveness of the product and reducing some unnecessary cost losses during the chip production process.

[0034] Illustratively, the DFT test principle mainly includes the following aspects:

[0035] Insertion of test points: A certain number of test points are reasonably placed in the circuit design so that the circuit can be comprehensively covered during the test. The insertion of test points needs to be determined according to the circuit structure and design requirements to improve the test coverage and efficiency as much as possible. And this process often requires some experienced staff to set according to experience.

[0036] Generation of test vectors: According to the positions of the test points and the functional requirements of the circuit, a series of test data that can effectively detect circuit faults are generated. These test vectors are used to simulate various situations in the actual working environment to detect the response and performance of the circuit under various conditions.

[0037] Application of test sequences: The generated test vectors are applied to the circuit in a certain order and timing to trigger possible faults and detect and diagnose the positions and types of faults. The application of test sequences needs to consider the clock frequency and data transmission speed of the circuit to ensure the correctness and stability of the test.

[0038] Design of fault models: For various possible fault modes, corresponding fault models are designed. These models are used to simulate fault situations so that faults can be accurately detected and located during the test.

[0039] Based on the above content, the present application designs a test circuit for design for testability based on a delay line. The test circuit may include:

[0040] A delay line for delaying the transmission time of an electrical signal;

[0041] A test point provided at the input end of the delay line for testing whether the delay line is damaged;

[0042] An observation point provided at the output end of the delay line for obtaining the test result of whether the delay line is damaged.

[0043] Among them, the delay line can be an electronic component or device, and its main function is to delay an electrical signal or an optical signal for a period of time.

[0044] Specifically, the delay line plays a crucial role in the DDR memory interface. The delay line of the DDR PHY is a physical structure used to adjust the signal transmission delay, and it is usually located inside the DDR PHY (physical layer). The main function of the delay line is to ensure that the clock signal and the data signal can maintain the correct timing relationship during the transmission process, so as to achieve accurate sampling and transmission of data.

[0045] Figure 1 The structural relationship diagram of the delay line on the DDR PHY shown in the exemplary embodiment of the present application is as follows Figure 1 As shown, delay lines are respectively arranged on the interfaces between the Dynamic Random Access Memory (DRAM) and the DDR PHY to ensure that the clock signal and the data signal can maintain the correct timing relationship during the transmission process.

[0046] In the DDR memory interface, data is sampled and transmitted through the clock edge. The DDR PHY ensures the accurate transmission of data by providing the alignment of the clock signal and the data signal. To achieve this goal, the DDR PHY synchronizes according to the edges of the clock signal and the data signal sent by the controller. When the clock edge arrives, the DDR PHY uses the delay line to adjust the transmission delay of the data signal to make it maintain the correct phase relationship with the clock signal, and then samples the data signal and transmits it to the memory.

[0047] Figure 2 The structural schematic diagram of the testability design test circuit of the delay line shown in the exemplary embodiment of the present application is as follows Figure 2 As shown, in the testability design test circuit of the delay line of the present application, the delay line can include multiple delay units and multiple data selectors. The multiple delay units are arranged in series, and each data selector is respectively connected to the input end of the delay unit, so that the multiple delay units and the multiple data selectors are arranged in one-to-one correspondence, so that the working state of the delay unit can be determined through the data selector. For example, the delay control is performed by the number of selected data selectors.

[0048] The present application sets test points at the input end of the delay line to test whether the delay line is damaged during the physical manufacturing process, and obtains the test result of whether the delay line is damaged through the observation point at the output end of the delay line.

[0049] In some embodiments of the present application, based on the above embodiments, the above test points can at least include:

[0050] A test data selector, the output end of the test data selector is connected to the input end of the delay line;

[0051] A first flip-flop, the output end of the first flip-flop is connected to the input end of the test data selector;

[0052] Among them, the input ends of the test data selector are respectively used to obtain the selection signal at the test point, the preset input clock signal and the output signal of the first flip-flop;

[0053] The input ends of the first flip-flop are respectively used to obtain the ground signal and the test clock signal at the test point.

[0054] Among them, the test data selector includes three input interfaces and one output interface. The first input interface of the test data selector is used to obtain the input clock signal, the second input interface of the test data selector is used to obtain the output signal of the first flip-flop, and the third input interface of the test data selector is used to obtain the selection signal at the test point.

[0055] Based on this, the test data selector determines whether to output the input clock signal or the output signal of the first flip-flop at the output end of the test data selector according to the selection signal input by the third input interface.

[0056] Input the test clock signal into the first flip-flop. Among them, the test clock signal can be used as the test clock signal at the test point, so that the first flip-flop inputs the output signal of the first flip-flop into the second input interface of the test data selector according to the test excitation.

[0057] Among them, the first flip-flop of the present application can select a DFF (bistable flip-flop), so that the first flip-flop can store the level state of the test clock signal and maintain this state at the output end until it receives the next trigger signal.

[0058] In some embodiments of the present application, based on the above embodiments, the above observation points may at least include:

[0059] A second flip-flop, the input end of the second flip-flop is connected to the output end of the delay line;

[0060] Among them, the input ends of the second flip-flop are respectively used to obtain the test clock signal at the test point and the output signal of the delay line.

[0061] Specifically, the second flip-flop of the present application can also select a DFF (bistable flip-flop), so that the second flip-flop can change the trigger state according to the output signal of the delay line, and thus can realize the signal detection function according to the rising edge or falling edge state of the second flip-flop.

[0062] The present application also designs a test method for testability design based on a delay line.Figure 3 The flowchart of the test method for the testability design based on a delay line is shown for an exemplary embodiment of the present application. As Figure 3 shown, the test method at least includes the following execution steps:

[0063] S300. Obtain a test point provided at the input end of the delay line and an observation point at the output end;

[0064] S310. Insert a first control logic designed based on the test point and a second control logic designed based on the observation point into a preset testability design test to obtain test vectors according to the testability design test;

[0065] S320. Test the delay line based on the test vectors to obtain a test result, and the test result is used to characterize the damage condition of the delay line.

[0066] Regarding the specific content of the first control logic, that is, in the program preset in the testability design test, control the input signals of different inputs of the electronic components in the test point to perform the test of the test point according to the corresponding input signals. For example, when controlling the third input port of the test data selector to input an input signal for characterizing the execution of the delay line test, control the output end of the test data selector to output the signal of the output end of the first trigger.

[0067] The specific content of the second control logic is similar to the specific content of the first control logic. Similarly, in the program preset in the testability design test, control the input signals of different inputs of the electronic components in the observation point to perform the test of the test point according to the corresponding input signals. For example, take the output signal of the delay line as an input signal of the observation point. The second control logic can be characterized as obtaining the output signal of the observation point, that is, the output signal of the second trigger, and obtaining a judgment result on whether the delay line is damaged according to the output signal of the second trigger.

[0068] After inserting the first control logic and the second control logic into the preset testability design test, test vectors are obtained according to the specific test content. The test content includes the setting positions of the test point and the observation point, as well as the inputs and outputs of the electronic components, etc. For example, a DFT netlist is automatically generated according to the test content, and backend layout is performed, and a communication connection with the DFT tool is established in the program. The layout content is input into the preset DFT tool. For example, the DFT tool can be mentor (Mentor Graphics, Mingdao). According to the DFT tool, test vectors and a coverage report of the test point are calculated, and the test vectors and the coverage report of the test point are returned to the program through the communication connection.

[0069] Further, the delay line is tested according to the test vectors of the return program. Specifically, the test of the delay line can be performed on an ATE machine (Integrated Circuit Automatic Tester). Similar to the DFT tool, a communication connection with the ATE machine is established in the program. The delay line of the present application can obtain a test result according to the test vectors, and then transmit the test result and the test vectors to the ATE machine to obtain a judgment result on whether the delay line is damaged, and return the judgment result to the program through the communication connection.

[0070] In the above embodiment, the technical solution of the present application inserts the generation process of the test vectors into the logic program of the design for testability test, so as to improve the coherence of the generation and use of the test vectors through an automated control process. Based on the automated control logic of the delay line damage test, the operation process of the delay line damage test is simplified, making the damage test of the delay line more convenient and easy to operate, thereby reducing the labor cost.

[0071] In some embodiments of the present application, based on the above embodiments, the test vectors of the present application may include test stimuli and expected results.

[0072] Figure 4 It is a flowchart showing the detection method of the damage situation of the delay line for an exemplary embodiment of the present application. As Figure 4 shown, testing the delay line based on the test vectors to obtain a test result may at least include the following execution steps:

[0073] S400: Input the test stimuli into the delay line so that the delay line outputs an excitation result according to the test stimuli;

[0074] S410: Compare the excitation result with the expected result to obtain the damage situation of the delay line according to the comparison result.

[0075] Specifically, through the ATE machine in the above embodiment, the test stimuli in the test vectors are input into the delay line, so that after the excitation signal acts on the delay line, an excitation result is obtained. Then, based on the ATE machine, the excitation result is compared with the expected result in the test vectors, and it is determined whether the delay line is damaged according to the comparison result. Exemplarily, after the excitation signal acts on the delay line, if the delay line is normal, the value represented by the excitation result should be equal to the expected result. If the value represented by the obtained excitation result is not equal to the expected result, it indicates that the delay line may be damaged.

[0076] In some embodiments of the present application, based on the above embodiments, Figure 5 It is a flowchart showing the process of obtaining the excitation result for an exemplary embodiment of the present application. As Figure 5As shown in the figure, delaying the test stimulus input to the delay line so that the delay line outputs an excitation result according to the test stimulus may include at least the following steps:

[0077] S500. Corresponding the test stimulus with the clock signal at the test point to obtain a test clock for characterizing the test stimulus;

[0078] S510. Inputting the test clock corresponding to the test stimulus into the delay line so that the delay line outputs an excitation result according to the test clock.

[0079] Specifically, as Figure 2 shown in the figure, test_clk in the figure represents the test clock. In order to more fully disclose the test process of whether the delay line is damaged, the following description is made for the representation method of the test stimulus. The test stimulus of the present application can be represented by a clock signal. For example, if the test stimulus itself is a voltage signal or a current signal, it is converted into a representation by a clock signal through a preset conversion module. For example, when adjusting the test stimulus signal, by adjusting the corresponding clock signal, the clock signal is converted into a voltage signal or a current signal through the conversion module. Of course, only an exemplary description is made here and no specific limitation is imposed.

[0080] In the above embodiment, the purpose is to enable the test stimulus of the present application to be represented by a clock signal, so that the test clock characterized based on the clock signal is easier to adjust and control. Thus, the convenience of testing whether the delay line is damaged is improved.

[0081] In some embodiments of the present application, based on the above embodiments, Figure 6 The flowchart in the figure shows a detection method for the damage situation of the delay line in another exemplary embodiment of the present application. As Figure 6 shown in the figure, there can be multiple test points. Comparing the excitation result with the expected result to obtain the damage situation of the delay line according to the comparison result may include at least the following steps:

[0082] S600. Obtaining the comparison result between the excitation result corresponding to all test points on the delay line and the expected result;

[0083] S610. If the comparison results between the excitation results corresponding to all test points and the expected results all indicate normal, obtain the test result that the delay line is not damaged;

[0084] S620. If at least one of the comparison results between the excitation results corresponding to all test points and the expected results indicates abnormal, obtain the test result that the delay line is damaged.

[0085] Specifically, when there are multiple test points, the delay line is considered to have no physical damage only when the test results of all test points are normal. And if the test result of only one test point is abnormal, it is regarded that the delay line may have physical damage.

[0086] It should be noted that for multiple test points, they can respectively correspond to multiple different delay lines, or multiple test points can correspond to the same delay line.

[0087] In the above embodiment, when there are multiple test points, by ensuring that the test results of all test points are normal, it is reflected that the test result of the delay line is that the delay line has no physical damage, thereby improving the test accuracy of the delay line test result and reducing test errors.

[0088] In some embodiments of the present application, based on the above embodiment, for the test method of the testability design based on the delay line in the present application, at least the following steps can also be included:

[0089] When generating test vectors according to the testability design test, generate the coverage rate of the test points on the delay line according to the test content of the testability design test, and increase the number of test points when the coverage rate is less than the preset threshold.

[0090] Specifically, the coverage rate of the test points can be used to characterize the comprehensiveness of the delay line test. The more test points are distributed, the more detailed the test positions corresponding to the delay line are, and the higher the accuracy of the test result. However, in order to improve a certain production efficiency, the present application controls the coverage rate of the test points by setting a threshold.

[0091] In some embodiments of the present application, based on the above embodiment, Figure 7 The flowchart showing the insertion of the first control logic and the second control logic into the testability design test for the exemplary embodiment of the present application is as Figure 7 shown. When there are multiple test points, for the test method of the testability design based on the delay line in the present application, at least the following steps can also be included:

[0092] S700. Determine whether the first control logic of all test points and the second control logic of all observation points are inserted successfully according to the coverage rate;

[0093] S710. If not, re-insert the first control logic of the test points and the second control logic of the observation points until the first control logic of all test points and the second control logic of all observation points are inserted successfully.

[0094] Specifically, after determining multiple test points, the ratio of the set test points to the positions of all test points that can be set can be calculated. When this ratio is different from the coverage rate of the test points on the delay line generated according to the test content of the design for testability (DFT) test, it indicates that the first control logic of all test points and the second control logic of all observation points are not inserted successfully. Then, the first control logic of all test points and the second control logic of all observation points can be re-inserted through the program preset in this application, thereby improving the reliability of the test results.

[0095] In some embodiments of the present application, based on the above embodiments, Figure 8 is a flowchart showing the delay line detection process in an exemplary embodiment of the present application. As Figure 8 shown, for the DFT test method based on the delay line in the present application, at least the following steps may further be included:

[0096] S800. Obtain the selection signal at the test point;

[0097] S810. When the selection signal is the DFT test mode, perform the DFT test on the corresponding test point.

[0098] Specifically, as Figure 2 shown, in the figure, test_mode represents the selection signal corresponding to the mode. By inserting the first control logic of the test points on the delay line and the second control logic of the observation points into the preset DFT test in the present application, the smoothness of the delay line damage test is improved.

[0099] Exemplarily, when the delay line is in normal use, adjust the selection signal for selecting the mode set at the test point so that the test point exits the test mode to ensure the normal use of the delay line.

[0100] For another example, during the production process of the module corresponding to the delay line, it is necessary to detect whether the delay line is normal. At this time, adjust the selection signal for selecting the mode set at the test point so that the test point enters the test mode to detect the delay line.

[0101] For still another example, after the module corresponding to the delay line has been used for a period of time and certain faults occur in the corresponding module, it is necessary to detect whether the delay line is normal for troubleshooting. At this time, adjust the selection signal for selecting the mode set at the test point so that the test point enters the test mode to detect the delay line.

[0102] Based on this, in the above implementation manner, the setting of the selection signal at the test point can improve the convenience of detecting whether the delay line is damaged.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0104] For the sake of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussions are not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. According to the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are for the purpose of better explaining the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A test method for design for testability based on a delay line, characterized in that, The method includes: Obtaining a test point provided at the input end of the delay line and an observation point at the output end; Inserting a first control logic designed based on the test point and a second control logic designed based on the observation point into a preset test for design for testability to obtain test vectors according to the test for design for testability; the test vectors include test stimuli and expected results; Inputting the test stimuli into the delay line so that the delay line outputs an excitation result according to the test stimuli; comparing the excitation result with the expected result to obtain the damage condition of the delay line according to the comparison result; Wherein, obtaining the test vectors according to the test for design for testability includes: obtaining test vectors according to specific test contents, and the test contents include the set positions of the test point and the observation point, as well as the input and output of electronic components.

2. The test method for design for testability based on a delay line according to claim 1, wherein The inputting the test stimuli into the delay line so that the delay line outputs an excitation result according to the test stimuli includes: Corresponding the test stimuli with the clock signal of the test point to obtain a test clock for characterizing the test stimuli; Inputting the test clock corresponding to the test stimuli into the delay line so that the delay line outputs an excitation result according to the test clock.

3. The test method for design for testability based on a delay line according to claim 1, wherein There are multiple test points, and the comparing the excitation result with the expected result to obtain the damage condition of the delay line according to the comparison result includes: Obtaining the comparison results of the excitation results and the expected results corresponding to all the test points on the delay line; If the comparison results of the excitation results and the expected results corresponding to all the test points all indicate normal, obtaining a test result that the delay line is not damaged; If at least one of the comparison results of the excitation results and the expected results corresponding to all the test points indicates abnormal, obtaining a test result that the delay line is damaged.

4. The test method for delay-line-based design for testability according to claim 1, wherein The method further includes: When obtaining the test vectors according to the test for design for testability, generating a coverage rate of the test points on the delay line according to the test contents of the test for design for testability, and increasing the number of test points when the coverage rate is less than a preset threshold.

5. The test method for testability design based on a delay line according to claim 4, wherein There are multiple test points, and the method includes: Judging whether the first control logic of all the test points and the second control logic of all the observation points are inserted successfully according to the coverage rate; If not, re-inserting the first control logic of the test points and the second control logic of the observation points until the first control logic of all the test points and the second control logic of all the observation points are inserted successfully.

6. The test method for delay-line-based design for testability according to claim 1, wherein The method further includes: Obtaining a selection signal on the test point; When the selection signal is in the test mode for design for testability, performing a test for design for testability on the corresponding test point.

7. A test circuit for design for testability based on a delay line, which is used to implement the design for testability based on a delay line test method according to any one of claims 1-6, characterized in that, Including: A delay line for delaying the transmission time of an electrical signal; A test point provided at the input end of the delay line for testing whether the delay line is damaged; An observation point provided at the output end of the delay line for obtaining a test result of whether the delay line is damaged.

8. The test circuit for delay-line-based testability design according to claim 7, wherein The test point includes: A test data selector, and the output end of the test data selector is connected to the input end of the delay line; The first flip-flop, the output terminal of the first flip-flop is connected to the input terminal of the test data selector; Wherein, the input terminals of the test data selector are respectively used to obtain the selection signal at the test point, the preset input clock signal and the output signal of the first flip-flop; The input terminals of the first flip-flop are respectively used to obtain the ground signal and the test clock signal at the test point.

9. The test circuit for delay-line-based testability design according to claim 7, wherein The observation point includes: The second flip-flop, the input terminal of the second flip-flop is connected to the output terminal of the delay line; Wherein, the input terminals of the second flip-flop are respectively used to obtain the test clock signal at the test point and the output signal of the delay line.

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