Method for manufacturing semiconductor device and semiconductor device

Abstract

The present invention provides a method for manufacturing a semiconductor device and a semiconductor device, which relates to the technical field of semiconductor device manufacturing. The method for manufacturing a semiconductor device provided by the present invention includes the steps of: S10. providing a GaAs substrate; S20. etching a first surface of the GaAs substrate with a first treatment solution, where the first treatment solution is H3PO4:H2O2:H2O = 1:1:138 - 2:1:50, so as to form an uneven structure on the first surface; S30. forming a SiN x layer covering the uneven structure on the first surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device fabrication, and more particularly, to a method for fabricating a semiconductor device and a semiconductor device. Background Art

[0002] A high-power edge-emitting chip includes a GaAs substrate, a SiN x insulating layer, and an ohmic contact layer disposed from bottom to top. Among them, the ohmic contact layer is further divided into a first metal layer, a thick gold layer, and a second metal layer. Among them, both the first metal layer and the second metal layer are metal layers, while the thick gold layer is a thick gold layer.

[0003] In the prior art, when fabricating a high-power edge-emitting chip, after the thick gold layer and the second metal layer are peeled off, gold peeling occurs at the edge, that is, the gold layer of the ohmic contact and the underlying insulating SiN x layer fall off together. Moreover, after subsequent cleavage, some bars also have gold peeling problems during the adhesion test (similarly, SiN x falls off together). Summary of the Invention

[0004] An object of the present invention is to provide a method for fabricating a semiconductor device and a semiconductor device, which can alleviate the problem that the SiN x layer is likely to fall off during the fabrication process of the semiconductor device.

[0005] In a first aspect, the present invention provides a method for fabricating a semiconductor device, including the steps of:

[0006] S10. Providing a GaAs substrate;

[0007] S20. Corroding a first surface of the GaAs substrate with a first treatment solution, where the first treatment solution is H3PO4:H2O2:H2O = 1:1:138 - 2:1:50, so as to form an uneven structure on the first surface;

[0008] S30. Forming a SiN x layer covering the uneven structure on the first surface.

[0009] Further, in the step S20, the value range of the corrosion time t of the first surface is 15s - 20s.

[0010] Further, in the step S20, the value range of the maximum height difference of the uneven structure is 8nm - 10nm.

[0011] Further, it further includes a step performed after the step S30:

[0012] S41. Form a first metal layer of an ohmic contact layer on the first surface, wherein the first metal layer covers a part of the SiN x layer;

[0013] The method further includes steps performed after step S20:

[0014] Step S21. Form a pit in a first region of the first surface, where the SiN x layer covers the first region, and a region formed by the projection of the region in the SiN x layer that is not covered by the first metal layer onto the first surface of the GaAs substrate is the first region;

[0015] Along the depth direction of the pit, there is at least one position in the pit where the cross-sectional area is larger than the area of the opening of the pit.

[0016] Further, step S21 specifically includes steps:

[0017] S211. Form a mask template with an opening at a first region of the first surface of the GaAs substrate;

[0018] S212. Etch the first region through the opening using a first processing solution to form a pit.

[0019] Further, the ratio of the width L to the depth H of the opening of the pit is L:H > 5:1 and L:H < 12:1.

[0020] Further, the method further includes steps performed after step S30:

[0021] S41. Form a first metal layer of an ohmic contact layer on the first surface, wherein the first metal layer covers a part of the SiN x layer;

[0022] S42. Form a photoresist layer on the first metal layer, and a window penetrating the upper and lower surfaces is formed on the photoresist layer;

[0023] S43. Form a thick gold layer, a part of the thick gold layer covers the photoresist layer, and another part is located within the window;

[0024] S43. Form a second metal layer on the thick gold layer;

[0025] S44. Remove the photoresist layer so that a part of the thick gold layer and a part of the second metal layer above the photoresist layer are stripped together, and the projections of the thick gold layer and the second metal layer towards the GaAs substrate are both outside the SiN x layer.

[0026] Further, the step S30 includes the steps of:

[0027] S31. Obtain the warping direction of the first surface of the GaAs substrate;

[0028] S32. When the first surface of the GaAs substrate warps towards the SiN x layer side, a low-frequency SiN x single layer is formed on the first surface;

[0029] When the first surface of the GaAs substrate warps away from the SiN x layer side, the layer in contact with the first surface of the GaAs substrate is a high-frequency SiN x single layer;

[0030] The low-frequency SiN x single layer bears compressive stress, and the high-frequency SiN x single layer bears tensile stress.

[0031] In a second aspect, the present invention provides a semiconductor device, which is prepared by the semiconductor device preparation method according to any one of the foregoing embodiments.

[0032] The beneficial effects of the embodiments of the present invention are:

[0033] A semiconductor device preparation method provided by the present invention includes the steps of: S10. Provide a GaAs substrate; S20. Etch the first surface of the GaAs substrate with a first treatment solution, where the first treatment solution is H3PO4:H2O2:H2O = 1:1:138 - 2:1:50, so as to form an uneven structure on the first surface; S30. Form a SiN x layer covering the uneven structure on the first surface.

[0034] Before forming the SiN x layer, first roughen the first surface of the GaAs substrate with the first treatment solution to form an uneven structure, thereby increasing the contact area with the SiN x layer, and the SiN xThe adhesion of the layer is improved, avoiding the situation of gold peeling off during the subsequent peeling of the thick gold layer, the second metal layer, and the first metal layer, thereby improving the finished product yield of the product and the stability of the device performance. Phosphoric acid (H3PO4) is a corrosion inhibitor. It mainly forms a protective phosphate film through the reaction of phosphoric acid with the GaAs substrate, thereby achieving the purpose of corrosion inhibition. This layer of film can prevent the first surface of the GaAs substrate from further contacting and chemically reacting with substances such as acids and oxygen, playing a role in protecting the surface of the GaAs substrate. At the same time, phosphoric acid also has certain stability and solubility, making the corrosion more stable. In this embodiment, the first treatment liquid is selected as H3PO4:H2O2:H2O = 1:1:138 - 2:1:50, because low-concentration phosphoric acid cannot effectively etch the GaAs substrate to increase the surface roughness, and the high-concentration phosphoric acid has an uncontrollable speed. Description of the Drawings

[0035] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 Schematic diagram of the semiconductor device obtained by the semiconductor device manufacturing method provided by the embodiment of the present invention;

[0037] Figure 2 Schematic diagram of step S21 in the semiconductor device manufacturing method provided by the embodiment of the present invention;

[0038] Figure 3 Flow chart of step S40 in the semiconductor device manufacturing method provided by the embodiment of the present invention.

[0039] Reference numerals: 1 - GaAs substrate; 2 - SiN x layer; 3 - first metal layer; 4 - thick gold layer; 5 - second metal layer; 6 - pit; 7 - photoresist layer; 8 - window. Detailed Embodiments

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0041] Accordingly, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0042] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.

[0043] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and should not be construed as indicating or implying relative importance.

[0044] In addition, terms such as "horizontal" and "vertical" do not mean that the components are required to be absolutely horizontal or hanging, but may be slightly inclined. For example, "horizontal" only means that its direction is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but may be slightly inclined.

[0045] In the description of the present invention, it should also be noted that unless otherwise clearly specified and limited, the terms "set", "installed", "connected", "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] As Figure 1 shown, the method for preparing a semiconductor device provided by the present invention includes the steps of:

[0047] S10. Provide a GaAs substrate 1.

[0048] S20. Etch the first surface of the GaAs substrate 1 with a first treatment solution, wherein the first treatment solution is H3PO4:H2O2:H2O = 1:1:138 - 2:1:50, so as to form a rough concave-convex structure on the first surface of the GaAs substrate 1.

[0049] First, phosphoric acid (H3PO4) is a corrosion inhibitor. By reacting phosphoric acid with the GaAs substrate 1, a protective phosphate film is formed, thereby achieving the purpose of corrosion inhibition. This film can prevent the first surface of the GaAs substrate 1 from further contacting and chemically reacting with substances such as acids and oxygen, playing a role in protecting the surface of the GaAs substrate 1. At the same time, phosphoric acid also has certain stability and solubility, making the corrosion more stable.

[0050] In the solution, the reason for not using hydrochloric acid for corrosion is that: before depositing the SiN x layer 2, the ridge waveguide of the GaAs substrate 1 is corroded (the exposed part of this layer is a high-Al component). Hydrochloric acid will accelerate the corrosion of the high-Al layer, while phosphoric acid will not show such a phenomenon. Hydrofluoric acid is not used because hydrofluoric acid itself is not a corrosion-inhibiting solvent but an acid with strong corrosiveness. It will also have a strong corrosive effect on the GaAs substrate 1 even when the solution ratio concentration is low. To sum up: phosphoric acid, this corrosion-inhibiting solvent, is selected for the purpose of removing the surface oxide layer and roughening. Utilizing its stability and corrosion-inhibiting effect, a stable and controllable effect is achieved, which can not only remove the oxide layer but also undergo a controllable chemical reaction with the GaAs substrate 1.

[0051] In the step S20, the value range of the corrosion time t can be 15s - 20s. If the time is too long, the corrosion will be too deep; if the time is too short, the unevenness will be insufficient and the roughening effect will not be achieved. After the reaction, the value range of the maximum height difference of the uneven structure is 8nm - 10nm. The maximum height difference refers to the vertical distance between the lowest point of the concave part and the highest point of the convex part.

[0052] Among them, the main steps of surface corrosion are as follows:

[0053] A. Prepare the first treatment solution (H3PO4:H2O2:H2O = 1:1:138 - 2:1:50); then introduce the first treatment solution into the circulation tank of the spin dryer (SRD) for circulation. When the temperature of the first treatment solution cools to 24°C ± 2°C, perform a companion wafer verification (at a rate of about 40n / min), and then place the GaAs substrate 1 into the first treatment solution for corrosion for 15s;

[0054] B. Take out the GaAs substrate 1 from the first treatment solution and rinse it with pure water (DIW) for 255s. Specifically, first, inject deionized water; then, spray ionized water; then blow nitrogen: this can increase the impact force to improve the cleaning effect and avoid generating oxides on the wafer surface; finally, quickly drain: quickly drain the deionized water.

[0055] C. After the flushing is completed, take it out and put it into a spin dryer for spin-drying. Specifically, first rinse it; then blow it dry; then perform primary drying: rough drying, with a rotation speed of 600; finally perform secondary drying: fine drying, with a rotation speed of 800.

[0056] S30. Form SiN layer 2 covering the concavo-convex structure on the first surface. x layer 2.

[0057] Specifically, the plasma enhanced chemical vapor deposition method can be used to prepare SiN layer 2 on the first surface of the GaAs substrate 1. x layer 2.

[0058] Further, the step S30 includes specific steps:

[0059] Obtain the warping direction of the first surface of the GaAs substrate 1. Due to the limitation of its own properties, the first surface of the existing GaAs substrate 1 may not be a flat surface, but a completely curved surface upward or downward. Before forming the SiN layer 2, detect the bending condition of the first surface, and then prepare SiN layer 2 with different properties according to its bending condition. x layer 2. x layer 2.

[0060] SiN x layer 2 is formed by alternately depositing a low-frequency SiN single layer and a high-frequency SiN single layer multiple times. Among them, when the first surface of the GaAs substrate 1 warps toward the SiN layer 2 side, the layer in contact with the first surface of the GaAs substrate 1 is a low-frequency SiN single layer. And when the first surface of the GaAs substrate 1 warps away from the SiN layer 2 side, the layer in contact with the first surface of the GaAs substrate 1 is a high-frequency SiN single layer; the low-frequency SiN single layer bears compressive stress, and the high-frequency SiN single layer bears tensile stress. Make the stress of the single layer in contact with the first surface of the SiN layer 2 more compatible with the first surface of the GaAs, and the two fit more closely. x single layer and high-frequency SiN x single layer; the low-frequency SiN x single layer bears compressive stress, and the high-frequency SiN x single layer bears tensile stress. Make the stress of the single layer in contact with the first surface of the SiN layer 2 more compatible with the first surface of the GaAs, and the two fit more closely. x layer 2 side warps, the layer in contact with the first surface of the GaAs substrate 1 is a high-frequency SiN x single layer; the low-frequency SiN x single layer bears compressive stress, and the high-frequency SiN x single layer bears tensile stress. Make the stress of the single layer in contact with the first surface of the SiN layer 2 more compatible with the first surface of the GaAs, and the two fit more closely. x layer 2 and the single layer in contact with the first surface are more compatible, and the two fit more closely.

[0061] Specifically, the deposition of the SiN layer 2 is divided into the following steps: x layer 2 is divided into the following steps:

[0062] First. Preheat: N2 volume flow rate: 1000 sccm, pressure: 1000 mT, temperature: 300 °C.

[0063] Second. Gas stabilization: N2 volume flow rate: 900 sccm, pressure 900 mT, temperature: 300 °C.

[0064] Third. N2 plasma surface treatment: N2 volume flow rate: 900 sccm, pressure 900 mT, power: 90 W, temperature: 300 °C.

[0065] Third. N2 purge: 30 s of vacuum pumping, 30 s of vacuum breaking, 3 cycles.

[0066] Fifth. Gas stabilization: SiH4 50 sccm, NH3 38 sccm, N2 200 sccm, pressure 1080 mT, temperature: 300 °C.

[0067] Sixth. High-frequency SiN x Single layer: SiH4 volume flow rate: 50 sccm, NH3 volume flow rate: 38 sccm, N2 volume flow rate: 200 sccm, pressure 1080 mT, power 30 W (HF), temperature: 300 °C.

[0068] Seventh. Low-frequency SiN x Single layer: SiH4 volume flow rate: 50 sccm, NH3 volume flow rate: 38 sccm, N2 volume flow rate: 200 sccm, pressure 1080 mT, power 30 W (LF), temperature: 300 °C. (Select whether to perform the sixth step or the seventh step first according to the warping direction of the first surface of the GaAs substrate 1. There are 15 cycles in total for the sixth step - seventh step. For example, perform the sixth step first, then the seventh step, then the sixth step again, and so on, alternating for 15 cycles).

[0069] Eighth. Vacuum pumping.

[0070] The method further includes a step of forming an ohmic contact layer after step S30, specifically including:

[0071] S41. Form a first metal layer 3 of the ohmic contact layer on the first surface, wherein the first metal layer 3 covers a part of the SiN x layer 2. Further, the method may further include a step before step S30: Step S21. Form a pit 6 in a first region of the first surface, and the SiN x layer 2 covers the first region, wherein the SiN xThe region formed by the projection of the region in layer 2 not covered by the first metal layer 3 onto the first surface of the GaAs substrate 1 is the first region; along the depth direction of the pit 6, there is at least one position in the pit 6 where the cross-sectional area is larger than the area of the opening of the pit 6, so that in step S30, the pit 6 is filled with the material for forming SiN x layer 2.

[0072] As Figure 2 shown, when preparing the ohmic contact layer, a part of the region in the SiN x layer 2 is covered by the first metal layer 3, while a part of the region is not covered (i.e., the first region). Since the stress is the greatest when the thick gold layer 4 and the second metal layer 5 are peeled off, the region in the SiN x layer 2 covered by the first metal layer 3 is protected, while the first region is not protected. Therefore, it is necessary to further increase the adhesion between the GaAs substrate 1 and the SiN x layer 2 in the first region. After the pit 6 is formed, when the SiN x layer 2 is prepared, a part of the SiN x will enter the pit 6. Since the structure of the pit 6 is a pocket type with a wide middle and a narrow opening, the part of the SiN x layer 2 entering the pit 6 will be stuck in the pit 6, thereby increasing the adhesion between the GaAs substrate 1 and the SiN x layer 2.

[0073] In this embodiment, the ratio L:H of the width L of the opening of the pit 6 to the depth H of the pit 6 is L:H > 5:1 and L:H < 12:1. Because PECVD deposits SiN x with step coverage, controlling the ratio of the length to the height of the opening does not affect the deposition of silicon nitride.

[0074] The formation of the pit 6 can be carried out by wet etching. Due to isotropy during etching, lateral etching will occur during the etching process, and naturally a pocket-type opening with a wide middle and a narrow opening will be formed. Specifically, step S21 specifically includes the steps of: S211. Form a mask template with an opening at the first region on the first surface of the GaAs substrate 1, and the mask template can be formed by photolithography and development. S212. Etch the first region through the opening using the first treatment liquid to form the pit 6 with the above morphology.

[0075] The formation of the pits 6 can be carried out before the surface roughening treatment. That is, first, photolithography and development are performed on the surface of the GaAs substrate 1, and then the photoresist is removed to form a mask template. Then, the surface of the GaAs substrate 1 is etched using the mask template to form the pits 6, and then the photoresist is removed. Then, the first treatment liquid is used to roughen and form an uneven structure, and finally, it is rinsed and dried to obtain the GaAs substrate 1 with pits 6 and a rough surface. The setting of the pits 6 can further increase the degree of surface roughening and improve the contact area between the first surface and the SiN x layer 2, thereby enhancing its adhesion.

[0076] As Figure 3 shown, the semiconductor device manufacturing method further includes a step of forming an ohmic contact layer after step S30. Among them, the step of forming the ohmic contact layer further includes:

[0077] S42. A photoresist layer 7 is formed on the first metal layer 3, and a window 8 penetrating its upper and lower surfaces is formed on the photoresist layer 7.

[0078] The photoresist layer 7 is used to form a mask for the thick gold layer 4. A photoresist is coated on the upper surface of the first metal layer 3, and after exposure and development, a window 8 penetrating the upper and lower surfaces of the photoresist layer 7 is formed in the preset thick gold layer 4 region.

[0079] S43. A thick gold layer 4 is formed, and a part of the thick gold layer 4 covers the photoresist layer 7, and another part is located within the window 8.

[0080] Depositing from top to bottom, the thick gold layer 4 is gradually formed. A part of the thick gold layer 4 covers the photoresist layer 7, and another part is located within the window 8.

[0081] S43. A second metal layer 5 is formed on the thick gold layer 4.

[0082] After the thick gold layer 4 is prepared, the second metal layer 5 is directly fabricated thereon.

[0083] S44. The photoresist layer 7 is removed, so that a part of the thick gold layer 4 and a part of the second metal layer 5 above the photoresist layer 7 are uniformly peeled off. The projections of the thick gold layer 4 and the second metal layer 5 facing the GaAs substrate 1 are both located outside the SiN x layer 2.

[0084] The photoresist layer 7 is peeled off, and a part of the thick gold layer 4 and a part of the second metal layer 5 covering the photoresist layer 7 are peeled off together, and the morphologies of a part of the thick gold layer 4 and a part of the second metal layer 5 at the position of the window 8 are retained.

[0085] In the prior art, in the step of forming the ohmic contact layer: the thick gold layer 4 is first peeled off, then the second metal layer 5 is plated, and then the second metal layer 5 is peeled off. When the second metal layer 5 is peeled off, it has a great impact on the warping of the GaAs substrate 1, and the wafer warping changes greatly, that is, the stress of the second metal layer 5 is large, which will cause the thin film stress mismatch. Therefore, in this method, the edge of the second metal layer 5 is shrunk, and in the area without the protection of the thick gold layer 4, a SiN x layer 2 + first metal layer 3 system is formed instead of the SiN x layer 2 + first metal layer 3 + second metal layer 5 system, which greatly improves the adhesion. Therefore, in this method, the thick gold layer 4 and the second metal layer 5 are peeled off in a unified manner. The process of peeling off the thick gold layer 4 generates less stress, thereby reducing the generation of large stress and reducing the impact of peeling off the second metal layer 5 on the GaAs substrate 1.

[0086] The present invention provides a semiconductor device. The semiconductor device is prepared by the semiconductor device preparation method described in any one of the foregoing embodiments. In the semiconductor device, the adhesion between the GaAs substrate 1 and the SiN x layer 2 is strong, and the problem of gold peeling is not likely to occur during peeling.

[0087] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: Includes steps: S10. Providing a GaAs substrate (1); S20. Etching the first surface of the GaAs substrate (1) using a first treatment liquid, wherein the first treatment liquid is H3PO4:H2O2:H2O=1:1:138-2:1:50, so that a concave-convex structure is formed on the first surface; S30. Forming a SiNx layer (2) covering the concavo-convex structure on the first surface; The following steps are also included after step S30: S41. Forming a first metal layer (3) of an ohmic contact layer on the first surface, wherein the first metal layer (3) covers a portion of the SiN x layer(2); S42. forming a photoresist layer (7) on the first metal layer (3), wherein windows (8) are formed on the photoresist layer (7) and penetrate the upper and lower surfaces thereof; S43. forming a thick gold layer (4), wherein a portion of the thick gold layer (4) covers the photoresist layer (7), and another portion is located within the window (8); S43. Forming a second metal layer (5) on the thick gold layer (4); S44. Remove the photoresist layer (7) so that part of the thick gold layer (4) and part of the second metal layer (5) above the photoresist layer (7) are uniformly peeled off, and the projections of the thick gold layer (4) and the second metal layer (5) toward the GaAs substrate (1) are both located on the SiN x Outside layer (2).

2. The method for preparing a semiconductor device according to claim 1, characterized in that: The time t for corroding the first surface in the step S20 ranges from 15s to 20s.

3. The method for preparing a semiconductor device according to claim 1, wherein: In the step S20, the maximum height difference of the concave-convex structure ranges from 8 nm to 10 nm.

4. The method for preparing a semiconductor device according to claim 1, wherein: The following steps are also included after step S20: Step S21. Form a pit (6) in the first region of the first surface, wherein the SiN x The layer (2) covers the first region, wherein the SiN x The area formed by the projection of the area in the layer (2) not covered by the first metal layer (3) onto the first surface of the GaAs substrate (1) is the first area; Along the depth direction of the pit (6), there is at least one position in the pit (6) where the area of ​​the cross section is larger than the area of ​​the opening of the pit (6).

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step S21 specifically includes the following steps: S211. Forming a mask having an opening at a first region of a first surface of a GaAs substrate (1); S212. Etching the first area through the opening using the first processing liquid to form a pit (6).

6. The method for preparing a semiconductor device according to claim 4, characterized in that: The ratio of the width L of the opening of the pit (6) to the depth H of the pit (6) is L:H>5:1, and L:H<12:

1.

7. The method for preparing a semiconductor device according to any one of claims 1 to 6, characterized in that: In the step S30, a SiN substrate is prepared on the first surface of the GaAs substrate (1) by using a plasma enhanced chemical vapor deposition method. x Layer (2).

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The step S30 comprises the steps of: S31. Obtaining a warping direction of a first surface of the GaAs substrate (1); S32. When the first surface of the GaAs substrate (1) faces the SiN x When one side of the layer (2) is warped, a low-frequency SiN x Single layer; When the first surface of the GaAs substrate (1) faces away from the SiN x When one side of the layer (2) is warped, the layer in contact with the first surface of the GaAs substrate (1) is a high-frequency SiN x Single layer; The low frequency SiN x The single layer is subjected to compressive stress, the high frequency SiN x The single layer is subjected to tensile stress.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the semiconductor device manufacturing method according to any one of claims 1 to 8.

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