Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a dielectric layer on one side of a substrate; forming an opening in the dielectric layer, the opening exposing the conductive structure in the substrate; forming an initial seed layer covering the side wall and the bottom of the opening; the initial seed layer is induced to form a seed layer, and the number of crystal nucleuses on the surface of the seed layer is larger than the number of crystal nucleuses on the surface of the initial seed layer; an interconnect structure is formed in the opening based on the seed layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] In the semiconductor manufacturing industry, aluminum and its alloys have been widely used for a long time to realize the interconnection of integrated circuits composed of a large number of transistors and other devices. However, with the continuous reduction in the size of transistors, the aluminum interconnection process that has been used for decades can no longer meet the needs of continuously improving the integration, speed and reliability of integrated circuits. Compared with traditional aluminum and its alloys, the resistivity of copper (Cu) is only about half of that of aluminum-copper alloys. For example, the resistivity of an alloy containing 0.5% copper is about 3.2μΩ·cm, while the resistivity of copper is 1.678μΩ·cm. Lower resistivity can not only reduce the RC delay of metal interconnection, but also reduce the power consumption of devices. In other words, as the size of devices decreases, the interconnection structure with lower resistivity can continuously reduce the intrinsic delay and continuously increase the device speed. Therefore, copper has gradually replaced aluminum as the main material for metal interconnection.

[0003] However, there are still many problems to be solved for lower resistivity interconnect structures (eg, copper). Summary of the invention

[0004] The present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0005] The first aspect of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes: forming a dielectric layer on one side of a substrate; forming an opening in the dielectric layer, wherein the opening exposes a conductive structure in the substrate; forming an initial seed layer covering the sidewalls and bottom of the opening; performing an induction treatment on the initial seed layer to form a seed layer, wherein the number of crystal nuclei on the surface of the seed layer is greater than the number of crystal nuclei on the surface of the initial seed layer; and forming an interconnection structure in the opening based on the seed layer.

[0006] In some embodiments, forming a dielectric layer on one side of the substrate includes: forming a first dielectric layer and a second dielectric layer stacked in sequence on one side of the substrate; forming an opening in the dielectric layer includes: before forming the second dielectric layer, forming a first opening in the first dielectric layer, the first opening exposing the conductive structure; after forming the second dielectric layer, forming a second opening in the second dielectric layer, wherein a cross-sectional size of the second opening is greater than or equal to a cross-sectional size of the first opening, and the second opening and the first opening constitute the opening.

[0007] In some embodiments, the forming of the initial seed layer covering the sidewalls and the bottom of the opening includes: forming a first initial seed layer covering the sidewalls and the bottom of the first opening; the inducing treatment of the initial seed layer to form the seed layer includes: before forming the second dielectric layer, performing a first induction treatment on the first initial seed layer to form a first seed layer, wherein the number of crystal nuclei on the surface of the first seed layer is greater than the number of crystal nuclei on the surface of the first initial seed layer; the forming of an interconnect structure in the opening based on the seed layer includes: forming a first interconnect structure in the first opening based on the first seed layer.

[0008] In some embodiments, the second opening exposes the first seed layer and the first interconnect structure; the forming of the initial seed layer covering the sidewalls and the bottom of the opening also includes: forming a second initial seed layer covering the sidewalls and the bottom of the second opening; the inducing treatment of the initial seed layer to form the seed layer includes: performing a second induction treatment on the second initial seed layer to form a second seed layer, wherein the number of crystal nuclei on the surface of the second seed layer is greater than the number of crystal nuclei on the surface of the second initial seed layer; the forming of the interconnect structure in the opening based on the seed layer includes: forming a second interconnect structure in the second opening based on the second seed layer.

[0009] In some embodiments, forming an opening in the dielectric layer further includes: before forming the second dielectric layer, forming a sacrificial layer in the first opening, wherein the second opening exposes the sacrificial layer; based on the second opening, removing the sacrificial layer so that the second opening is connected to the first opening.

[0010] In some embodiments, the induction treatment includes at least one of radiation induction, laser induction, electron beam induction and light induction.

[0011] The second aspect of the present disclosure provides a semiconductor structure, which is manufactured by the method described in any embodiment of the first aspect of the present disclosure. The semiconductor structure comprises: a substrate, a dielectric layer, an interconnection structure and a seed layer; the dielectric layer is located on one side of the substrate; the interconnection structure extends from the surface of the dielectric layer away from the substrate into the dielectric layer; the seed layer wraps the sidewall and bottom of the interconnection structure, wherein the interconnection structure is connected to the conductive structure in the substrate through the seed layer.

[0012] In some embodiments, the dielectric layer includes a first dielectric layer and a second dielectric layer stacked in sequence on one side of the substrate; the interconnect structure includes a first interconnect structure and a second interconnect structure, wherein the first interconnect structure extends from a surface of the first dielectric layer facing away from the substrate to the first dielectric layer, and the second interconnect structure extends from a surface of the second dielectric layer facing away from the first dielectric layer to the second dielectric layer; the seed layer includes a first seed layer and a second seed layer, wherein the first seed layer wraps the side wall and the bottom of the first interconnect structure, and the second seed layer wraps the side wall and the bottom of the second interconnect structure.

[0013] In some embodiments, a cross-sectional dimension of the second interconnect structure is greater than or equal to a cross-sectional dimension of the first interconnect structure.

[0014] In some embodiments, the material of the seed layer includes at least one of tantalum nitride, tantalum, and copper; the material of the interconnect structure includes at least one of copper and cobalt.

[0015] In the present disclosure, a dielectric layer is formed on one side of a substrate; an opening is formed in the dielectric layer, the opening exposing a conductive structure in the substrate; an initial seed layer covering the sidewalls and bottom of the opening is formed; the initial seed layer is induced to form a seed layer, wherein the number of crystal nuclei on the surface of the seed layer is greater than the number of crystal nuclei on the surface of the initial seed layer; and an interconnection structure is formed in the opening based on the seed layer. In this way, the formation of crystal nuclei can be promoted and the number of crystal nuclei can be increased. The increase in the number of crystal nuclei can improve the uniformity and continuity of the interconnection structure subsequently formed on the seed layer, thereby improving the quality of the interconnection structure and facilitating the improvement of the conductive performance of the interconnection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1C It is a schematic diagram of forming an interconnection structure provided by an exemplary embodiment.

[0017] Figure 2 It is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0018] FIG. 3A to FIG. 3C A schematic diagram of a manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure

[0019] 4A to 4F It is a schematic diagram of a manufacturing process of another semiconductor structure provided by an embodiment of the present disclosure.

[0020] Figure 5A and Figure 5B It is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] In order to facilitate the understanding of the present disclosure, the exemplary embodiments of the present disclosure will be described in more detail below with reference to the relevant drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0022] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In some embodiments, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of the actual embodiment may not be described here, and well-known functions and structures may not be described in detail.

[0023] The present disclosure will be described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0024] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0025] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0026] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0027] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0028] With the vigorous development of semiconductor technology, semiconductor thin film technology has also developed, and physical vapor deposition (PVD) thin film technology has emerged. Common types of physical vapor deposition coating processes include: vacuum evaporation coating, vacuum sputtering coating and vacuum ion plating. Among them, vacuum sputtering coating is widely used in semiconductor processes. Figures 1A to 1C The formation process of the interconnection structure is exemplarily described.

[0029] Figures 1A to 1C FIG. 1 is a schematic diagram of forming an interconnection structure provided by an exemplary embodiment. Figure 1A and Figure 1B As shown, an opening OP extending through the dielectric layer is formed, the opening OP exposes the conductive structure 101 in the substrate, a seed layer 102 covering the dielectric layer and the opening OP is formed, and a metal is electroplated on the seed layer 102 to form an interconnection structure 103 in the opening, and the interconnection structure 103 is connected to the conductive structure 101 through the seed layer 102. Figure 1C The electron microscope image of the formed interconnect structure is shown. The formation process of the seed layer 102 includes but is not limited to PVD, and the material of the interconnect structure 103 includes but is not limited to copper.

[0030] Taking copper electroplating as an example, the nucleation and growth of copper become very critical issues. In the process of copper electroplating, the growth of copper may have various problems such as vacancies and damage, which makes the quality of the final copper interconnection poor and seriously affects the conductive performance of the device.

[0031] Based on one or more of the above technical problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes: forming a dielectric layer on one side of a substrate; forming an opening in the dielectric layer, the opening exposing a conductive structure in the substrate; forming an initial seed layer covering the sidewalls and bottom of the opening; inducing the initial seed layer to form a seed layer, wherein the number of crystal nuclei on the surface of the seed layer is greater than the number of crystal nuclei on the surface of the initial seed layer; and forming an interconnection structure in the opening based on the seed layer. In this way, by inducing the initial seed layer, the formation of crystal nuclei can be promoted and the number of crystal nuclei can be increased. The increase in the number of crystal nuclei can improve the uniformity and continuity of the interconnection structure subsequently formed on the seed layer, thereby improving the quality of the interconnection structure and facilitating the improvement of the conductive performance of the interconnection structure.

[0032] Figure 2 is a flow chart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. It should be noted that: Figure 2 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 2The steps shown in the figure can be adjusted in order according to actual needs. Figure 2 As shown, the manufacturing method comprises the following steps:

[0033] Step S210: forming a dielectric layer on one side of the substrate;

[0034] Step S220: forming an opening in the dielectric layer, wherein the opening exposes the conductive structure in the substrate;

[0035] Step S230: forming an initial seed layer covering the sidewalls and bottom of the opening;

[0036] Step S240: performing an induction treatment on the initial seed layer to form a seed layer, wherein the number of crystal nuclei on the surface of the seed layer is greater than the number of crystal nuclei on the surface of the initial seed layer;

[0037] Step S250 : forming an interconnection structure in the opening based on the seed layer.

[0038] FIG. 3A to FIG. 3C is a schematic diagram of a manufacturing process of a semiconductor structure provided by an embodiment of the present disclosure. Figure 2 , FIG. 3A to FIG. 3C The method for manufacturing the semiconductor structure provided by the embodiment of the present disclosure is exemplarily described.

[0039] In step S210, refer to Figure 3A As shown, a dielectric layer 320 is formed on one side of the substrate. For example, a thin film deposition process is used to form the dielectric layer 320 on the front side of the substrate. The thin film deposition process involved in this embodiment and the following includes at least one of a PVD process, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and an Atomic Layer Deposition (ALD) process.

[0040] The substrate includes a pre-metal dielectric layer 310 (Pre-Metal Dielectric, PMD) and a conductive structure 301 located in the pre-metal dielectric layer 310. It should be noted that the substrate may also include Figure 3A Other film layers not shown in the figure, for example, the device layer located on the side of the pre-metal dielectric layer 310 away from the dielectric layer 320. For ease of understanding, Figure 3A Only the pre-metal dielectric layer 310 and the conductive structure 301 are shown. In this embodiment, the front side of the substrate may be the surface of the pre-metal dielectric layer 310 facing away from the device layer.

[0041] The pre-metal dielectric layer 310 is located between the device layer (not shown in the figure) and the dielectric layer 320. The pre-metal dielectric layer 310 serves as a dielectric layer between the device layer and the dielectric layer 320. Figure 3C The spacer layer between the interconnect structures 340 in the device layer can protect the device layer from being contaminated by foreign particles. The material of the pre-metal dielectric layer 310 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and low dielectric constant (low-k) material.

[0042] The conductive structure 301 connects the circuit components in the device layer, that is, the circuit components can be connected through the conductive structure 301 and the Figure 3C The conductive structure 301 is led out from the interconnect structure 340 in the substrate. The material of the conductive structure 301 includes a conductive material, for example, at least one of polysilicon, doped polysilicon, and metal tungsten. The number of the conductive structure 301 can be one or more. When the number of the conductive structure 301 is multiple, the multiple conductive structures 301 are isolated from each other by the pre-metal dielectric layer 310.

[0043] In step S220, refer to Figure 3A As shown, an opening OP is formed in the dielectric layer 320, and the opening OP exposes the conductive structure 301 in the substrate. For example, a patterned photoresist layer (not shown in the figure) is formed on the surface of the dielectric layer 320 away from the substrate, and the dielectric layer 320 is etched based on the patterned photoresist layer until the conductive structure 301 is exposed, thereby forming an opening OP in the dielectric layer 320. It should be noted that the opening OP can be formed by etching in one step or in steps. The etching process involved in this embodiment and the following includes at least one of dry etching and wet etching.

[0044] In some embodiments, the above step S210 includes: forming a first dielectric layer 321 and a second dielectric layer 322 stacked in sequence on one side of the substrate. For example, the first dielectric layer 321 and the second dielectric layer 322 are sequentially deposited on the front side of the substrate using a thin film deposition process, and the first dielectric layer 321 and the second dielectric layer 322 may include one or more film layers. For example, referring to Figure 3AAs shown, the first dielectric layer 321 includes a dielectric barrier layer 3211 and a first insulating layer 3212, and the dielectric barrier layer 3211 is located between the pre-metal dielectric layer 310 and the first insulating layer 3212; the second dielectric layer 322 includes an isolation layer 3212 and a second insulating layer 3222, and the isolation layer 3212 is located between the first insulating layer 3212 and the second insulating layer 3222. The material of the dielectric barrier layer 3211 includes but is not limited to nitrogen-doped silicon carbide (NDC), and the dielectric barrier layer 3211 can prevent copper from diffusing in the substrate and its oxide. The isolation layer 3212 includes but is not limited to silicon nitride. The materials of the first insulating layer 3212 and the second insulating layer 3222 include but are not limited to silicon oxide.

[0045] In some embodiments, the above step S220 includes: before forming the second dielectric layer 322, forming a first opening in the first dielectric layer 321, the first opening exposing the conductive structure 301; forming a sacrificial layer (not shown in the figure) in the first opening; after forming the second dielectric layer 322, forming a second opening in the second dielectric layer 322, the second opening exposing the sacrificial layer; based on the second opening, removing the sacrificial layer so that the second opening and the first opening are connected, and the second opening and the first opening constitute an opening OP.

[0046] Exemplarily, a patterned first photoresist layer (not shown) is formed on the surface of the first dielectric layer 321 facing away from the substrate, and the first dielectric layer 321 is etched based on the patterned first photoresist layer until the conductive structure 301 is exposed, thereby forming a first opening in the first dielectric layer 321. The first opening includes but is not limited to a via, and the number of the vias can be one or more. For ease of understanding, Figure 3A Two vias are shown in FIG.

[0047] A sacrificial material is filled into the first opening to form a sacrificial layer. The material of the sacrificial layer includes but is not limited to a carbon-containing material. In practical applications, a planarization process such as chemical mechanical polishing can also be used to remove the sacrificial material on the surface of the first dielectric layer 321, and the sacrificial material retained in the first opening constitutes the sacrificial layer.

[0048] A second dielectric layer 322 is deposited on the first dielectric layer 321 and the sacrificial layer, a patterned second photoresist layer (not shown in the figure) is formed on the surface of the second dielectric layer 322 away from the first dielectric layer 321, and the second dielectric layer 322 is etched based on the patterned second photoresist layer until the sacrificial layer is exposed, thereby forming a second opening in the second dielectric layer 322. The second opening includes but is not limited to a trench, and the trench exposes the sacrificial layer in one or more vias.

[0049] By removing the exposed sacrificial layer through the second opening, the second opening can be connected to the first opening. Here, the second opening and the first opening constitute the opening OP. The cross-sectional size of the second opening is greater than or equal to the cross-sectional size of the first opening, for example, Figure 3A The groove in the second opening connects the two vias, and the cross-sectional size of the second opening is greater than the cross-sectional size of the first opening. Of course, in other embodiments, the cross-sectional size of the second opening can be equal to the cross-sectional size of the first opening.

[0050] It should be noted that, in the process of etching the second dielectric layer 322, there may be a certain amount of over-etching, that is, a portion of the first dielectric layer 321 and the sacrificial layer is etched, so that the bottom of the second opening extends into the first dielectric layer 321 and the sacrificial layer, thereby forming Figure 3A The opening OP is shown.

[0051] In step S230, refer to Figure 3A As shown in FIG. 1 , an initial seed layer 330S is formed to cover the sidewalls and bottom of the opening OP. For example, a vacuum sputtering coating is used to form the initial seed layer 330S. Figure 3A The initial seed layer 330S shown conformally covers the dielectric layer 320 and the surface exposed by the opening OP. The material of the initial seed layer 330S includes at least one of titanium and copper.

[0052] In some embodiments, the manufacturing method further includes: forming a barrier layer covering the sidewalls and bottom of the opening OP. For example, a barrier layer is deposited on the dielectric layer 320 and the surface exposed by the opening OP using a thin film deposition process, and then an initial seed layer 330S is formed, that is, the barrier layer is formed before the initial seed layer 330S. The barrier layer is used to block the metal diffusion in the interconnect structure 340, and the barrier layer can also improve the adhesion of the conductive film layer subsequently formed on the seed layer 330, thereby improving the film layer quality. The material of the barrier layer includes at least one of tungsten, titanium, tantalum, tungsten nitride, titanium nitride, and tantalum nitride.

[0053] In step S240, refer to Figure 3B As shown, the initial seed layer 330S is subjected to an induction treatment (IT) to form a seed layer 330. The induction treatment includes at least one of irradiation induction, laser induction, electron beam induction and light induction. For ease of understanding, the following will take irradiation induction as an example for exemplary description.

[0054] Exemplarily, the initial seed layer 330S is irradiated and induced by in-situ heavy ion helium (He). Irradiation can change the nucleation time, the number of nuclei, and the shape of nuclei, etc. These factors will affect the number of crystal nuclei, thereby promoting the formation of crystal nuclei and increasing the number of crystal nuclei, so that the number of crystal nuclei on the surface of the initial seed layer 330S after irradiation induction is greater than the number of crystal nuclei on the surface of the initial seed layer 330S before irradiation induction, that is, the number of crystal nuclei on the surface of the seed layer 330 is greater than the number of crystal nuclei on the surface of the initial seed layer 330S. It can be understood that the seed layer 330 is the initial seed layer 330S after the induction treatment. It should be noted that more crystal nuclei can promote more uniform crystal growth, and the increase in the number of crystal nuclei can improve the uniformity and continuity of the conductive film layer subsequently formed on the seed layer 330.

[0055] In some embodiments, the defect concentration of the seed layer 330 is greater than the defect concentration of the initial seed layer 330S. It should be noted that radiation induction can increase the defect concentration of the initial seed layer 330S. Specifically, radiation induction will form defects in the initial seed layer 330S itself, so that the defect concentration of the initial seed layer 330S after radiation induction is greater than the defect concentration of the initial seed layer 330S before radiation induction, that is, the defect concentration of the seed layer 330 is greater than the defect concentration of the initial seed layer 330S, and these defects can provide more nucleation sites, promote the formation of crystal nuclei, and increase the number of crystal nuclei.

[0056] The principle of increasing defect concentration by irradiation mainly includes the following two points: 1) Thermal effect. The thermal effect generated by irradiation can cause the film grains to melt and grow. This thermal effect helps the movement and recombination of defects and can increase the defect concentration; 2) Defect recombination at the interface. In metal-based nanostructured materials, grain boundaries can absorb vacancies and interstitial atoms generated by irradiation and recombine at the interface, thereby changing the defect concentration near the interface.

[0057] In step S250, refer to Figure 3C As shown, based on the seed layer 330, an interconnection structure 340 is formed in the opening OP. For example, metal is electroplated in the opening OP formed with the seed layer 330 to form the interconnection structure 340 in the opening OP, and the interconnection structure 340 is connected to the conductive structure 301 through the seed layer 330. The material of the interconnection structure 340 includes at least one of copper, cobalt, and ruthenium. In practical applications, a planarization process such as chemical mechanical polishing can also be used to remove the seed layer 330 and the metal on the surface of the dielectric layer 320, and the metal retained in the opening OP constitutes the interconnection structure 340. Electroplating includes but is not limited to electrochemical plating (ECP).

[0058] For example, after forming a copper seed layer, by inducing irradiation on the copper seed layer, the vacancy nucleation and growth movement of the copper seed layer can be promoted, and the crystal nuclei of the copper seed layer can be precisely and evenly arranged, so that uniform copper interconnects can be generated after ECP electroplating, and the electron transport properties of the semiconductor structure can be regulated, thereby optimizing the performance of semiconductor devices. It can be understood that irradiation increases the defect concentration in the seed layer film, increases the electron carrier concentration, and reduces the surface resistivity of the seed layer film. At the same time, by adjusting the laser irradiation energy density, the defect concentration of the seed layer film can be quickly and effectively regulated within a large range, promoting the uniform growth of the subsequent ECP film.

[0059] In some embodiments, the wavelength of the laser irradiation is 10 nm to 1 mm; the frequency of the laser irradiation is 0 to 3×10 16 Hz; the number of laser irradiation pulses is 50 to 500 times; the energy density of laser irradiation is 50mJ / cm 2 Up to 2000mJ / cm 2 .

[0060] 4A to 4F is a schematic diagram of another semiconductor structure manufacturing process provided by an embodiment of the present disclosure. It should be noted that: 4A to 4F The embodiment shown is FIG. 3A to FIG. 3C The same structures continue to use the same reference numerals, and the same structures can refer to the relevant descriptions of the above embodiments, and will not be described in detail again. Figure 2 , 4A to 4F A method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure is exemplarily described.

[0061] In some embodiments, reference FIG. 4A to FIG. 4C As shown, the above step S220 includes: before forming the second dielectric layer, forming a first opening OP1 in the first dielectric layer 321, the first opening OP1 exposing the conductive structure 301; the above step S230 includes: forming a first initial seed layer 331S covering the sidewall and bottom of the first opening OP1; the above step S240 includes: before forming the second dielectric layer, performing a first induction treatment on the first initial seed layer 331S to form a first seed layer 331, wherein the number of crystal nuclei on the surface of the first seed layer 331 is greater than the number of crystal nuclei on the surface of the first initial seed layer 331S; the above step S250 includes: based on the first seed layer 331, forming a first interconnect structure 341 in the first opening OP1.

[0062] Exemplarily, a patterned first photoresist layer (not shown) is formed on the surface of the first dielectric layer 321 facing away from the substrate, and the first dielectric layer 321 is etched based on the patterned first photoresist layer until the conductive structure 301 is exposed, thereby forming a conductive structure 302 in the first dielectric layer 321. Figure 4A The first opening OP1 shown in FIG. 1 is formed by vacuum sputtering. Figure 4A The first preliminary seed layer 331S shown conformally covers the surface exposed by the first opening OP1 . The material of the first preliminary seed layer 331S includes at least one of titanium and copper.

[0063] Reference Figure 4B As shown, the first initial seed layer 331S is subjected to the first irradiation induction IT1 by in-situ heavy ion helium (He) to form the first seed layer 331. The number of crystal nuclei on the surface of the first initial seed layer 331S after the first irradiation induction IT1 is greater than the number of crystal nuclei on the surface of the first initial seed layer 331S before the first irradiation induction IT1, that is, the number of crystal nuclei on the surface of the first seed layer 331 is greater than the number of crystal nuclei on the surface of the first initial seed layer 331S. It can be understood that the first seed layer 331 is the first initial seed layer 331S after the first induction treatment, and the defect concentration of the first seed layer 331 is greater than the defect concentration of the first initial seed layer 331S. For irradiation induction and its principle, please refer to the relevant description in the previous text.

[0064] Reference Figure 4C As shown, metal is electroplated in the first opening OP1 where the first seed layer 331 is formed to form a first interconnection structure 341 in the first opening OP1, and the first interconnection structure 341 connects the first seed layer 331. The material of the first interconnection structure 341 includes at least one of copper, cobalt, and ruthenium.

[0065] In some embodiments, reference FIG. 4D to FIG. 4F As shown, the above step S220 includes: after forming the second dielectric layer 322, forming a second opening OP2 in the second dielectric layer 322, the second opening OP2 exposing the first seed layer 331 and the first interconnect structure 341; the above step S230 also includes: forming a second initial seed layer 332S covering the sidewall and bottom of the second opening OP2; the above step S240 includes: performing a second induction treatment on the second initial seed layer 332S to form a second seed layer 332, wherein the number of crystal nuclei on the surface of the second seed layer 332 is greater than the number of crystal nuclei on the surface of the second initial seed layer 332S; the above step S250 includes: based on the second seed layer 332, forming a second interconnect structure 342 in the second opening OP2.

[0066] For example, in Figure 4CA second dielectric layer 322 is deposited on the structure shown in FIG. 1 , a patterned second photoresist layer (not shown in the figure) is formed on the surface of the second dielectric layer 322 facing away from the first dielectric layer 321, and the second dielectric layer 322 is etched based on the patterned second photoresist layer until the first interconnect structure 341 is exposed, thereby forming a structure as shown in FIG. 1 in the second dielectric layer 322. Figure 4D The second opening OP2 shown in FIG. 1 is formed by vacuum sputtering. Figure 4D The second initial seed layer 332S shown conformally covers the second dielectric layer 322 and the surface exposed by the second opening OP2. The material of the second initial seed layer 332S includes at least one of titanium and copper.

[0067] Reference Figure 4E As shown, in-situ heavy ion helium (He) is used to perform a second irradiation induction IT2 on the second initial seed layer 332S to form a second seed layer 332. The number of crystal nuclei on the surface of the second initial seed layer 332S after the second irradiation induction IT2 is greater than the number of crystal nuclei on the surface of the second initial seed layer 332S before the second irradiation induction IT2, that is, the number of crystal nuclei on the surface of the second seed layer 332 is greater than the number of crystal nuclei on the surface of the second initial seed layer 332S. It can be understood that the seed layer 330 includes a first seed layer 331 and a second seed layer 332, and the second seed layer 332 is the second initial seed layer 332S after the second induction treatment, and the defect concentration of the second seed layer 332 is greater than the defect concentration of the second initial seed layer 332S. For irradiation induction and its principle, please refer to the relevant description above.

[0068] Reference Figure 4F As shown, metal is electroplated in the second opening OP2 formed with the second seed layer 332 to form a second interconnect structure 342 in the second opening OP2, and the second interconnect structure 342 connects the second seed layer 332. It can be understood that the interconnect structure 340 includes a first interconnect structure 341 and a second interconnect structure 342, and the material of the second interconnect structure 342 includes at least one of copper, cobalt, and ruthenium. In practical applications, a planarization process such as chemical mechanical polishing can also be used to remove the second seed layer 332 and the metal on the surface of the second dielectric layer 322, and the metal retained in the second opening OP2 constitutes the second interconnect structure 342.

[0069] Understandably, 4A to 4F The first interconnection structure 341 and the second interconnection structure 342 are formed step by step. In particular, when the cross-sectional size (e.g., diameter or radius) of the via hole is small, the first interconnection structure 341 and the second interconnection structure 342 are formed step by step to ensure that the via hole is well filled to reduce the formation of voids or gaps in the interconnection structure.

[0070] Based on the manufacturing method of the above semiconductor structure, an embodiment of the present disclosure provides a semiconductor structure, which can be manufactured using the method in any of the above embodiments.

[0071] Figure 5A and Figure 5B Schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure. Figure 5A As shown, the semiconductor structure includes: a substrate, a dielectric layer 320, an interconnection structure 340 and a seed layer 330. The dielectric layer 320 is located on one side of the substrate; the interconnection structure 340 extends from the surface of the dielectric layer 320 away from the substrate into the dielectric layer 320; the seed layer 330 wraps the sidewall and bottom of the interconnection structure 340, wherein the interconnection structure 340 is connected to the conductive structure 301 in the substrate through the seed layer 330.

[0072] In the embodiment of the present disclosure, by inducing treatment of the initial seed layer 330S, the formation of crystal nuclei can be promoted and the number of crystal nuclei can be increased. The increase in the number of crystal nuclei can improve the uniformity and continuity of the interconnection structure 340 subsequently formed on the seed layer 330, thereby improving the quality of the interconnection structure 340 and helping to improve the conductive performance of the interconnection structure 340.

[0073] In some embodiments, reference Figure 5A As shown, the substrate includes a pre-metal dielectric layer 310 and a conductive structure 301 located in the pre-metal dielectric layer 310. It should be noted that the substrate may also include Figure 5A Other film layers not shown in the figure, for example, the device layer located on the side of the pre-metal dielectric layer 310 away from the dielectric layer 320. For ease of understanding, Figure 5A Only the pre-metal dielectric layer 310 and the conductive structure 301 are shown. For the pre-metal dielectric layer 310 and the conductive structure 301, reference may be made to the related descriptions above.

[0074] In some embodiments, reference Figure 5A As shown, the dielectric layer 320 includes a first dielectric layer 321 and a second dielectric layer 322 sequentially stacked on one side of the substrate. Figure 5A As shown, the first dielectric layer 321 includes a dielectric barrier layer 3211 and a first insulating layer 3212, wherein the dielectric barrier layer 3211 is located between the pre-metal dielectric layer 310 and the first insulating layer 3212; the second dielectric layer 322 includes an isolation layer 3212 and a second insulating layer 3222, wherein the isolation layer 3212 is located between the first insulating layer 3212 and the second insulating layer 3222. The materials of the dielectric barrier layer 3211, the first insulating layer 3212, the isolation layer 3212, and the second insulating layer 3222 may refer to the related description above.

[0075] In some embodiments, reference Figure 5A and Figure 5B As shown, the interconnect structure 340 includes a first interconnect structure 341 and a second interconnect structure 342, wherein the first interconnect structure 341 extends from a surface of the first dielectric layer 321 away from the substrate to the first dielectric layer 321, and the second interconnect structure 342 extends from a surface of the second dielectric layer 322 away from the first dielectric layer 321 to the second dielectric layer 322; the seed layer 330 includes a first seed layer 331 and a second seed layer 332, wherein the first seed layer 331 wraps the side wall and the bottom of the first interconnect structure 341, and the second seed layer 332 wraps the side wall and the bottom of the second interconnect structure 342.

[0076] In some embodiments, reference Figure 5B As shown, the cross-sectional dimension of the second interconnect structure 342 is greater than or equal to the cross-sectional dimension of the first interconnect structure 341 .

[0077] In some embodiments, the material of the seed layer 330 includes at least one of tantalum nitride, tantalum, and copper; the material of the interconnect structure 340 includes at least one of copper and cobalt.

[0078] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a dielectric layer on one side of the substrate; forming an opening in a dielectric layer, the opening exposing a conductive structure in the substrate; forming an initial seed layer covering the sidewalls and the bottom of the opening; Performing an induction treatment on the initial seed layer to form a seed layer, wherein the number of crystal nuclei on the surface of the seed layer is greater than the number of crystal nuclei on the surface of the initial seed layer; Based on the seed layer, an interconnect structure is formed in the opening.

2. The manufacturing method according to claim 1, characterized in that: The step of forming a dielectric layer on one side of the substrate comprises: forming a first dielectric layer and a second dielectric layer stacked in sequence on one side of the substrate; The step of forming an opening in the dielectric layer comprises: Before forming the second dielectric layer, forming a first opening in the first dielectric layer, wherein the first opening exposes the conductive structure; After forming the second dielectric layer, a second opening is formed in the second dielectric layer, wherein a cross-sectional dimension of the second opening is greater than or equal to a cross-sectional dimension of the first opening, and the second opening and the first opening constitute the opening.

3. The manufacturing method according to claim 2, characterized in that: The forming of an initial seed layer covering the sidewall and the bottom of the opening comprises: forming a first initial seed layer covering the sidewalls and the bottom of the first opening; The induction treatment of the initial seed layer to form the seed layer includes: Before forming the second dielectric layer, performing a first induction treatment on the first initial seed layer to form a first seed layer, wherein the number of crystal nuclei on the surface of the first seed layer is greater than the number of crystal nuclei on the surface of the first initial seed layer; The step of forming an interconnect structure in the opening based on the seed layer comprises: Based on the first seed layer, a first interconnect structure is formed in the first opening.

4. The manufacturing method according to claim 3, characterized in that: The second opening exposes the first seed layer and the first interconnect structure; The forming of an initial seed layer covering the sidewalls and the bottom of the opening further includes: forming a second initial seed layer covering the sidewalls and the bottom of the second opening; The induction treatment of the initial seed layer to form the seed layer includes: Performing a second induction treatment on the second initial seed layer to form a second seed layer, wherein the number of crystal nuclei on the surface of the second seed layer is greater than the number of crystal nuclei on the surface of the second initial seed layer; The step of forming an interconnect structure in the opening based on the seed layer comprises: Based on the second seed layer, a second interconnect structure is formed in the second opening.

5. The manufacturing method according to claim 2, characterized in that: The step of forming an opening in the dielectric layer further comprises: Before forming the second dielectric layer, forming a sacrificial layer in the first opening, wherein the second opening exposes the sacrificial layer; Based on the second opening, the sacrificial layer is removed so that the second opening is connected to the first opening.

6. The manufacturing method according to claim 1, characterized in that: The induction treatment includes at least one of radiation induction, laser induction, electron beam induction and light induction.

7. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method according to any one of claims 1 to 6; the semiconductor structure comprises: substrate; a dielectric layer, the dielectric layer being located on one side of the substrate; an interconnect structure extending from a surface of the dielectric layer facing away from the substrate into the dielectric layer; A seed layer wraps the sidewall and the bottom of the interconnect structure, wherein the interconnect structure is connected to the conductive structure in the substrate through the seed layer.

8. The semiconductor structure according to claim 7, characterized in that: The dielectric layer includes a first dielectric layer and a second dielectric layer sequentially stacked on one side of the substrate; The interconnect structure comprises a first interconnect structure and a second interconnect structure, wherein the first interconnect structure extends from a surface of the first dielectric layer facing away from the substrate into the first dielectric layer, and the second interconnect structure extends from a surface of the second dielectric layer facing away from the first dielectric layer into the second dielectric layer; The seed layer includes a first seed layer and a second seed layer, wherein the first seed layer wraps around the sidewall and the bottom of the first interconnect structure, and the second seed layer wraps around the sidewall and the bottom of the second interconnect structure.

9. The semiconductor structure according to claim 8, characterized in that: A cross-sectional dimension of the second interconnect structure is greater than or equal to a cross-sectional dimension of the first interconnect structure.

10. The semiconductor structure according to claim 7, characterized in that: The material of the seed layer includes at least one of tantalum nitride, tantalum and copper; the material of the interconnect structure includes at least one of copper and cobalt.

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