Preparation method of semiconductor structure and semiconductor structure
By forming a multi-layer isolation material layer in the deep trench isolation structure and selectively removing it, the problem of difficulty in ensuring uniformity during filling and planarization is solved, and the effect of reducing process difficulty and improving product yield is achieved.
Patent Information
- Application Number
- CN202510114063.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2025-04-25
AI Technical Summary
The deep trench isolation structure has problems of difficulty in ensuring uniformity during filling and planarization, resulting in poor structural performance and difficulty in subsequent process flow.
By forming isolation trenches in the substrate and forming first and second isolation material layers therein, target trenches are formed by removing part of the material layers and further reducing the material layer thickness, thereby reducing the difficulty of the planarization process.
It has achieved the reduction of process difficulty and improved product yield, and no new light cover is required, effectively saving costs.
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Figure CN119890137A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art
[0002] Deep Trench Isolation (DTI) is a key structure for device isolation in integrated circuits. The main challenges faced in its preparation process are the formation, filling and planarization of DTI trenches.
[0003] The filling of deep trench isolation structures with high aspect ratios usually requires the deposition of thicker filling dielectrics, and it is difficult to achieve good uniformity with chemical mechanical planarization. Therefore, good filling will make planarization more difficult, and the planarization process affects the performance of the structure and whether the subsequent process flow can be completed smoothly.
[0004] However, although the safety of the planarization process is guaranteed by removing the edges and taking the center of the wafer, thereby ensuring the yield, it leads to a lot of waste and increases the cost. Summary of the invention
[0005] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0006] According to some embodiments, the present application provides a method for preparing a semiconductor structure, which, in some embodiments, includes:
[0007] providing a substrate;
[0008] forming an isolation trench in the substrate;
[0009] forming a first isolation material layer and an initial trench, wherein the first isolation material layer at least covers the inner surface of the isolation trench, and the initial trench is located above the isolation trench and on the outer surface of the first isolation material layer;
[0010] removing at least a portion of the first isolation material layer located on the surface of the initial trench to form a target trench;
[0011] A second isolation layer is formed in the target trench, and a portion of the first isolation material layer is removed to form a first isolation layer.
[0012] In the method for preparing the semiconductor structure of the above embodiment, an isolation groove is formed in the substrate, a first isolation material layer at least covering the inner surface of the isolation groove and an initial groove located above the isolation groove are formed, and a target groove is formed by removing part of the first isolation material layer located on the surface of the initial groove, thereby reducing the thickness of the semiconductor structure as a whole, while ensuring the structural integrity of the groove area, and no additional mask is required, which can effectively save costs; then a second isolation layer is formed in the target groove, and part of the first isolation material layer is removed to form a first isolation layer, and part of the first isolation material layer is selectively removed through a second removal process, thereby reducing the difficulty of the planarization process, and the sealing integrity of the groove area can be protected again. In this way, the first isolation layer and the second isolation layer are formed by the above method, which can reduce the process difficulty and improve the product yield.
[0013] In some embodiments, forming a second isolation layer in a target trench and removing a portion of the first isolation material layer to form a first isolation layer includes:
[0014] forming a second isolation material layer, wherein the second isolation material layer is at least located in the target trench;
[0015] A portion of the second isolation material layer and a portion of the first isolation material layer are removed to form a second isolation layer and a first isolation layer.
[0016] In some embodiments, the second isolation material layer is also located on the top surface of the first isolation material layer; removing a portion of the second isolation material layer and a portion of the first isolation material layer to form the second isolation layer and the first isolation layer includes:
[0017] Removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer, wherein the second initial isolation layer and the first initial isolation layer have target patterns therein;
[0018] A portion of the second initial isolation layer and a portion of the first initial isolation layer are removed to form a second isolation layer and a first isolation layer.
[0019] In some embodiments, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer includes:
[0020] forming a patterned mask layer on the top surface of the second isolation material layer, wherein the patterned mask layer has a target pattern;
[0021] Based on the patterned mask layer, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer having a target pattern;
[0022] The patterned mask layer is removed.
[0023] In some embodiments, removing a portion of the second initial isolation layer and a portion of the first initial isolation layer to form a second isolation layer and a first isolation layer includes:
[0024] A planarization process is adopted to remove a portion of the second initial isolation layer and a portion of the first initial isolation layer to form a second isolation layer and a first isolation layer.
[0025] In some embodiments, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer includes:
[0026] An anti-reflective etching process is adopted to remove a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer.
[0027] In some embodiments, before forming the first isolation material layer and the initial trench, the method further includes: forming a dielectric layer on the top surface of the substrate, wherein the dielectric layer exposes the surface of the isolation trench.
[0028] In some embodiments, forming an isolation trench in a substrate and forming a dielectric layer on a top surface of the substrate includes:
[0029] forming a dielectric material layer on the top surface of the substrate;
[0030] A portion of the substrate and a portion of the dielectric material layer are removed to form a dielectric layer and an isolation trench.
[0031] In some embodiments, forming a first isolation material layer includes:
[0032] forming a first isolation material layer on the top surface of the dielectric layer and the surface of the isolation trench;
[0033] Removing a portion of the first isolation material layer to form a first isolation layer includes:
[0034] A portion of the first isolation material layer located on the top surface of the dielectric layer is removed to expose the top surface of the dielectric layer, and the remaining first isolation material layer constitutes a first isolation layer.
[0035] According to some embodiments, the present application further provides a semiconductor structure, which is prepared using the method for preparing the semiconductor structure in any of the above embodiments.
[0036] In the semiconductor structure of the above embodiment, when forming the first isolation layer and the second isolation layer, a portion of the first isolation material layer located on the surface of the initial groove is removed to form a target groove, thereby reducing the thickness of the semiconductor structure as a whole, while ensuring the structural integrity of the groove area, and no additional photomask is required, which can effectively save costs; then a second isolation layer is formed in the target groove, and a portion of the first isolation material layer is removed to form the first isolation layer, and a portion of the first isolation material layer is selectively removed through a second removal process, thereby reducing the difficulty of the planarization process, and the sealing integrity of the groove area can be protected again. Therefore, the above semiconductor structure has a low process difficulty and a high product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present application;
[0038] Figure 2 A schematic cross-sectional view of a structure obtained from step S10 to step S50 in a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0039] Figure 3 A schematic cross-sectional view of a structure obtained in step S70 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0040] Figure 4 A schematic cross-sectional view of a structure obtained in step S91 of a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0041] Figure 5 A schematic cross-sectional view of a structure obtained in step S9221 in a method for preparing a semiconductor structure provided in an embodiment of the present application;
[0042] Figure 6 A schematic cross-sectional view of a structure obtained in step S9212 in a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0043] Figure 7 A schematic cross-sectional view of a structure obtained in step S9213 and step S82 in a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0044] Figure 8 This is a schematic cross-sectional view of a structure obtained in step S922 of a method for preparing a semiconductor structure provided in one embodiment of the present application.
[0045] Explanation of the accompanying drawings: 10, substrate; 11, isolation trench; 12, dielectric layer; 21, initial trench; 22, target trench; second isolation layer; 31, first isolation layer; 301, first isolation material layer; 311, first initial isolation layer; 32, second isolation layer; 302, second isolation material layer; 321, second initial isolation layer; 41, patterned mask layer. DETAILED DESCRIPTION
[0046] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.
[0048] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.
[0049] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.
[0050] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0051] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0052] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.
[0053] As a key device isolation structure in integrated circuits, deep trench isolation (DTI) is important in that it can effectively improve the electrical isolation between devices, thereby reducing leakage current, improving integration and overall performance. However, it still faces significant challenges in its production process, mainly in two aspects: trench formation and filling, and subsequent planarization.
[0054] First, the trench formation process of the deep trench isolation structure requires high precision and depth control, and usually requires specific etching technology to achieve deep and narrow trenches. Due to the high aspect ratio requirement, trench filling is particularly critical. The selection of filling materials and the deposition process must be able to effectively fill the deep trenches to avoid pores or defects. Especially when the filling medium exceeds 2um, the adapted deposition technology such as chemical vapor deposition faces the problem of uniformity. At the same time, in order to prevent uneven filling due to the high aspect ratio, multi-layer deposition and subsequent processing are often required.
[0055] Secondly, the planarization process also plays a vital role in the production of the entire deep trench isolation structure. This process not only affects the final performance of the deep trench isolation structure, but also affects the smooth progress of subsequent processes. Whether the planarization can achieve good uniformity and effect directly determines the reliability of the device. Due to the height difference generated during the filling process, the difficulty of the planarization process increases sharply, often resulting in the surface failing to achieve the ideal flatness, which affects the subsequent lithography and chemical treatment processes.
[0056] The existing solution strategy includes adjusting the position and number of zero marks to ensure safety and stability in the process. In addition, in order to improve the yield rate, many manufacturers will choose to take the chips from the center of the wafer. Although this strategy can ensure product quality to a certain extent, it also causes waste of raw materials and affects cost-effectiveness.
[0057] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0058] See also Figure 1 The present application provides a method for preparing a semiconductor structure, which includes the following steps.
[0059] Step S10, providing a substrate;
[0060] Step S30, forming an isolation trench in the substrate;
[0061] Step S50, forming a first isolation material layer and an initial trench, wherein the first isolation material layer at least covers the inner surface of the isolation trench, and the initial trench is located above the isolation trench and on the outer surface of the first isolation material layer;
[0062] Step S70, removing at least a portion of the first isolation material layer located on the surface of the initial trench to form a target trench;
[0063] Step S90 , forming a second isolation layer in the target trench, and removing a portion of the first isolation material layer to form a first isolation layer.
[0064] In the method for preparing the semiconductor structure of the above embodiment, an isolation groove is formed in the substrate, a first isolation material layer at least covering the inner surface of the isolation groove and an initial groove located above the isolation groove are formed, and a target groove is formed by removing part of the first isolation material layer located on the surface of the initial groove, thereby reducing the thickness of the semiconductor structure as a whole, while ensuring the structural integrity of the groove area, and no additional mask is required, which can effectively save costs; then a second isolation layer is formed in the target groove, and part of the first isolation material layer is removed to form a first isolation layer, and part of the first isolation material layer is selectively removed through a second removal process, thereby reducing the difficulty of the planarization process, and the sealing integrity of the groove area can be protected again. In this way, the first isolation layer and the second isolation layer are formed by the above method, which can reduce the process difficulty and improve the product yield.
[0065] In some embodiments, before step S50, forming the first isolation material layer and the initial trench, the method further includes:
[0066] Step S40 , forming a dielectric layer on the top surface of the substrate, wherein the dielectric layer exposes the surface of the isolation trench.
[0067] In some embodiments, step S30, forming an isolation trench in the substrate, and step S40, forming a dielectric layer on the top surface of the substrate, include:
[0068] Step S41, forming a dielectric material layer on the top surface of the substrate;
[0069] Step S42: removing a portion of the substrate and a portion of the dielectric material layer to form a dielectric layer and an isolation trench.
[0070] In some embodiments, step S50, forming a first isolation material layer, includes:
[0071] Step S51 , forming a first isolation material layer on the top surface of the dielectric layer and the surface of the isolation trench.
[0072] In some embodiments, step S90, removing a portion of the first isolation material layer to form a first isolation layer, includes:
[0073] Step S901 , removing a portion of the first isolation material layer located on the top surface of the dielectric layer to expose the top surface of the dielectric layer, and the remaining first isolation material layer constitutes a first isolation layer.
[0074] In some embodiments, step S90, forming a second isolation layer in the target trench and removing a portion of the first isolation material layer to form a first isolation layer, includes:
[0075] Step S91, forming a second isolation material layer, wherein the second isolation material layer is at least located in the target trench;
[0076] Step S92 , removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second isolation layer and a first isolation layer.
[0077] In some embodiments, the second isolation material layer is also located on the top surface of the first isolation material layer; step S92, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second isolation layer and a first isolation layer, includes:
[0078] Step S921, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer, wherein the second initial isolation layer and the first initial isolation layer have a target pattern;
[0079] Step S922: remove a portion of the second initial isolation layer and a portion of the first initial isolation layer to form a second isolation layer and a first isolation layer.
[0080] In some embodiments, step S921, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer, includes:
[0081] Step S9211, forming a patterned mask layer on the top surface of the second isolation material layer, wherein the patterned mask layer has a target pattern;
[0082] Step S9212: Based on the patterned mask layer, remove a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer having a target pattern;
[0083] Step S9213, removing the patterned mask layer.
[0084] In some embodiments, step S922, removing a portion of the second initial isolation layer and a portion of the first initial isolation layer to form a second isolation layer and a first isolation layer, includes:
[0085] Step S9221: Use a planarization process to remove a portion of the second initial isolation layer and a portion of the first initial isolation layer to form a second isolation layer and a first isolation layer.
[0086] In some embodiments, step S921, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer, includes:
[0087] Step S921a: removing a portion of the second isolation material layer and a portion of the first isolation material layer by using an anti-reflective etching process to form a second initial isolation layer and a first initial isolation layer.
[0088] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
[0089] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figures 2 to 8 The method is described in detail.
[0090] like Figure 2 As shown, in step S10, a substrate 10 is provided. As an example, in the embodiment of the present disclosure, the substrate 10 can be composed of a semiconductor material, an insulating material, a conductor material or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10 or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator, etc. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on the substrate 10, so the type of substrate 10 should not limit the scope of protection of the present disclosure.
[0091] like Figure 2As shown, in step S30, an isolation trench 11 is formed in the substrate 10. For example, the isolation trench 11 has a high aspect ratio, and a high aspect ratio can enhance the electrical isolation effect between devices, reduce leakage current, and improve the performance of the device. For example, the aspect ratio of the isolation trench 11 ranges from 5:1 to 10:1. For example, the aspect ratio of the isolation trench 11 is 5:1 or 10:1, etc.
[0092] In some embodiments, before step S50, forming the first isolation material layer 301 and the initial trench 21, the method further includes:
[0093] Step S40 , forming a dielectric layer 12 on the top surface of the substrate 10 , wherein the dielectric layer 12 exposes the surface of the isolation trench 11 .
[0094] It should be noted that step S40 may be performed before, after or simultaneously with forming the isolation trench 11 in step S30 .
[0095] In some embodiments, step S30, forming an isolation trench 11 in the substrate 10, and step S40, forming a dielectric layer 12 on the top surface of the substrate 10, include:
[0096] Step S41, forming a dielectric material layer (not shown) on the top surface of the substrate 10;
[0097] Step S42 , removing a portion of the substrate 10 and a portion of the dielectric material layer to form a dielectric layer 12 and an isolation trench 11 .
[0098] For example, the dielectric layer 12 covers the top surface of the substrate 10, and the substrate 10 not covered by the dielectric layer 12 has an opening, and the width of the opening area of the substrate 10 is greater than or equal to the width of the opening of the isolation trench 11. In some embodiments, the width of the opening area of the substrate 10 is a preset width, and the opening area of the substrate 10 has a certain depth, which is less than the depth of the isolation trench 11, so as to form a shallower filling trench 13.
[0099] like Figure 2 As shown, in some embodiments, step S50, forming a first isolation material layer 301, includes:
[0100] Step S51 , forming a first isolation material layer 301 on the top surface of the dielectric layer 12 and the surface of the isolation trench 11 .
[0101] For example, in an embodiment in which the substrate 10 has a filled trench 13, the first isolation material layer 301 is also located in the filled trench 13. It can be understood that the first isolation material layer 301 located in the filled trench 13 also has a preset width.
[0102] like Figure 3As shown, in step S70 , at least a portion of the first isolation material layer 301 located on the surface of the initial trench 21 is removed to form a target trench 22 .
[0103] For example, a maskless etching process (Blank etch) can be used to remove a portion of the first isolation material layer 301 located on the surface of the initial trench 21 to form a target trench 22. Conventional etching methods usually require the preparation of a mask, which not only increases the cost but also may introduce additional defects. In the etching process of the maskless etching process, no additional mask needs to be made, which simplifies the process flow and reduces production time and cost.
[0104] It can be understood that, because the surface of the deep trench isolation structure after filling is usually not flat, it is difficult to reduce the film thickness of the structure surface to the maximum extent by a single etching method. In step S70, at least part of the first isolation material layer 301 located on the surface of the initial trench 21 is removed, which can reduce the thickness of the semiconductor structure as a whole, facilitate the subsequent planarization process, improve the efficiency of the planarization process, and help improve the flatness of the final surface. At the same time, the structural integrity of the trench area is guaranteed, and no additional mask is required, which can effectively save costs.
[0105] Please combine Figures 4 to 8 It is understood that in some embodiments, in step S90, a portion of the first isolation material layer 301 is removed to form the first isolation layer 31, and a portion of the first isolation material layer 301 is selectively removed through a second removal process, thereby reducing the difficulty of the planarization process and protecting the sealing integrity of the trench area again. In this way, the process difficulty can be reduced and the product yield can be improved.
[0106] In some embodiments, step S90 , removing a portion of the first isolation material layer 301 to form a first isolation layer 31 , includes the following steps.
[0107] Step S901 , removing a portion of the first isolation material layer 301 located on the top surface of the dielectric layer 12 to expose the top surface of the dielectric layer 12 , and the remaining first isolation material layer 301 constitutes a first isolation layer 31 .
[0108] In some embodiments, step S90 of forming a second isolation layer 32 in the target trench 22 and removing a portion of the first isolation material layer 301 to form the first isolation layer 31 further includes the following steps.
[0109] like Figure 4 As shown, in step S91 , a second isolation material layer 302 is formed, and the second isolation material layer 302 is at least located in the target trench 22 .
[0110] For example, the second isolation material layer 302 can be formed by chemical vapor deposition or physical vapor deposition (PVD) processes, and the chemical vapor deposition process method can include one or more of atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).
[0111] like Figures 5 to 8 As shown, in step S92 , a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 are removed to form a second isolation layer 32 and a first isolation layer 31 .
[0112] In some embodiments, the second isolation material layer 302 is also located on the top surface of the first isolation material layer 301. In the embodiment where the second isolation material layer 302 is also located on the top surface of the first isolation material layer 301, step S92, removing a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 to form the second isolation layer 32 and the first isolation layer 31, includes the following steps S921 and S922.
[0113] like Figures 5 to 7 As shown, in step S921, a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 are removed to form a second initial isolation layer 321 and a first initial isolation layer 311, wherein the second initial isolation layer 321 and the first initial isolation layer 311 have target patterns therein;
[0114] like Figure 8 As shown, in step S922 , a portion of the second initial isolation layer 321 and a portion of the first initial isolation layer 311 are removed to form the second isolation layer 32 and the first isolation layer 31 .
[0115] In some embodiments, step S921 , removing a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 to form a second initial isolation layer 321 and a first initial isolation layer 311 , includes the following steps S9211 to S9213 .
[0116] like Figure 5 As shown, in step S9211, a patterned mask layer 41 is formed on the top surface of the second isolation material layer 302, and the patterned mask layer 41 has a target pattern.
[0117] For example, a portion of the target pattern in the patterned mask layer 41 directly above the isolation trench 11 has a preset width.
[0118] For example, step S9211 also includes the step of coating a photoresist material layer on the top surface of the second isolation material layer 302. The photoresist material layer undergoes a series of steps such as exposure and development to form a graphic patterned mask layer 41. The photoresist can be a positive photoresist or a negative photoresist, and the development method can be a positive development or a negative development.
[0119] like Figure 6 As shown, in step S9212, based on the patterned mask layer 41, a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 are removed to form a second initial isolation layer 321 and a first initial isolation layer 311 having a target pattern.
[0120] In some embodiments, the width of the second preliminary isolation layer 321 is the same as the width of the first preliminary isolation layer 311 located within the filling trench 13 .
[0121] For example, a selective etching process may be used to remove part of the second isolation material layer 302 and part of the first isolation material layer 301. For example, a dry etching process or a wet etching process may be used. Thus, by removing part of the second isolation material layer 302 and part of the first isolation material layer 301 through a selective etching process, the volume of the structure to be removed in a subsequent planarization process can be reduced, thereby reducing the difficulty of the planarization process and improving the effect of the planarization process.
[0122] like Figure 6 As shown, in some embodiments, step S921, removing a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 to form a second initial isolation layer 321 and a first initial isolation layer 311, includes:
[0123] Step S921a: removing a portion of the second isolation material layer 302 and a portion of the first isolation material layer 301 by using an anti-reflective etching process to form a second initial isolation layer 321 and a first initial isolation layer 311 .
[0124] It is understood that by using anti-reflective coatings or materials, the reflection of light can be reduced, ensuring the correct absorption of light during the photolithography process, improving the accuracy of pattern transfer, and improving the overall yield by reducing defects and non-uniformity.
[0125] like Figure 7 As shown, step S9213, removing the patterned mask layer 41.
[0126] For example, the patterned mask layer 41 may be removed by an ashing process.
[0127] In some embodiments, step S922, removing a portion of the second initial isolation layer 321 and a portion of the first initial isolation layer 311 to form the second isolation layer 32 and the first isolation layer 31, includes:
[0128] Step S9221 , using a planarization process to remove a portion of the second initial isolation layer 321 and a portion of the first initial isolation layer 311 to form a second isolation layer 32 and a first isolation layer 31 .
[0129] It can be understood that, in the above embodiment, step 70 reduces the thickness of the semiconductor structure of the entire structure by removing part of the first isolation material layer 301, thereby reducing the difficulty of the planarization process in step S9221. In addition, in step S921, a part of the second isolation material layer 302 and a part of the first isolation material layer 301 are removed by a selective etching process, thereby further reducing the volume of the structure removed by the planarization process in step S9221, thereby further reducing the difficulty of the planarization process and improving the effect of the planarization process.
[0130] See also Figure 8 According to some embodiments, the present application further provides a semiconductor structure, which is prepared by the method for preparing the semiconductor structure in any of the above embodiments. Since a better preparation method is used to prepare the semiconductor structure, the beneficial effects of the preparation method of the above semiconductor structure are also possessed by the semiconductor structure in the embodiments of the present application, which will not be described in detail here.
[0131] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0132] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming an isolation trench in the substrate; forming a first isolation material layer and an initial trench, wherein the first isolation material layer at least covers the inner surface of the isolation trench, and the initial trench is located above the isolation trench and on the outer surface of the first isolation material layer; removing at least a portion of the first isolation material layer located on the surface of the initial trench to form a target trench; A second isolation layer is formed in the target trench, and a portion of the first isolation material layer is removed to form a first isolation layer.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The step of forming a second isolation layer in the target trench and removing a portion of the first isolation material layer to form a first isolation layer includes: forming a second isolation material layer, wherein the second isolation material layer is at least located in the target trench; A portion of the second isolation material layer and a portion of the first isolation material layer are removed to form the second isolation layer and the first isolation layer.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The second isolation material layer is also located on the top surface of the first isolation material layer; The removing a portion of the second isolation material layer and a portion of the first isolation material layer to form the second isolation layer and the first isolation layer comprises: removing a portion of the second isolation material layer and a portion of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer, wherein the second initial isolation layer and the first initial isolation layer have target patterns therein; A portion of the second initial isolation layer and a portion of the first initial isolation layer are removed to form the second isolation layer and the first isolation layer.
4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The removing part of the second isolation material layer and part of the first isolation material layer to form a second initial isolation layer and a first initial isolation layer comprises: forming a patterned mask layer on the top surface of the second isolation material layer, wherein the patterned mask layer has the target pattern; Based on the patterned mask layer, removing a portion of the second isolation material layer and a portion of the first isolation material layer to form the second initial isolation layer and the first initial isolation layer having the target pattern; The patterned mask layer is removed.
5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The removing part of the second initial isolation layer and part of the first initial isolation layer to form the second isolation layer and the first isolation layer comprises: A planarization process is adopted to remove a portion of the second initial isolation layer and a portion of the first initial isolation layer to form the second isolation layer and the first isolation layer.
6. The method for preparing a semiconductor structure according to claim 3, characterized in that: The removing a portion of the second isolation material layer and a portion of the first isolation material layer to form the second initial isolation layer and the first initial isolation layer comprises: An anti-reflective etching process is adopted to remove a portion of the second isolation material layer and a portion of the first isolation material layer to form the second initial isolation layer and the first initial isolation layer.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the first isolation material layer and the initial trench, the method further includes: A dielectric layer is formed on the top surface of the substrate, wherein the dielectric layer exposes the surface of the isolation trench.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The step of forming an isolation trench in the substrate and forming a dielectric layer on the top surface of the substrate comprises: forming a dielectric material layer on the top surface of the substrate; A portion of the substrate and a portion of the dielectric material layer are removed to form the dielectric layer and the isolation trench.
9. The method for preparing a semiconductor structure according to claim 7, characterized in that: Forming a first isolation material layer, comprising: forming the first isolation material layer on the top surface of the dielectric layer and the surface of the isolation trench; The removing part of the first isolation material layer to form a first isolation layer includes: A portion of the first isolation material layer located on the top surface of the dielectric layer is removed to expose the top surface of the dielectric layer, and the remaining first isolation material layer constitutes a first isolation layer.
10. A semiconductor structure, characterized in that: The semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.