A semiconductor structure and a method of forming the same

Abstract

The present disclosure provides a semiconductor structure and a forming method thereof. The forming method comprises: providing a first dielectric layer; forming a first protective layer and a conductive layer on the first dielectric layer; removing part of the conductive layer to form a plurality of cavities penetrating through the conductive layer and exposing the first protective layer; the cavities divide the conductive layer into a plurality of conductive structures; forming a sacrificial layer in the cavities; forming a second protective layer on the sacrificial layer and the conductive structures; removing part of the second protective layer on the sacrificial layer to form an opening exposing the sacrificial layer; and removing the sacrificial layer from the opening.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As the size of semiconductor structures continues to shrink, capacitive coupling between adjacent interconnects, metal lines, or other components increases, causing resistance-capacitance (RC) delay (RC delay) to become more severe, thereby affecting the performance of the semiconductor structure. Methods for addressing the above-mentioned issues include using low-k dielectric materials to form dielectric layers or forming cavities in dielectric layers. Compared to low-k dielectric materials, air has a lower dielectric constant, so structures with cavities can significantly improve the RC delay problem.

[0003] However, the cavity ratio formed in the related art is relatively small, making the effect of improving the resistance and capacitance delay less obvious. How to increase the cavity ratio and thus improve the performance of the semiconductor structure has become an urgent problem to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0005] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0007] providing a first dielectric layer;

[0008] forming a first protective layer and a conductive layer on the first protective layer on the first dielectric layer;

[0009] removing a portion of the conductive layer to form a plurality of cavities penetrating the conductive layer and exposing the first protective layer; the cavities divide the conductive layer into a plurality of conductive structures;

[0010] forming a sacrificial layer in the cavity;

[0011] forming a second protective layer on the sacrificial layer and the conductive structure;

[0012] removing a portion of the second protective layer on the sacrificial layer to form an opening exposing the sacrificial layer;

[0013] The sacrificial layer is removed from the opening.

[0014] In an optional embodiment, the materials of the first protective layer and the second protective layer include at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride;

[0015] The material of the sacrificial layer includes at least one of the following: silicon oxide and spin-on hard mask material.

[0016] In an optional embodiment, removing the sacrificial layer from the opening includes:

[0017] The sacrificial layer is removed from the opening using a wet etching solution.

[0018] In an optional embodiment, the method further includes:

[0019] Before forming the sacrificial layer in the cavity, forming a third protective layer on the sidewall of the cavity and the surface of the conductive structure;

[0020] The forming of a sacrificial layer in the cavity comprises:

[0021] forming a sacrificial layer in the cavity having the third protective layer formed on the sidewall thereof;

[0022] The forming of a second protective layer on the sacrificial layer and the conductive structure includes:

[0023] A second protection layer is formed on the sacrificial layer and the third protection layer.

[0024] In an optional embodiment, the method further includes:

[0025] After removing the sacrificial layer from the opening, a fourth protection layer is formed on the sidewall of the cavity.

[0026] In an optional embodiment, the multiple conductive structures are arranged along a first direction, and each of the conductive structures extends along a second direction; the first direction is perpendicular to the second direction; and a plurality of openings are formed on the sacrificial layer in each of the cavities.

[0027] In an optional embodiment, the multiple openings on the sacrificial layer in each of the cavities are arranged along the second direction.

[0028] In an optional embodiment, the dimension between two adjacent conductive structures along the first direction is W1, the dimension of the opening along the first direction is W2, and the ratio of W2:W1 is in the range of 1:3 to 1:2.

[0029] In an optional embodiment, the method further includes:

[0030] After removing the sacrificial layer from the opening, a second dielectric layer is formed on the second protection layer and the opening.

[0031] In an optional embodiment, the method further includes:

[0032] Before providing the first dielectric layer, providing a third dielectric layer;

[0033] forming a plurality of first contact structures penetrating the third dielectric layer;

[0034] forming a fourth dielectric layer on the third dielectric layer; wherein the first dielectric layer is located on the fourth dielectric layer;

[0035] A plurality of second contact structures are formed penetrating the fourth dielectric layer, the first dielectric layer and the first protective layer; the first contact structures are in contact with the second contact structures, and the second contact structures are in contact with the conductive structures.

[0036] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including:

[0037] a first dielectric layer;

[0038] a first protective layer, located on the first dielectric layer;

[0039] a plurality of conductive structures, located on the first protective layer;

[0040] a plurality of cavities, each of the cavities being located between adjacent conductive structures;

[0041] a second protective layer, located on the conductive structure and the cavity;

[0042] The opening is located in the second protective layer and communicates with the cavity.

[0043] In an optional embodiment, the material of the first protective layer and the second protective layer includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0044] In an optional embodiment, the semiconductor structure further includes: a third protection layer located on the sidewall of the cavity and between the second protection layer and the conductive structure.

[0045] In an optional embodiment, the material of the third protective layer includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0046] In an optional embodiment, the semiconductor structure further includes: a fourth protection layer located on a sidewall of the cavity.

[0047] In an optional embodiment, a plurality of openings are formed on the sacrificial layer between every two adjacent conductive structures.

[0048] In the technical solution provided by the present disclosure, a first protective layer is formed between the first dielectric layer and the conductive layer, and a second protective layer is formed on the conductive layer. A portion of the second protective layer on the sacrificial layer is removed to form an opening, and the sacrificial layer is removed from the opening, thereby forming a cavity between the conductive structures. First, the first protective layer can protect the first dielectric layer, thereby preventing the first dielectric layer from being affected when the sacrificial layer in the cavity is removed. Second, by removing only a portion of the second protective layer on the sacrificial layer to form an opening exposing the sacrificial layer, a wet etching solution can contact the sacrificial layer and prevent a second dielectric layer formed on the second protective layer in a subsequent process from entering the formed cavity. Third, because the sacrificial layer can be completely removed, the proportion of the cavity ultimately formed between the conductive structures is relatively large, even reaching 100%. In addition, the proportion of the cavity formed in the embodiment of the present disclosure is not limited by the size of the adjacent conductive structures. Even when the size of the adjacent conductive structures is relatively large, a relatively large cavity can be formed, thereby significantly improving the resistance and capacitance delay problem between the adjacent conductive structures, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figures 1 to 3 A schematic structural diagram of a semiconductor structure forming process according to an embodiment of the present disclosure;

[0050] Figure 4 A schematic diagram showing the relationship between the ratio of cavities and the distance between adjacent conductive structures under different precursors provided in an embodiment of the present disclosure;

[0051] Figure 5 A schematic flow chart of a method for forming a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Figures 6 to 20 A schematic structural diagram of a semiconductor structure forming process according to another embodiment of the present disclosure;

[0053] Figures 21 to 23 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0055] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0056] In the drawings, like reference numerals refer to like elements throughout.

[0057] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Figures 1 to 3 A schematic diagram of the formation process of a semiconductor structure provided by an embodiment of the present disclosure. Figures 1 to 3 As shown, the formation process of the semiconductor structure may specifically include: referring to Figure 1 , providing a first silicon oxide layer, forming a first contact structure in the first silicon oxide layer; forming a silicon carbonitride layer and a second silicon oxide layer on the first silicon oxide layer, forming a second contact structure in the silicon carbonitride layer and the second silicon oxide layer; depositing a conductive layer, such as aluminum, on the second silicon oxide layer. Figure 2, using a dry etching process to remove part of the conductive layer to form grooves, which divide the conductive layer into multiple conductive structures. Figure 3 A third silicon oxide layer is filled in the groove using a deposition process, and a void is formed in the third silicon oxide layer between adjacent conductive structures by adjusting the process parameters during the deposition of the third silicon oxide layer, thereby forming a cavity.

[0060] The current cavity ratio between conductive structures is affected by the distance between two adjacent conductive structures (Space CD) and deposition process conditions. The cavity ratio here can be understood as follows: Figure 3 In the cross-sectional view shown in , the ratio of the area of ​​the cavity to the area of ​​the third silicon oxide layer between two adjacent conductive structures is shown in . The deposition process conditions here include the precursor.

[0061] Figure 4 Schematic diagram of the relationship between the ratio of cavities and the distance between two adjacent conductive structures under different precursors. Figure 4 As shown in the figure, when the precursors during deposition are tetrahydrosilane (SiH4), tetraethoxysilane (TEOS), and octamethylcyclotetrasiloxane (OMCTS), respectively, the proportion of cavities is different under the same Space CD. When the precursor is TEOS, the proportion of cavities formed is small when the Space CD is small or large. When the precursor is SiH4 or OMCTS, the proportion of cavities formed is relatively increased. However, under the three precursors, the greater the distance between two adjacent conductive structures, the lower the proportion of cavities. When the distance between two adjacent conductive structures is large, the proportion of cavities is not ideal, which makes the problem of resistance and capacitance delay between adjacent conductive structures more serious, thereby affecting the performance of the semiconductor structure.

[0062] In this regard, an embodiment of the present disclosure provides a method for forming a semiconductor structure. Figure 5 Schematic diagram of the process of forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 5 As shown, the method for forming a semiconductor structure includes the following steps:

[0063] Step 1001: providing a first dielectric layer;

[0064] Step 1002: forming a first protective layer and a conductive layer on the first protective layer on the first dielectric layer;

[0065] Step 1003: removing a portion of the conductive layer to form a plurality of cavities penetrating the conductive layer and exposing the first protective layer; the cavities divide the conductive layer into a plurality of conductive structures;

[0066] Step 1004: forming a sacrificial layer in the cavity;

[0067] Step 1005: forming a second protective layer on the sacrificial layer and the conductive structure;

[0068] Step 1006: removing a portion of the second protective layer on the sacrificial layer to form an opening exposing the sacrificial layer;

[0069] Step 1007: removing the sacrificial layer from the opening.

[0070] Figures 6 to 20 The schematic diagram of the semiconductor structure forming process provided by the embodiment of the present disclosure is shown below. Figure 5 、 Figures 6 to 20 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0071] Reference Figure 6 , execute step 1001 to provide a first dielectric layer 101.

[0072] In some specific examples, the material of the first dielectric layer 101 includes but is not limited to silicon oxide.

[0073] In some embodiments, as Figure 6 as well as Figure 7 As shown, the method further includes:

[0074] Before providing the first dielectric layer 101, providing a third dielectric layer 112;

[0075] forming a plurality of first contact structures 114 penetrating the third dielectric layer 112;

[0076] A fourth dielectric layer 113 is formed on the third dielectric layer 112; the first dielectric layer 101 is located on the fourth dielectric layer 113;

[0077] A plurality of second contact structures 115 are formed penetrating the fourth dielectric layer 113 , the first dielectric layer 101 , and the first protective layer 102 ; the first contact structures 114 are in contact with the second contact structures 115 .

[0078] In some embodiments, the second contact structure 115 contacts a conductive structure formed in a subsequent process.

[0079] In some specific examples, the material of the third dielectric layer 112 includes, but is not limited to, silicon oxide. The material of the fourth dielectric layer 113 includes, but is not limited to, silicon nitride, silicon carbonitride, and silicon boronitride.

[0080] In some specific examples, the method of forming the fourth dielectric layer 113, the third dielectric layer 112, and the first dielectric layer 101 includes, but is not limited to, a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0081] In some specific examples, the first contact structure 114 may be formed by forming a through hole through the third dielectric layer 112 using a dry etching process, and then filling the through hole with a conductive material to form the first contact structure 114. Dry etching processes include, but are not limited to, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE). The method for forming the second contact structure 115 is similar to the method for forming the first contact structure 114 and will not be further described.

[0082] In some specific examples, the material of the first contact structure 114 includes but is not limited to copper, and the material of the second contact structure 115 includes but is not limited to tungsten.

[0083] Reference Figure 8 , executing step 1002 , forming a first protective layer 102 and a conductive layer 103 on the first dielectric layer 101 .

[0084] It is understandable that in the embodiment of the present disclosure, the first protection layer 102 is formed on the first dielectric layer 101 so that the first dielectric layer 101 can be protected when the sacrificial layer is removed in the subsequent process, thereby avoiding consumption of the first dielectric layer 101.

[0085] Here, when selecting the material of the first protective layer 102, it is necessary to consider that when the sacrificial layer is removed by a wet etching solution in the subsequent process, the consumption of the first protective layer 102 needs to be small. Therefore, the etching selectivity ratio of the sacrificial layer to the first protective layer 102 needs to be high.

[0086] In some embodiments, the material of the first protective layer 102 includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0087] In some specific examples, the material of the conductive layer 103 may include a metal material. For example, the material of the conductive layer 103 may include, but is not limited to, aluminum. In other specific examples, the material of the conductive layer 103 may also include a semiconductor material. For example, the material of the conductive layer 103 may include, but is not limited to, silicon, silicon germanium, germanium, gallium arsenide, and silicon carbide.

[0088] In some specific examples, the material of the fourth dielectric layer 113 and the material of the first protective layer 102 may be the same or different.

[0089] In some specific examples, methods for forming the first protective layer 102 and the conductive layer 103 include but are not limited to deposition processes.

[0090] In some embodiments, as Figure 8 As shown, the method further includes: providing a first material layer 117 , wherein the first material layer 117 is located between the first protective layer 102 and the conductive layer 103 ; and providing a second material layer 118 , wherein the second material layer 118 is located on the conductive layer 103 .

[0091] The first material layer 117 can be a single-layer film layer or a multi-layer film layer. For example, the first material layer 117 is a single-layer film layer, and the material of the first material layer 117 includes titanium, which can be used to enhance the adhesion between the conductive layer 103 and the first protective layer 102. The first material layer 117 is a multi-layer film layer, and the first material layer 117 includes a titanium layer and a titanium nitride layer. The titanium layer is used to enhance the adhesion between the first protective layer 102 and the conductive layer 103, and the titanium nitride layer can serve as a diffusion barrier layer between the titanium layer and the conductive layer 103. The material of the second material layer 118 can be titanium nitride, which can serve as an anti-reflective layer in subsequent photolithography processes.

[0092] Reference Figure 9 , perform step 1003 to remove part of the conductive layer 103 to form a plurality of conductive structures 105 and cavities 104 located between adjacent conductive structures 105 .

[0093] In some specific examples, such as Figure 10 As shown, the plurality of conductive structures 105 are arranged along a first direction, and each of the conductive structures 105 extends along a second direction; the first direction is perpendicular to the second direction.

[0094] The first direction here may be the X direction in the drawings of the present disclosure, and the second direction may be the Y direction in the drawings of the present disclosure.

[0095] In some embodiments, as Figure 11 As shown, the method further includes:

[0096] Before forming the sacrificial layer in the cavity 104 , a third protection layer 109 is formed on the sidewalls of the cavity 104 and the surface of the conductive structure 105 .

[0097] Here, the thickness of the formed third protection layer 109 can be controlled to ultimately form a relatively large cavity 104. The size of the third protection layer 109 on the sidewall of the conductive structure 105 along the first direction can range from 5 nm to 10 nm.

[0098] In some specific examples, such as Figure 11 As shown, the third protection layer 109 covers the sidewalls of the conductive structure 105 , the sidewalls of the first material layer 117 , and the sidewalls of the second material layer 118 .

[0099] It can be understood that, on the one hand, the third protective layer 109 here can be used to protect the conductive structure 105, the second material layer 118, and the first material layer 117, so as to avoid the influence of the wet etching solution on the conductive structure 105, the first material layer 117 and the second material layer 118 when removing the sacrificial layer in the subsequent process; on the other hand, the third protective layer 109 can also inhibit the migration of atoms in the conductive structure 105, such as aluminum atoms, thereby improving the performance of the semiconductor structure.

[0100] The material selection of the third protective layer 109 needs to consider how to minimize the impact on the third protective layer 109 when removing the sacrificial layer in the cavity in the subsequent process. The etching selectivity ratio between the sacrificial layer and the third protective layer needs to be high.

[0101] In some specific examples, the material of the third protective layer 109 includes, but is not limited to, at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0102] In some specific examples, a method of forming the third protection layer 109 includes, but is not limited to, ALD.

[0103] Reference Figures 12 to 13 , executing step 1004 , forming a sacrificial layer 106 in the cavity 104 .

[0104] In some embodiments, forming the sacrificial layer 106 in the cavity 104 includes: forming the sacrificial layer 106 in the cavity 104 with a third protection layer 109 formed on a sidewall thereof.

[0105] In some embodiments, the material of the sacrificial layer 106 includes but is not limited to at least one of the following: silicon oxide, spin-on hard mask (SOH) material (eg, silicon hard mask material, carbon hard mask material, organic hard mask material, etc.).

[0106] In some specific examples, a specific method of forming the sacrificial layer 106 in the cavity 104 includes: Figure 12 As shown, a sacrificial material layer 116 is formed on the cavity 104 and the conductive structure 105; Figure 13 As shown, a portion of the sacrificial material layer 116 is removed, and the top surface of the remaining sacrificial material layer 116 is flush with the top surface of the third protective layer 109. Methods for removing a portion of the sacrificial material layer 116 include, but are not limited to, dry etching and chemical mechanical polishing (CMP). For example, if the sacrificial layer 106 is made of silicon oxide, dry etching may be used to remove the portion of the sacrificial material layer 116; if the sacrificial layer 106 is made of a spin-on hard mask, chemical mechanical polishing may be used to remove the portion of the sacrificial material layer 116.

[0107] In some specific examples, the method of forming the sacrificial material layer 116 includes, but is not limited to, a deposition process and a spin coating process, wherein the spin coating process includes, but is not limited to, a spin-on dielectric (SOD) process.

[0108] Reference Figure 14 , step 1005 is performed to form a second protective layer 107 , where the second protective layer 107 covers the sacrificial layer 106 and the conductive structure 105 .

[0109] In some embodiments, as Figure 14 As shown, forming the second protection layer 107 on the sacrificial layer 106 and the conductive structure 105 includes: forming the second protection layer 107 on the sacrificial layer 106 and the third protection layer 109. Figure 14 As shown, the second protection layer 107 covers the third protection layer 109 and the sacrificial layer 106 .

[0110] In some embodiments, the material of the second protective layer 107 includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride. The material of the first protective layer 102 and the material of the second protective layer 107 can be the same or different.

[0111] Here, when selecting the material of the second protective layer 107, it is necessary to consider that when the sacrificial layer 106 is removed by a wet etching solution in the subsequent process, the consumption of the second protective layer 107 needs to be less. Therefore, the etching selectivity ratio of the sacrificial layer 106 to the second protective layer 107 needs to be higher.

[0112] Reference Figure 15 as well as Figure 16 , performing step 1006 to remove a portion of the second protection layer 107 on the sacrificial layer 106 to form an opening 108 exposing the sacrificial layer 106 .

[0113] In some specific examples, a method of removing a portion of the second protection layer 107 on the sacrificial layer 106 includes, but is not limited to, dry etching.

[0114] Here, removing a portion of the second protection layer 107 on the sacrificial layer 106 can be understood as: a portion of the second protection layer 107 on the sacrificial layer 106 in each cavity 104 is removed.

[0115] It should be noted that Figure 16 The shape, number, and arrangement of the openings 108 are merely examples, and this disclosure does not limit the specific shape, number, or arrangement of the openings 108. Exemplary shapes of the openings 108 include, but are not limited to, circular, rectangular, elliptical, and polygonal. Multiple openings 108 may be formed between two adjacent conductive structures 105. The openings 108 between two adjacent conductive structures 105 may be arranged in a row along the second direction, or in multiple rows along the first and second directions.

[0116] It can be understood that in the embodiment of the present disclosure, a portion of the second protective layer 107 on the sacrificial layer 106 is removed to form an opening 108 exposing the sacrificial layer 106, so that the wet etching solution in the subsequent process can contact the sacrificial layer 106 through the opening 108, thereby removing the sacrificial layer 106.

[0117] In some embodiments, as Figure 16 As shown, a plurality of openings are formed on the sacrificial layer in each of the cavities.

[0118] In some embodiments, the plurality of openings on the sacrificial layer in each of the cavities are arranged along the second direction.

[0119] It can be understood that in the embodiment of the present disclosure, multiple openings are formed on the sacrificial layer in each of the cavities, so that the wet etching solution can better contact the sacrificial layer. On the other hand, the multiple openings are arranged along the second direction, and a certain distance can be maintained between each opening. This can prevent the second dielectric layer from entering the already formed cavity when the second dielectric layer is subsequently formed on the second protective layer.

[0120] In some specific examples, a plurality of openings are formed on the sacrificial layer in each of the cavities. Figure 16 As shown, they are arranged in a row along the second direction, and can also be arranged as follows Figure 17 In some other specific examples, a plurality of openings are formed on the sacrificial layer in each cavity and can be arranged in a plurality of rows in an array along the first direction and the second direction.

[0121] In some embodiments, the dimension between two adjacent conductive structures 105 along the first direction is W1 , and the dimension of the opening 108 along the first direction is W2 ; the ratio of W2 : W1 is in the range of 1:3 to 1:2.

[0122] It can be understood that in the embodiment of the present disclosure, by controlling the size of the opening 108 within a reasonable range, on the one hand, the subsequent wet etching solution can have better contact with the sacrificial layer 106, thereby improving the efficiency of removing the sacrificial layer 106 and shortening the process time; on the other hand, when the second dielectric layer is formed on the second protective layer 107 in the subsequent process, the second dielectric layer will not enter the formed cavity 104, resulting in a larger proportion of the formed cavity 104.

[0123] Reference Figure 18 , executing step 1007 , removing the sacrificial layer 106 from the opening 108 .

[0124] In some embodiments, removing the sacrificial layer from the opening includes:

[0125] The sacrificial layer is removed from the opening using a wet etching solution; the wet etching solution includes but is not limited to hydrofluoric acid.

[0126] In some specific examples, the wet etching solution can be diluted hydrofluoric acid.

[0127] In the embodiment of the present disclosure, the wet etching solution contacts the sacrificial layer in the cavity through the opening 108, and the sacrificial layer in the cavity can be completely removed, so that the proportion of the cavity finally formed is relatively large, and can even reach 100%, thereby significantly improving the resistance and capacitance delay problem between adjacent conductive structures.

[0128] In some embodiments, as Figure 19 As shown, the method further includes: forming a fourth protection layer 110 on the sidewall of the cavity 104 after removing the sacrificial layer 106 from the opening 108 .

[0129] In some specific examples, the material of the fourth protective layer 110 includes, but is not limited to, silicon oxide and silicon nitride. The method of forming the fourth protective layer 110 includes, but is not limited to, ALD.

[0130] In some specific examples, the fourth protection layer 110 has a relatively small size along the first direction, and an exemplary size of the fourth protection layer 110 along the first direction ranges from 5 nm to 10 nm.

[0131] It can be understood that in the embodiment of the present disclosure, on the one hand, by forming a thin fourth protective layer 110 on the side wall of the cavity 104, the migration of atoms in the conductive structure 105, such as aluminum atoms, can be suppressed, thereby improving the performance of the semiconductor structure; on the other hand, because the fourth protective layer is relatively thin, it has less impact on the proportion of the cavity between adjacent conductive structures.

[0132] It should be noted that, in the embodiment of the present disclosure, the scheme of forming the third protective layer 109 and the scheme of forming the fourth protective layer 110 can be parallel. In the preceding process, when the third protective layer 109 is formed, in order to finally form a cavity 104 with a relatively large proportion, the fourth protective layer 110 may no longer be formed; in the preceding process, when the third protective layer 109 is not formed, the fourth protective layer 110 may be formed to suppress the migration of aluminum atoms.

[0133] In some embodiments, as Figure 20 As shown, the method further includes: after removing the sacrificial layer 106 from the opening 108 using a wet etching solution, forming a second dielectric layer 111 on the second protection layer 107 and the opening 108 .

[0134] In some specific examples, the material of the second dielectric layer 111 includes, but is not limited to, silicon nitride. Methods for forming the second dielectric layer 111 include, but are not limited to, a deposition process.

[0135] In the embodiment of the present disclosure, a first protective layer 102 is formed between the first dielectric layer 101 and the conductive layer 103, and a second protective layer 107 is formed on the conductive layer 103. A portion of the second protective layer 107 on the sacrificial layer 106 is removed to form an opening 108. The sacrificial layer 106 is removed from the opening 108, thereby forming a cavity 104 between the conductive structures 105. On the one hand, the first protective layer 102 can protect the first dielectric layer 101, so that the first dielectric layer 101 can be prevented from being affected when the sacrificial layer 106 in the cavity 104 is removed. On the other hand, by only removing a portion of the second protective layer 107 on the sacrificial layer 106 to form the opening 108 exposing the sacrificial layer 106, the wet etching solution can be etched. The sacrificial layer 106 contacts the second protective layer 107, and the second dielectric layer 111 formed on the second protective layer 107 in the subsequent process will not enter the formed cavity 104; thirdly, since the sacrificial layer 106 can be completely removed, the proportion of the cavity 104 finally formed between the conductive structures 105 is relatively large, and can even reach 100%. In addition, the proportion of the cavity 104 formed in the embodiment of the present disclosure is not limited by the size between adjacent conductive structures 105. Even when the size between adjacent conductive structures 105 is large, a cavity 104 with a relatively large proportion can be formed, which can significantly improve the resistance and capacitance delay problem between adjacent conductive structures 105, thereby improving the performance of the semiconductor structure.

[0136] Based on the same inventive concept as the above-mentioned method for forming a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure. Figures 21 to 23 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure, referring to Figures 21 to 23 , the semiconductor structure includes:

[0137] a first dielectric layer 101;

[0138] A first protective layer 102, located on the first dielectric layer 101;

[0139] A plurality of conductive structures 105 are located on the first protective layer 102;

[0140] a plurality of cavities 104 , each of the cavities 104 being located between adjacent conductive structures 105 ;

[0141] A second protective layer 107 is located on the conductive structure 105 and the cavity 104;

[0142] The opening 108 is located in the second protective layer 107 and communicates with the cavity 104 .

[0143] In the embodiment of the present disclosure, the cavity 104 between adjacent conductive structures 105 accounts for a large proportion, and can even reach the following Figure 21As shown in FIG1 , the resistance and capacitance delay problem between adjacent conductive structures 105 can be significantly improved. In the embodiment of the present disclosure, the proportion of the cavity 104 is not limited by the size between adjacent conductive structures 105. Even when the size between adjacent conductive structures 105 is large, the proportion of the cavity 104 can reach 100%.

[0144] In some specific examples, the material of the conductive structure 105 may include a metal material. For example, the material of the conductive structure 105 may include, but is not limited to, aluminum. In other specific examples, the material of the conductive structure 105 may also include a semiconductor material. For example, the material of the conductive structure 105 may include, but is not limited to, silicon, silicon germanium, germanium, gallium arsenide, and silicon carbide.

[0145] In some embodiments, the conductive structure 105 is made of aluminum.

[0146] In some embodiments, the materials of the first protective layer 102 and the second protective layer 107 include at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0147] In some embodiments, as Figure 22 As shown, the semiconductor structure further includes: a third protection layer 109 located on the sidewall of the cavity 104 and between the second protection layer 107 and the conductive structure 105 .

[0148] In some embodiments, the material of the third protective layer 109 includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

[0149] In some specific examples, the size of the third protection layer 109 on the sidewall of the conductive structure 105 along the first direction may range from 5 nm to 10 nm.

[0150] In some embodiments, as Figure 23 As shown, the semiconductor structure further includes a fourth protection layer 110 located on the sidewall of the cavity 104 .

[0151] In some embodiments, the material of the fourth protective layer 110 includes at least one of the following: silicon oxide and silicon nitride.

[0152] In some specific examples, the fourth protection layer 110 has a relatively small size along the first direction, and an exemplary size of the fourth protection layer 110 along the first direction ranges from 5 nm to 10 nm.

[0153] It can be understood that in the embodiment of the present disclosure, on the one hand, by forming a thin fourth protective layer 110 on the side wall of the cavity 104, the migration of atoms in the conductive structure 105, such as aluminum atoms, can be suppressed, thereby improving the performance of the semiconductor structure; on the other hand, because the fourth protective layer is relatively thin, it has less impact on the proportion of the cavity between adjacent conductive structures.

[0154] In some embodiments, the multiple conductive structures 105 are arranged along a first direction, and each of the conductive structures 105 extends along a second direction; the first direction is perpendicular to the second direction; and multiple openings 108 are formed on the sacrificial layer between each two adjacent conductive structures 105.

[0155] In some embodiments, the plurality of openings 108 on the sacrificial layer between every two adjacent conductive structures 105 are arranged along the second direction.

[0156] In some embodiments, the dimension between two adjacent conductive structures 105 along the first direction is W1 , and the dimension of the opening 108 along the first direction is W2 ; the ratio of W2 : W1 is in the range of 1:3 to 1:2.

[0157] In some embodiments, the semiconductor structure further includes a second dielectric layer 111 located on the second protection layer 107 and the opening 108 .

[0158] In some specific examples, the material of the second dielectric layer 111 includes but is not limited to silicon nitride.

[0159] like Figures 21 to 23 As shown, the semiconductor structure further includes: a first material layer 117 , the first material layer 117 is located between the first protection layer 102 and the conductive structure 105 ; and a second material layer 118 , the second material layer 118 is located between the conductive structure 105 and the second protection layer 107 .

[0160] In some embodiments, the semiconductor structure further comprises:

[0161] a third dielectric layer 112;

[0162] a plurality of first contact structures 114 located in the third dielectric layer 112 and penetrating the third dielectric layer 112;

[0163] a fourth dielectric layer 113 on the third dielectric layer 112;

[0164] A plurality of second contact structures 115 penetrate the fourth dielectric layer 113 , the first dielectric layer 101 , and the first protective layer 102 ; the first contact structures 114 contact the second contact structures 115 , and the second contact structures 115 contact the conductive structures 105 .

[0165] In some specific examples, the material of the third dielectric layer 112 includes but is not limited to silicon oxide; the material of the fourth dielectric layer 113 includes but is not limited to silicon nitride, silicon carbonitride, and silicon boronitride; the material of the first contact structure 114 includes but is not limited to copper; and the material of the second contact structure 115 includes but is not limited to tungsten.

[0166] In some specific examples, the first contact structure 114 , the second contact structure 115 , and the conductive structure 105 may be used to form an interconnection structure in a chip.

[0167] The chip can be a logic chip, a memory chip, or a power management integrated circuit (PMIC). Types of logic chips include, but are not limited to, central processing unit (CPU) chips, graphics processing unit (GPU) chips, image signal processor (ISP) chips, application processor (AP) chips, embedded neural network processing unit (NPU) chips, and video processing unit (VPU) chips. Types of memory chips include, but are not limited to, dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, phase change random access memory (PRAM) chips, magnetoresistive random access memory (MRAM) chips, ferroelectric random access memory (FeRAM) chips, resistive random access memory (RRAM) chips, and flash memory chips.

[0168] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0169] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0170] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a first dielectric layer; forming a first protective layer and a conductive layer on the first protective layer on the first dielectric layer; removing a portion of the conductive layer to form a plurality of cavities penetrating the conductive layer and exposing the first protective layer; the cavities divide the conductive layer into a plurality of conductive structures; forming a sacrificial layer in the cavity; forming a second protective layer on the sacrificial layer and the conductive structure; removing a portion of the second protective layer on the sacrificial layer to form an opening exposing the sacrificial layer; removing the sacrificial layer from the opening; The plurality of conductive structures are arranged along a first direction, and each of the conductive structures extends along a second direction; the first direction is perpendicular to the second direction; a plurality of openings are formed on the sacrificial layer in each of the cavities; The plurality of openings on the sacrificial layer in each of the cavities are arranged along the second direction; The dimension between two adjacent conductive structures along the first direction is W1, and the dimension of the opening along the first direction is W2; the ratio of W2:W1 is in the range of 1:3 to 1:

2.

2. The forming method according to claim 1, wherein: The materials of the first protective layer and the second protective layer include at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride; The material of the sacrificial layer includes at least one of the following: silicon oxide and spin-on hard mask material.

3. The forming method according to claim 1, wherein: The removing the sacrificial layer from the opening comprises: The sacrificial layer is removed from the opening using a wet etching solution.

4. The forming method according to claim 1, wherein: The method further comprises: Before forming the sacrificial layer in the cavity, forming a third protective layer on the sidewall of the cavity and the surface of the conductive structure; The forming of a sacrificial layer in the cavity comprises: forming a sacrificial layer in the cavity having the third protective layer formed on the sidewall thereof; The forming of a second protective layer on the sacrificial layer and the conductive structure includes: A second protection layer is formed on the sacrificial layer and the third protection layer.

5. The forming method according to claim 1, wherein: The method further comprises: After removing the sacrificial layer from the opening, a fourth protection layer is formed on the sidewall of the cavity.

6. The forming method according to claim 1, wherein: The method further comprises: After removing the sacrificial layer from the opening, a second dielectric layer is formed on the second protection layer and the opening.

7. The forming method according to claim 1, wherein: The method further comprises: Before providing the first dielectric layer, providing a third dielectric layer; forming a plurality of first contact structures penetrating the third dielectric layer; forming a fourth dielectric layer on the third dielectric layer; wherein the first dielectric layer is located on the fourth dielectric layer; A plurality of second contact structures are formed penetrating the fourth dielectric layer, the first dielectric layer and the first protective layer; the first contact structures are in contact with the second contact structures, and the second contact structures are in contact with the conductive structures.

8. A semiconductor structure, characterized in that include: a first dielectric layer; a first protective layer, located on the first dielectric layer; a plurality of conductive structures, located on the first protective layer; a plurality of cavities, each of the cavities being located between adjacent conductive structures; a second protective layer, located on the conductive structure and the cavity; an opening, located in the second protective layer and communicating with the cavity; The plurality of conductive structures are arranged along a first direction, and each of the conductive structures extends along a second direction; the first direction is perpendicular to the second direction; a plurality of openings are formed on the sacrificial layer in each of the cavities; The plurality of openings on the sacrificial layer in each of the cavities are arranged along the second direction; The dimension between two adjacent conductive structures along the first direction is W1, and the dimension of the opening along the first direction is W2; the ratio of W2:W1 is in the range of 1:3 to 1:

2.

9. The semiconductor structure according to claim 8, wherein: The semiconductor structure further includes a third protection layer located on the sidewall of the cavity and between the second protection layer and the conductive structure.

10. The semiconductor structure according to claim 9, wherein: The materials of the first protective layer and the second protective layer include at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride; The material of the third protective layer includes at least one of the following: silicon nitride, silicon carbonitride, and silicon boronitride.

11. The semiconductor structure according to claim 8, wherein: The semiconductor structure further includes a fourth protection layer located on a sidewall of the cavity.

12. The semiconductor structure according to claim 8, wherein: The plurality of conductive structures are arranged along a first direction, and each of the conductive structures extends along a second direction; the first direction is perpendicular to the second direction; and a plurality of openings are formed on the sacrificial layer between each two adjacent conductive structures.

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