System-level stacking structure and electronic equipment

Abstract

The invention discloses a system-level stacking structure and electronic equipment. The system-level stack structure includes a substrate, a conductive connection element, an integrated circuit, and a conductive component. The substrate comprises a supporting surface, and the conductive connecting element and the integrated circuit are arranged on the supporting surface in parallel. The conductive part is located on the surfaces of the conductive connecting element and the integrated circuit, the conductive part is connected with the conductive connecting element and electrically connected with the integrated circuit, and the conductive part and the integrated circuit are spaced by a first distance in the direction perpendicular to the supporting face. The integrated circuit and the conductive component form a gap for heat dissipation through the spacing distance, so that the safety and reliability of the system-level stacking structure and the electronic equipment are effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a system-level stacking structure and electronic equipment. Background Art

[0002] System in a Package (SIP) integrates multiple functional chips, including processors, memory and other functional chips, into one package to achieve basically complete functions. From the perspective of the structure of the SIP package, it is mainly the arrangement, compatibility and layout of multiple functional chips and discrete components. From the perspective of the current product packaging structure, chips and discrete components mainly appear in a flat structure, which obviously increases the overall size of the packaging structure, or uses the substrate embedding process of passive components, which increases the substrate processing cycle and cost, and the substrate yield is relatively poor.

[0003] With the gradual development of Internet technology and the growing demand for networks, in order to meet the requirements of high-speed processing performance, multi-dimensional (3D) stacked semiconductor chips are usually used to adapt to high-power chips. Multi-dimensional stacked semiconductor chips usually stack multiple chips in the vertical direction, thereby increasing the chip interconnection density, reducing the package volume, and improving the efficiency of electrical and thermal transmission. Since the multiple chips of the stacked semiconductor chips are stacked in the vertical direction, the heat of the semiconductor chip is not easy to dissipate during operation. Especially for the power SIP module with a large current when working, the heat accumulates inside the semiconductor chip, making it difficult for the heat of the chip to dissipate, resulting in a high junction temperature of the stacked chip, and the low-impedance connection between the chip and the discrete component in the high temperature environment of the stacked structure, which is easy to affect the service life of the semiconductor chip and even cause the semiconductor chip to fail. According to statistical data, at least 55% of the reasons for the failure of electronic equipment are temperature rise failures. For every 1°C increase in the temperature of the semiconductor chip, the reliability of the electronic device decreases by 5%. Therefore, the heat dissipation effect of the stacked chip is improved to meet the heat dissipation requirements of high-power devices. Summary of the invention

[0004] In order to solve the aforementioned technical problems, the present invention provides a system-level stacking structure with high security and reliability.

[0005] Furthermore, the present invention also provides an electronic device including the above-mentioned system-level stacking structure.

[0006] In a first aspect, an embodiment of the present invention provides a system-level stacking structure, comprising: a substrate, comprising a supporting surface; a conductive connection element and at least one integrated circuit, wherein the conductive connection element and the integrated circuit are arranged in parallel on the supporting surface; a conductive component, located between the conductive connection element and the surface of the integrated circuit, the conductive component connects the conductive connection element and is electrically connected to the integrated circuit, and the conductive component and the integrated circuit are separated by a first distance in a direction perpendicular to the supporting surface.

[0007] In one embodiment, a heat-conducting layer is provided between the conductive component and the integrated circuit, and the heat-conducting layer is used to conduct heat generated by the integrated circuit and / or the conductive component.

[0008] In one embodiment, the conductive component is an inductor, and a conductive pin of the inductor is connected to the conductive component.

[0009] In one embodiment, the inductor is a single-winding inductor or a double-winding inductor.

[0010] In one embodiment, the system-level stacking structure includes a plurality of the conductive connection elements disposed at different positions.

[0011] In one embodiment, a plurality of separated conductive connection elements are arranged at predetermined intervals around the peripheral edge of the substrate.

[0012] In one embodiment, the conductive connection element is made of copper.

[0013] In one embodiment, the system-level stacking structure further includes a plurality of discrete components, which are arranged in parallel with the integrated circuit on the support surface and are electrically connected to the integrated circuit and / or the conductive component through conductive lines.

[0014] In one embodiment, the system-level stacking structure is a system-level packaged power module.

[0015] In a second aspect, an embodiment of the present invention further provides an electronic device, comprising a functional module and the aforementioned system-level stacking structure, wherein the functional module is connected to the system-level stacking structure to execute a preset function.

[0016] Compared with the prior art, since the conductive component and the integrated circuit are not simultaneously arranged in the supporting surface of the substrate, but are stacked in the thickness direction, and a gap is formed between the conductive component and the integrated circuit by the first distance, the heat generated by the conductive component can be quickly dissipated without affecting the working performance of the integrated circuit. At the same time, the heat generated by the integrated circuit during operation is conducted and dissipated through the gap formed by the first distance, so that the heat generated by the integrated circuit can also be quickly dissipated, ensuring the safety and reliability of the operation of the overall components of the system-level stacking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A schematic diagram of a three-dimensional structure of a system-level stacking structure in an embodiment of the present invention;

[0019] Figure 2 for Figure 1 A perspective structural diagram of the system-level stacking structure is shown;

[0020] Figure 3 In the first embodiment of the present invention, Figure 2 The schematic diagram of the cross-sectional structure of the system-level stacking structure along line III-III is shown;

[0021] Figure 4 In the first embodiment of the present invention, Figure 2 The system-level stacking structure shown is a schematic cross-sectional structure diagram along line IV-IV;

[0022] Figure 5 In the first embodiment of the present invention, Figure 2 A partial top view of the system-level stacked structure shown;

[0023] Figure 6 In the second embodiment of the present invention, Figure 2 A schematic cross-sectional structure diagram of the system-level stacking structure along line III-III is shown;

[0024] Figure 7 In the third embodiment of the present invention, Figure 2 The schematic diagram of the cross-sectional structure of the system-level stacking structure along line III-III is shown;

[0025] Figure 8 In the third embodiment of the present invention, Figure 2The schematic diagram of the cross-sectional structure of the system-level stacking structure along line IV-IV is shown;

[0026] Fig. 9 In the third embodiment of the present invention, Figure 2 A partial top view of the system-level stacked structure shown;

[0027] Fig.10 FIG. 4 is a functional block diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood. The following description of each embodiment is with reference to the attached diagrams to illustrate the specific embodiments that the present invention can be used to implement.

[0029] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. It should be noted that the terms "first", "second" and the like in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "include", "may include", "include", or "may include" used in the present invention indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components or combinations thereof, and are intended to cover non-exclusive inclusions. It should also be understood that "at least one" described herein means one or more, such as one, two or three, etc., and "plurality" means at least two, such as two or three, etc., unless otherwise clearly defined.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0031] See also Figure 1 and Figure 2 ,in, Figure 1 is a schematic diagram of the three-dimensional structure of the system-level stacking structure 1 in an embodiment of the present invention, Figure 2 for Figure 1 The perspective structural diagram of the system-level stacking structure 1 is shown. In this embodiment, the system-level stacking structure 1 may be a microcircuit structure stacked by a system-level package (SIP), and the system-level stacking structure 1 may be a power module, a high-speed storage module, a processor module, and a semiconductor device module, etc. In this embodiment, the system-level stacking structure 1 is described as a system-level stacked power module as an example.

[0032] Specifically, Figure 1 and Figure 2 As shown, the system-level stacked structure 1 includes a substrate 10, an integrated circuit layer 20 and a conductive element layer 30 which are stacked in sequence.

[0033] The substrate 10 includes supporting surfaces 10a ( Figure 3 ) and the connecting surface 10b( Figure 3 ), the integrated circuit layer 20 is disposed on the support surface 10a of the substrate 10, the conductive element layer 30 is disposed on the surface of the integrated circuit layer 20, and is electrically connected to a part of the circuit of the integrated circuit layer 20 through a part of the conductive connecting elements of the integrated circuit layer 20. The integrated circuit layer 20 and the conductive element layer 30 cooperate with each other to perform the preset function.

[0034] It can be understood that the integrated circuit layer 20 includes multiple integrated circuits, multiple discrete electronic components and at least one conductive connection element, and the conductive element layer 30 includes at least one conductive component, and the conductive component is electrically connected to the integrated circuit through the conductive connection element. In this embodiment, the conductive element layer 30 is located on the upper side of the integrated circuit layer 20, and there is a certain distance between the two. Therefore, the heat generated by the conductive element layer 30 and the integrated circuit layer 20 during operation has little influence on each other, which is more conducive to the heat dissipation of the two, thereby ensuring the safety and reliability of the system-level stacking structure.

[0035] It can be understood that the system-level stacking structure 1 can directly cooperate with other modules to perform preset functions, or it can be encapsulated using packaging materials such as epoxy resin, that is, the epoxy resin is covered with the system-level stacking structure 1 using a plastic encapsulation process, thereby protecting the substrate 10 and the devices in the integrated circuit layer 20 and the conductive element layer 30.

[0036] More specifically, see Figure 3 , Figure 4 and Figure 5 ,in, Figure 3 For Figure 2 The schematic diagram of the cross-sectional structure of the system-level stacking structure along line III-III is shown. Figure 4 For Figure 2 The schematic diagram of the cross-sectional structure of the system-level stacking structure along the IV-IV line is shown. Figure 5 For Figure 1 A partial structural top view of the system-level stacking structure shown in FIG. 1 , wherein in this embodiment, Figure 5 For Figure 1 The illustrated system-level stacked structure is a top view of the corresponding integrated circuit layer 20 .

[0037] like Figures 3 to 5 As shown, in the support surface 10a and the connection surface 10b on the opposite sides of the substrate 10, the support surface 10a is used to support and set the integrated circuit layer 20. In this embodiment, the inside of the substrate 10, the support surface 10a and the connection surface 10b are all provided with corresponding conductive circuits (printed traces) to facilitate the electrical connection of the electronic components set on the support surface 10a of the substrate 10. The connection surface 10b is provided with a plurality of conductive pins P, and the conductive pins P are electrically connected to the electronic components in the integrated circuit layer 20 and the conductive element layer 30 through the conductive circuits inside the substrate 10, and the system-level stacked structure 1 is connected to other electronic modules through the plurality of conductive pins P. In this embodiment, the substrate 10 can be a printed circuit board (PCB), or a packaging substrate made of resin or other materials.

[0038] The integrated circuit layer 20 includes a plurality of integrated circuits and auxiliary discrete electronic components. Specifically, the integrated circuit layer 20 includes a plurality of integrated circuits 201 and a plurality of discrete components 202. The integrated circuit 201 may be an integrated chip. In this embodiment, the integrated circuit 201 is connected to the conductive circuit in the substrate 10 through conductive hardware (not shown). For example, when the system-level stacking structure 1 is a power management chip in a power module, the integrated circuit 201 may be a chip including an operational amplifier circuit, a chip including a voltage conversion circuit such as a boost circuit (Boost) or a buck circuit (Buck), a microprocessor management chip, or one or more thereof. Of course, the system-level stacking structure 1 may also be other integrated packaged chips, and is not limited to this example.

[0039] The plurality of discrete components 202 may include resistors, capacitors, inductors, transformer windings or other electronic components. The plurality of discrete components 202 are connected and bonded to each other through conductive traces in the substrate 10, and are electrically connected to the integrated circuit 201 to form a corresponding functional circuit.

[0040] In this embodiment, the integrated circuit 201 has a first height H1 in a direction perpendicular to the support surface 10a, that is, the thickness of the integrated circuit 201 is the first height H1, wherein the dimension of the discrete component 202 in the direction perpendicular to the support surface 10a is smaller than the first height H1.

[0041] The integrated circuit layer 20 further includes a plurality of conductive connection elements 203, which are arranged along the peripheral side of the edge of the substrate 10, and the conductive connection elements 203 have a second height H2 in a direction perpendicular to the support surface 10a. The second height H2 is greater than the first height H1. In this embodiment, the number and position of the conductive connection elements 203 can be adjusted according to actual needs, and the material of the conductive connection elements 203 can be a conductive metal material such as copper, aluminum, or other alloy conductive materials, and the surface of the conductive connection elements 203 can also be formed into a conductive structure by surface processes such as nickel plating, tin plating, and gold plating.

[0042] In this embodiment, the conductive connection element 203 is a rectangular parallelepiped structure as a whole, and is disposed on the support surface 10a of the substrate 10 by welding. Alternatively, in other embodiments of the present invention, the conductive connection element 203 can also be a columnar, strip, sheet, etc. as a whole, or can be CNC or cast into a structure of other shapes and appearances.

[0043] The conductive element layer 30 at least includes a conductive component 31, wherein the conductive component 31 is located on a portion of the surface of the plurality of integrated circuits 201 and the plurality of discrete components 202 in the integrated circuit layer 20, and the conductive component 31 contacts and connects the conductive connection element 203. Correspondingly, since the height of the conductive connection element 203 is greater than the height of the integrated circuit 201, the conductive component 31 connected to the conductive connection element 203 is spaced apart from the integrated circuit 201 by a first distance D1 in a direction perpendicular to the substrate 10. In other words, there is a gap of the first distance D1 between the conductive component 31 and the integrated circuit 201 in a direction perpendicular to the substrate 10.

[0044] In this embodiment, the conductive component 31 is an inductor, wherein the conductive pins (not shown) of the inductor are connected to the conductive connection elements 203. The number of the pins of the inductor directly corresponds to the number of the conductive connection elements 203. In this embodiment, when the inductor is a single-winding inductor, the inductor includes two conductive pins at different positions, and the number of the conductive connection elements 203 is also two, which are arranged at positions corresponding to the pin positions of the inductor.

[0045] In the present embodiment, since the conductive component 31 and the integrated circuit 201 are not simultaneously arranged in the supporting surface 10a of the substrate 10, but are stacked in the thickness direction, and an air gap is formed between the conductive component 31 and the integrated circuit 201 by spacing them by the first distance D1, the heat generated by the conductive component 31 is quickly dissipated without affecting the working performance of the integrated circuit 201. At the same time, the heat generated by the integrated circuit 201 during operation is conducted and dissipated through the gap formed by the first distance D1, so that the heat generated by the integrated circuit 201 can also be quickly dissipated, thereby ensuring the safety and reliability of the operation of the overall components of the system-level stacking structure 1.

[0046] Furthermore, the conductive component 31 only needs to be connected and supported by the conductive connection element 203 on the surface of the substrate 10, which effectively reduces the area and weight of the substrate 10 occupied by the conductive component 31, and can effectively improve the power density of the SIP packaging structure, so that the conductive component 31 has a small thermal resistance when transmitting a large current under the heat dissipation structure, thereby effectively improving the yield of the system-level stacking structure 1. In addition, the configuration of the conductive component 31 enables the system-level stacking structure to use standard devices during the development process, effectively simplifying the design structure, thereby shortening the development and design time of the system-level stacking structure.

[0047] See also Figure 6 , which is the second embodiment of the present invention. Figure 2 The schematic diagram of the cross-sectional structure of the system-level stacking structure along line III-III is shown, wherein: Figure 6 The system-level stacking structure 2 shown in FIG. Figure 3-Figure 5 The structure of the system-level stacked structure 1 shown is basically the same, the only difference is that a heat-conducting layer 40 is further provided in the gap between the conductive component 31 and the integrated circuit 201 .

[0048] Specifically, Figure 6 As shown, in the support surface 10a and the connection surface 10b on the opposite sides of the substrate 10, the support surface 10a is used to support and set the integrated circuit layer 20. In this embodiment, the inside of the substrate 10, the support surface 10a and the connection surface 10b are all provided with corresponding conductive circuits (printed wiring) to facilitate the electrical connection of the electronic components set on the support surface 10a of the substrate 10. The connection surface 10b is provided with a plurality of conductive pins P, and the conductive pins P are electrically connected to the electronic components in the integrated circuit layer 20 and the conductive element layer 30 through the conductive circuit inside the substrate 10, and the system-level stacking structure 2 is connected to other electronic modules through the plurality of conductive pins P. In this embodiment, the substrate 10 can be a PCB circuit board, or it can be a substrate of resin or other materials.

[0049] The integrated circuit layer 20 includes a plurality of integrated circuits and auxiliary discrete electronic components. Specifically, the integrated circuit layer 20 includes a plurality of integrated circuits 201 and a plurality of discrete components 202. The integrated circuit 201 may be an integrated chip. For example, when the system-level stacking structure 2 is a power management chip in a power module, the integrated circuit 201 may be a chip including an operational amplifier circuit, a chip including a voltage conversion circuit such as a boost circuit (Boost) or a buck circuit (Buck), a microprocessor management chip, etc. Of course, the system-level stacking structure 2 may also be other integrated packaged chips, and is not limited to this example.

[0050] The plurality of discrete components 202 may include resistors, capacitors, inductors, transformer windings or other electronic components. The plurality of discrete components 202 are connected to each other through conductive traces in the substrate 10 and are electrically connected to the integrated circuit 201 to form a corresponding functional circuit.

[0051] In this embodiment, the integrated circuit 201 has a first height H1 in a direction perpendicular to the support surface 10a, that is, the thickness dimension of the integrated circuit 201 is the first height H1, wherein the dimension of the discrete component 202 along the direction perpendicular to the support surface 10a is smaller than the first height H1.

[0052] The integrated circuit layer 20 further includes a plurality of conductive connection elements 203, which are arranged along the peripheral side of the edge of the substrate 10, and the conductive connection elements 203 have a second height H2 in a direction perpendicular to the support surface 10a. The second height H2 is greater than the first height H1. In this embodiment, the number and position of the conductive connection elements 203 can be adjusted according to actual needs, and the material of the conductive connection elements 203 can be a conductive metal material such as copper, aluminum, or other conductive materials.

[0053] The conductive element layer 30 at least includes a conductive component 31, wherein the conductive component 31 is located on the surface of multiple integrated circuits 201 and multiple discrete components 202 in the integrated circuit layer 20, and the conductive component 31 contacts and connects the conductive connection element 203. Correspondingly, since the height of the conductive connection element 203 is greater than the height of the integrated circuit 201, the conductive component 31 connected to the conductive connection element 203 is spaced apart from the integrated circuit 201 by a first distance D1 in a direction perpendicular to the substrate 10. In other words, the conductive component 31 and the integrated circuit 201 have a gap of the first distance D1 in a direction perpendicular to the substrate 10.

[0054] In this embodiment, the conductive component 31 is an inductor, wherein the conductive pins (not shown) of the inductor are connected to the conductive connection elements 203. The number of the pins of the inductor directly corresponds to the number of the conductive connection elements 203. In this embodiment, when the inductor is a single-winding inductor, the inductor includes two conductive pins at different positions, and the number of the conductive connection elements 203 is also two, which are arranged at positions corresponding to the pin positions of the inductor.

[0055] The heat-conducting layer 40 is located between the conductive component 31 and the integrated circuit 201 , or in other words, the gap between the conductive component 31 and the integrated circuit 201 is filled with the heat-conducting layer 40 .

[0056] In this embodiment, the thermal conductivity of the heat-conducting layer 40 is at least greater than the thermal conductivity of the conductive component 31 and the integrated circuit 201 , and the greater the thermal conductivity of the heat-conducting layer 40 , the better the uniform temperature heat dissipation effect.

[0057] In the embodiment of the present invention, the thermal conductivity of the heat-conducting layer 40 ranges from 5W / mK to 20W / mK. For example, the thermal conductivity of the heat-conducting layer 40 may be 6W / mK or 12W / mK, so that the heat-conducting layer 40 maintains the desired uniform temperature and a more uniform heat dissipation effect. Of course, the thermal conductivity of the heat-conducting layer 40 may be adjusted according to actual needs, and is not limited to this example.

[0058] In this embodiment, the material of the heat-conducting layer 40 is selected from heat-conducting gel, which has better heat-conducting and heat-dissipating performance, thereby performing uniform heat dissipation. In other embodiments of the present invention, the heat-conducting layer 40 can also be selected from other heat-conducting materials, and is not limited to this example.

[0059] In the present embodiment, since the conductive component 31 and the integrated circuit 201 are not simultaneously arranged in the supporting surface 10a of the substrate 10, but are stacked in the thickness direction, and a heat-conducting layer 40 is arranged between the conductive component 31 and the integrated circuit 201, the heat generated by the conductive component 31 can be quickly dissipated without affecting the working performance of the integrated circuit 201. At the same time, the heat generated by the integrated circuit 201 during operation is conducted and dissipated through the heat-conducting layer 40, so that the heat generated by the integrated circuit 201 can also be quickly dissipated, thereby ensuring the safety and reliability of the operation of the overall components of the system-level stacking structure 2.

[0060] See also Figure 7 , Figure 8 and Fig. 9 , Figure 7 In the third embodiment of the present invention, Figure 2 The schematic diagram of the cross-sectional structure of the system-level stacking structure along line III-III is shown. Figure 8 In the third embodiment of the present invention, Figure 2The schematic diagram of the cross-sectional structure of the system-level stacking structure along the IV-IV line is shown. Fig. 9 In the third embodiment of the present invention, Figure 2 A partial structural top view of the system-level stacking structure is shown, wherein in this embodiment, Fig. 9 For Figure 2 The illustrated system-level stacked structure is a top view of the corresponding integrated circuit layer 20 .

[0061] Among them, the system-level stacking structure 2 and Figure 3-Figure 5 The structure of the system-level stacked structure 1 shown is basically the same, and the only difference is the structure of the conductive component 31.

[0062] Specifically, Figure 7-Figure 9 As shown, in the support surface 10a and the connection surface 10b on the opposite sides of the substrate 10, the support surface 10a is used to support and set the integrated circuit layer 20. In this embodiment, the inside of the substrate 10, the support surface 10a and the connection surface 10b are all provided with corresponding conductive circuits (printed wiring) to facilitate the electrical connection of the electronic components set on the support surface 10a of the substrate 10. The connection surface 10b is provided with a plurality of conductive pins P, and the conductive pins P are electrically connected to the electronic components in the integrated circuit layer 20 and the conductive element layer 30 through the conductive circuits inside the substrate 10, and the system-level stacking structure 3 is connected to other electronic modules through the plurality of conductive pins P. In this embodiment, the substrate 10 can be a PCB circuit board, or it can be a substrate of resin or other materials.

[0063] The integrated circuit layer 20 includes a plurality of integrated circuits and auxiliary discrete electronic components. Specifically, the integrated circuit layer 20 includes a plurality of integrated circuits 201 and a plurality of discrete components 202. The integrated circuit 201 may be an integrated chip. In this embodiment, the integrated circuit 201 is connected to the conductive circuit in the substrate 10 through conductive hardware (not shown). For example, when the system-level stacking structure 3 is a power management chip, the integrated circuit 201 may be a chip including an operational amplifier circuit, a chip including a voltage conversion circuit such as a boost circuit (Boost) or a buck circuit (Buck), a microprocessor management chip, etc. Of course, the system-level stacking structure 2 may also be other integrated packaged chips, and is not limited to this example.

[0064] The plurality of discrete components 202 may include resistors, capacitors, inductors, transformer windings or other electronic components. The plurality of discrete components 202 are connected to each other through conductive traces in the substrate 10 and are electrically connected to the integrated circuit 201 to form a corresponding functional circuit.

[0065] In this embodiment, the integrated circuit 201 has a first height H1 in a direction perpendicular to the support surface 10a, that is, the thickness of the integrated circuit 201 is the first height H1, wherein the size of the discrete component 202 in the direction perpendicular to the support surface 10a is smaller than the first height H1.

[0066] The integrated circuit layer 20 further includes a plurality of conductive connection elements 203, which are arranged along the peripheral edge of the substrate 10, and the conductive connection elements 203 have a second height H2 in a direction perpendicular to the support surface 10a. The second height H2 is greater than the first height H1. In this embodiment, the number and position of the conductive connection elements 203 can be adjusted according to actual needs, and the material of the conductive connection elements 203 can be a conductive metal material such as copper, aluminum, or other conductive materials.

[0067] The conductive element layer 30 at least includes a conductive component 31, wherein the conductive component 31 is located on the surface of multiple integrated circuits 201 and multiple discrete components 202 in the integrated circuit layer 20, and the conductive component 31 contacts and connects the conductive connection element 203. Correspondingly, since the height of the conductive connection element 203 is greater than the height of the integrated circuit 201, the conductive component 31 connected to the conductive connection element 203 is spaced apart from the integrated circuit 201 by a first distance D1 in a direction perpendicular to the substrate 10. In other words, the conductive component 31 and the integrated circuit 201 have a gap of the first distance D1 in a direction perpendicular to the substrate 10.

[0068] In this embodiment, the conductive component 31 is an inductor, wherein the conductive pin (not marked) of the inductor is connected to the conductive connection element 203, and the inductor is a dual-winding inductor, including two groups of conductive pins at four different positions. Then the number of conductive connection elements 203 is also two groups of four in total, which are arranged at positions corresponding to the pin positions of the inductor.

[0069] In the present embodiment, since the conductive component 31 and the integrated circuit 201 are not simultaneously arranged in the supporting surface 10a of the substrate 10, but are stacked in the thickness direction, and an air gap is formed between the conductive component 31 and the integrated circuit 201 by spacing them by the first distance D1, the heat generated by the conductive component 31 is quickly dissipated without affecting the working performance of the integrated circuit 201. At the same time, the heat generated by the integrated circuit 201 during operation is conducted and dissipated through the gap formed by the first distance D1, so that the heat generated by the integrated circuit 201 can also be quickly dissipated, thereby ensuring the safety and reliability of the operation of the overall components of the system-level stacking structure 3.

[0070] See also Fig.10 , which is a functional block diagram of an electronic device 100 in one embodiment of the present invention. In this embodiment, the electronic device 100 includes functional modules and Figure 1-Figure 9The system-level stacking structure in the electronic device 100 is connected and coordinated with the functional modules to realize the preset functions corresponding to the electronic device 100. For example, when the system-level stacking structure is a power management chip, the functional modules can be a processor (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU) and peripheral circuits, or workloads such as display screens and speakers, etc. The power management chip is used to provide driving power for the functional modules. Of course, in other embodiments of the present invention, the conductor device stacking packaging structure can also be a memory chip, a processor, etc., and is not limited to this example. Due Figure 1-Figure 9 The system-level stacking structures 1 to 3 have good safety and reliability, and thus the electronic device 100 has correspondingly better safety and reliability.

[0071] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0072] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A system-level stacking structure, characterized in that: include: a substrate, including a support surface; A conductive connection element and at least one integrated circuit, wherein the conductive connection element and the integrated circuit are arranged in parallel on the support surface; A conductive component is located between the conductive connection element and the surface of the integrated circuit. The conductive component is connected to the conductive connection element and is electrically connected to the integrated circuit. The conductive component and the integrated circuit are spaced a first distance apart in a direction perpendicular to the supporting surface.

2. The system-level stacking structure according to claim 1, characterized in that: A heat-conducting layer is arranged between the conductive component and the integrated circuit, and the heat-conducting layer is used for conducting heat generated by the integrated circuit and / or the conductive component.

3. The system-level stacking structure according to claim 1, characterized in that: The conductive component is an inductor, and a conductive pin of the inductor is connected to the conductive component.

4. The system-level stacking structure according to claim 3, characterized in that: The inductor is a single-winding inductor or a double-winding inductor.

5. The system-level stacking structure according to claim 4, characterized in that: The system-level stacking structure includes a plurality of the conductive connection elements arranged at different positions.

6. The system-level stacking structure according to claim 5, characterized in that: A plurality of separated conductive connection elements are arranged at predetermined intervals around the peripheral edge of the substrate.

7. The system-level stacking structure according to any one of claims 1 to 6, characterized in that: The conductive connection element is made of copper.

8. The system-level stacking structure according to claim 7, characterized in that: The system-level stacking structure further includes a plurality of discrete components, which are arranged in parallel with the integrated circuit on the support surface and are electrically connected to the integrated circuit and / or the conductive component through conductive lines.

9. The system-level stacking structure according to claim 8, characterized in that: The system-level stacking structure is a system-level packaged power module.

10. An electronic device, characterized in that: It comprises a functional module and a system-level stacking structure according to any one of claims 1 to 9, wherein the functional module is connected to the system-level stacking structure to execute a preset function.

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