Packaging structure, packaging device and electronic equipment

Abstract

The invention discloses a packaging structure, a packaging device and electronic equipment. The packaging structure comprises a packaging substrate; the first stacking piece is located on the packaging substrate and comprises a plurality of first chip sets; the second stacking piece is located on the packaging substrate and comprises a plurality of second chip sets; wherein the first stacking piece and the second stacking piece are connected with the same signal channel, the number of the first chip sets is different from that of the second chip sets, the chips in the first chip sets belong to different columns, and the chips in the second chip sets belong to different columns. The packaging structure is small in size.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a packaging structure, a packaging device, and an electronic device. Background Art

[0002] Recently, the demand for portable devices in the electronic product market has increased rapidly, and therefore, there is a growing demand for miniaturization and lightness of electronic components mounted on electronic products. However, as the storage capacity required for electronic components increases, the size of the electronic components also increases. Summary of the invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a packaging structure, including:

[0004] Package substrate;

[0005] A first stack, located on the packaging substrate, includes a plurality of first chip groups;

[0006] A second stack, located on the packaging substrate, includes a plurality of second chip groups;

[0007] The first stack and the second stack are connected to the same signal channel, the number of the first chipset is different from the number of the second chipset, the chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns.

[0008] In some embodiments, each of the first chipsets is connected to each data signal respectively, multiple first chipsets are connected to the same control signal, each of the second chipsets is connected to each data signal respectively, and multiple second chipsets are connected to the same control signal.

[0009] In some embodiments, the first chipset includes:

[0010] Chip down;

[0011] an upper chip, offset and arranged on the lower chip;

[0012] The lower chip and the upper chip are connected via leads, and the leads are connected to the packaging substrate.

[0013] In some embodiments, in the vertical direction, projection areas of the plurality of first chip groups overlap, and projection areas of the plurality of second chip groups overlap.

[0014] In some embodiments, the structure of the upper chip is the same as that of the lower chip, and the lower chip includes:

[0015] A plurality of edge data pads, located on the side of the lower chip;

[0016] A plurality of intermediate data pads located at the center of the lower chip;

[0017] Wherein, each of the edge data pads is connected to each of the middle data pads via a signal wiring.

[0018] In some embodiments, the lower chip comprises:

[0019] A plurality of edge control signal pads, located on the side of the lower chip;

[0020] A plurality of intermediate control signal pads located at the center of the lower chip;

[0021] Wherein, each of the edge control signals is connected to each of the intermediate control signal pads via a metal wiring.

[0022] In some embodiments, the plurality of edge control signal pads and the plurality of edge data pads are located on the same straight line.

[0023] In some embodiments, a ground pad or a power pad is disposed between adjacent edge data pads and between adjacent edge control signal pads.

[0024] In some embodiments, two adjacent chips in the first stack belong to different columns, two adjacent chips in the second stack belong to different columns, and some chips in the first stack and some chips in the second stack belong to the same column.

[0025] In some embodiments, the first stack or the second stack further includes a dummy chipset, so that a height of the first stack is the same as a height of the second stack.

[0026] According to a second aspect of an embodiment of the present disclosure, there is provided a packaging device, including:

[0027] Package substrate;

[0028] A first stack, located on the packaging substrate, includes a plurality of first chip groups;

[0029] A second stack, located on the packaging substrate, includes a plurality of second chip groups;

[0030] a first lead, connecting each of the first chipsets to the packaging substrate;

[0031] a second lead, connecting each of the second chipsets to the packaging substrate;

[0032] The first stack and the second stack are connected to the same signal channel, the number of the first chipset is different from the number of the second chipset, the chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns.

[0033] In some embodiments, the chips in the first chipset are connected via the first leads, and the chips in the second chipset are connected via the second leads.

[0034] In some embodiments, the first chipset includes:

[0035] A lower chip, located on the packaging substrate;

[0036] An upper chip is offset and arranged on the lower chip to expose a lower edge signal pad on the lower chip;

[0037] Wherein, a contact signal pad is arranged on the packaging substrate, and an upper edge signal pad is arranged on the side of the upper chip;

[0038] The first lead connects the contact signal pad, the lower edge signal pad and the upper edge signal pad.

[0039] In some embodiments, the lower chip also includes a lower middle signal pad, which is connected to the lower edge signal pad through a lower metal trace, and the upper chip also includes an upper middle signal pad, which is connected to the lower edge signal pad through an upper metal trace.

[0040] In some embodiments, ground pads or power pads are disposed between the lower edge signal pads and between the upper edge pads.

[0041] In some embodiments, multiple first chipsets are stacked and arranged, and multiple first chipsets are respectively connected to the same first control signal pad on the packaging substrate through the first leads, and multiple second chipsets are stacked and arranged, and multiple second chipsets are respectively connected to the same second control signal pad on the packaging substrate through the second leads.

[0042] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0043] Motherboard, including processor;

[0044] A semiconductor package is soldered on the mainboard, and the processor communicates with the semiconductor package through a signal channel;

[0045] Wherein, the semiconductor package is the above-mentioned package structure or the above-mentioned package device.

[0046] In summary, the embodiments of the present disclosure disclose a packaging structure, a packaging device, and an electronic device. The packaging structure includes a first stack and a second stack, the first stack and the second stack share the same signal channel, the number of first chipsets in the first stack is different from the number of second chipsets in the second stack, and the chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns, so that the first chipset and the second chipset can use different data signals respectively, thereby shortening the path of the data signal in the same chipset and reducing signal loss. At the same time, since the packaging structure can include two groups of chip stacks, the height of the packaging structure can be reduced and the packaging volume can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1A is a schematic diagram of an electronic device according to an exemplary embodiment;

[0048] Figure 1B is a schematic diagram of a first storage block according to an exemplary embodiment;

[0049] Figure 2 is a schematic diagram of a packaging structure according to an exemplary embodiment;

[0050] Figure 3 According to an exemplary embodiment, Figure 2 A schematic diagram of the first stack in the X direction;

[0051] Figure 4 According to an exemplary embodiment, Figure 3 A schematic diagram of the second stack in the X direction;

[0052] Figure 5 is a top view of a first stack according to an exemplary embodiment;

[0053] Figure 6 According to an exemplary embodiment, Figure 5 A schematic diagram of the first bonding pad in the X direction;

[0054] Figure 7 According to an exemplary embodiment, Figure 5 A schematic diagram of the third bonding pad in the X direction;

[0055] Figure 8 is a schematic diagram of a first upper chip according to an exemplary embodiment;

[0056] Fig. 9 is another schematic diagram of a first stack and a second stack according to an exemplary embodiment;

[0057] Fig.10is another schematic diagram of a first stack according to an exemplary embodiment;

[0058] Fig.11 is a schematic diagram of a packaging device according to an exemplary embodiment;

[0059] Fig.12 is a schematic diagram of a fourth bonding pad according to an exemplary embodiment;

[0060] Fig.13 is a schematic diagram of a packaging device according to an exemplary embodiment;

[0061] Fig.14 is another schematic diagram of a packaged device according to an exemplary embodiment;

[0062] Fig.15 is another schematic diagram showing an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0063] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0064] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0065] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0066] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0067] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0068] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0069] like Figure 1A As shown, the embodiment of the present disclosure discloses an electronic device 10. The electronic device 10 can be applied in a personal computer or a mobile electronic device. The mobile electronic device can be a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device and / or a drone.

[0070] like Figure 1A As shown, the electronic device 10 may include a processor 11 and a memory system 12. The processor 11 is a main component of the electronic device 10, which is used to process and manage instructions, such as for executing operating systems and applications. The processor 11 can be configured to enable workloads to be distributed on multiple computing entities to be processed in parallel in order to solve complex operations or tasks, such as in a distributed computing environment. The processor 11 is a functional block, firmware, or a combination thereof configured to execute one or more machine executable commands or software fragments. The processor 11 can be implemented by using hardware (that is, various circuit elements and devices) that performs calculations and other operations (e.g., control operations or configuration operations) in the electronic device 10. The processor 11 can be implemented as an integrated circuit (IC), a system on a chip (SoC), an application processor (AP), a mobile AP, a chipset, and / or a group of chips. In some embodiments, the processor 110 may be a semiconductor device that performs a memory control function, and may include a memory controller. The processor 11 may further include a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), and / or a modem.

[0071] like Figure 1AAs shown, the memory system 12 may include a first storage block 121 and a second storage block 122. The structures of the first storage block 121 and the second storage block 122 may be the same. Either the first storage block 121 or the second storage block 122 may include a plurality of memory dies 102. These memory dies 102 are all arranged on the package substrate 101. In this embodiment, the first storage block 121 and the second storage block 122 may be divided into different ranks, the first storage block 121 may belong to rank0, and the second storage block 122 may belong to rank1. Of course, the first storage block 121 may belong to rank1, and the second storage block 122 may belong to rank0. In this embodiment, a "rank" may be a collection, grouping, or other organization of memory dies in the memory system 12. Each rank may include one or more memory dies, and the number of memory dies associated with each rank may be the same or different. In this example embodiment, the memory system 12 is shown as having a dual-rank structure but is not limited thereto, and may have various other rank structures.

[0072] like Figure 1A As shown, the processor 11 communicates with the memory system 12 through a signal channel 13 (channel). Channel 13 can be a bus, which includes a command / address signal line for transmitting a command / address (CMD / ADDR), a clock signal line for transmitting data (DQ), and a clock signal line for transmitting a data clock signal (WCK and WCKB) and reading a clock signal (RDQS and RDQSB). Channel 13 may further include a clock signal line for transmitting a clock signal (CK and CKB), and a chip select signal line for transmitting a chip select signal (CS0 and CS1) to distinguish between a first storage block 121 (rank0) and a second storage block 122 (rank1), respectively. The WCK and WCKB clock signals are complementary, the RDQS and RDQSB clock signals are complementary, and the CK and CKB clock signals are complementary. The clock signals can be defined as "complementary" when the rising edge of the first clock signal is synchronized with the falling edge of the second clock signal and when the rising edge of the second clock signal is synchronized with the falling edge of the first clock signal. The first storage block 121 and the second storage block 122 may share a clock signal line, a command / address signal line, and a data line of the signal channel 13 .

[0073] like Figure 1B As shown, in order to increase the storage capacity of the electronic device 10, it is necessary to increase the storage capacity of the first storage block 121. The first storage block 121 is provided with a large number of memory dies 102 on the package substrate 101. For example, a plurality of memory dies 102 are respectively provided on the package substrate 101. The memory dies 102 may be DRAM. Figure 1BThe memory dies 102 are fixed on the package substrate 101 individually, which increases the storage capacity while also increasing the volume of the first storage block 121 , which is not conducive to applying the first storage block 121 to a miniaturized electronic device 10 .

[0074] like Figure 2 As shown, the present disclosure discloses a packaging structure 100, which has a small volume and can be applied to miniaturized electronic devices. The packaging structure 100 may include a packaging substrate 101, a first stack 200 and a second stack 300. The first stack 200 and the second stack 300 are both arranged on the packaging substrate 101. The first stack 200 and the second stack 300 can be arranged side by side. Since the packaging structure 100 can Figure 1A The first storage block 121 in the package structure 100 is replaced, so the first stack 200 and the second stack 300 can share the same signal channel. The first stack 200 and the second stack 300 both include multiple memory chips, thereby increasing the storage capacity of the package structure 100. At the same time, the first stack 200 and the second stack 300 occupy a small area of ​​the package substrate 101. The first stack 200 and the second stack 300 are arranged side by side, that is, the two are not stacked, so the height of the package structure 100 is small, thereby reducing the package volume. In the Y direction, the spacing between the first stack 200 and the second stack 300 can be between 800-1200um, for example, 900um, 1000um, 1100um, so as to ensure that there is a small spacing between the first stack 200 and the second stack 300.

[0075] like Figure 3 As shown, Figure 3 Display as Figure 2 FIG. 2 is a schematic diagram of the structure of the first stack 200 in the X direction. The first stack 200 may include a plurality of first chip groups 201, for example Figure 3It is shown that the first stack 200 includes two first chip groups 201, and may also include three or more first chip groups 201. The structures of these first chip groups 201 are the same. These first chip groups 201 can be stacked on the package substrate 101. The first chip group 201 may include a first lower chip 203 and a first upper chip 204. The first lower chip 203 may be fixed on the package substrate 101 by a first adhesive layer 202, and the first upper chip 204 may be fixed on the first lower chip 203 by a first adhesive layer 202. The first lower chip 203 and the first upper chip 204 may be the same memory chip, for example, both are DRAM, for example, DDR5 or DDR6. The first adhesive layer 202 may be DAF. The first upper chip 204 may be offset on the first lower chip 203, for example, in the X direction, the first upper chip 204 has a relative offset relative to the first lower chip 203, so that the pads on the side of the first lower chip 203 are exposed. In this embodiment, the first stack 200 includes four chips, the two first lower chips 203 are aligned in the Z direction (vertical direction) and in the X direction (horizontal direction), and the two first upper chips 204 are aligned in the Z direction (vertical direction) and in the X direction (horizontal direction), that is, in the vertical direction, the projection areas of the two first chip groups 201 overlap, so that in the horizontal direction, the upper first chip group 201 will not exceed the lower first chip group 201, so the first stack 200 can reduce the horizontal size, thereby reducing the packaging volume.

[0076] like Figure 4 As shown, Figure 4 Display as Figure 2Schematic diagram of the second stack 300 in the X direction. The second stack 300 may include a plurality of second chip groups 301, for example, three or more second chip groups 301. These second chip groups 301 are stacked. The structures of these second chip groups 301 may be the same. The second chip group 301 may include a second lower chip 303 and a second upper chip 304, and the second lower chip 303 and the second upper chip 304 may be the same memory chip. The second lower chip 303 is fixed on the package substrate 101 by the second adhesive layer 302, and the second upper chip 304 is fixed on the second lower chip 303 by the second adhesive layer 302. In the horizontal direction, the second upper chip 304 is offset and arranged on the second lower chip 303. In this embodiment, the second stack 300 may include six memory chips, and the three second lower chips 303 are aligned in the Z direction (vertical direction) and aligned in the X direction (horizontal direction). The three second upper chips 304 are aligned in the Z direction (vertical direction) and in the X direction (horizontal direction), that is, in the vertical direction, the projection areas of the three second chip groups 301 overlap, so that in the horizontal direction, the upper second chip group 301 will not exceed the lower second chip group 301, so the second stack 300 can reduce the horizontal size, thereby reducing the packaging volume.

[0077] like Figure 2-Figure 4 As shown, the first stack 200 and the second stack 300 are arranged side by side. The first stack 200 includes two first chip groups 201, and the first stack 200 includes, for example, four memory chips. The second stack 300 includes three second chip groups 301, and the second stack 300 includes, for example, six memory chips. The structure of the second chip group 301 can also be the same as the structure of the first chip group 201. The structure of the first lower chip 203 in the first stack 200 can be the same as the structure of the second lower chip 303 in the second stack 300, that is, the first lower chip 203 and the second lower chip 303 can be the same memory chip, and at the same time, the first upper chip 204 and the second upper chip 304 can be the same memory chip, and the first adhesive layer 202 and the second adhesive layer 302 are the same adhesive material. The first stack 200 and the second stack 300 are arranged side by side, which can reduce the packaging volume compared to stacking these chips into one stack.

[0078] like Figure 3-Figure 4As shown, the first stack 200 includes, for example, four memory chips, namely, in the Z direction, the first lower chip 203, the first upper chip 204, the first lower chip 203 and the first upper chip 204, respectively. At the same time, in order to better realize the transmission of data signals, two adjacent memory chips belong to different ranks, that is, in the vertical direction, from bottom to top, the first lower chip 203, for example, belongs to the first rank (rank 0), and the first upper chip 204, for example, belongs to the second rank (rank 1), that is, the two memory chips in the first chipset 201 belong to different ranks. Of course, the first lower chip 203 can belong to the second rank, and the first upper chip 204 can belong to the first rank. The second stack 300 includes, for example, six memory chips, namely, in the Z direction, the second lower chip 303, the second upper chip 304, the second lower chip 303, the second upper chip 304, the second lower chip 303, and the second upper chip 304, respectively. At the same time, in order to better realize data transmission, two adjacent memory chips belong to different ranks, namely, in the vertical direction, from bottom to top, the second lower chip 303, for example, belongs to the first rank (rank 0), and the second upper chip 304, for example, belongs to the second rank (rank 1), that is, the two memory chips in the second chipset 301 belong to different ranks. Of course, the second lower chip 303 can belong to the second rank, and the second upper chip 304 can belong to the first rank. In this embodiment, the first lower chip 203 in the first stack 200 may belong to the same column (rank 0) as the second lower chip 303 in the second stack 300, and the first upper chip 204 in the first stack 200 may belong to the same column (rank 1) as the second upper chip 304 in the second stack 300, so that some memory chips in the first stack 200 and some memory chips in the second stack 300 may belong to the same column (rank). Since some memory chips in the first stack 200 and some memory chips in the second stack 300 belong to the same column, when data is transmitted to the first stack 200 and the second stack 300 respectively, the data can be stored in the memory chips belonging to the same column in the first stack 200 and the second stack 300 respectively, thereby ensuring data consistency.

[0079] like Figure 5-Figure 6 As shown, Figure 5 Shown is a top view of a first stack 200, Figure 6The cross-sectional view of the first stack 200 is shown. Since the structures of the first stack 200 and the second stack 300 are substantially the same, the first stack 200 is used as an example in this embodiment to illustrate the connection relationship between the first stack 200 and the package substrate 101. The package substrate 101 may include a first bonding pad 104 and a second bonding pad 105, that is, on the package substrate 101, two rows of bonding pads are arranged side by side. The first bonding pad 104 is closer to the side of the package substrate 101 than the second bonding pad 105. There is a lower edge pad 206 on the side of the first lower chip 203, and there is an upper edge pad 205 on the side of the first upper chip 204. The first upper chip 204 is offset relative to the first lower chip 203, so that the lower edge pad 206 on the first lower chip 203 is exposed. The lower edge pad 206 and the upper edge pad 205 are arranged correspondingly, that is, one upper edge pad 205 corresponds to one lower edge pad 206. The lower edge pad 206 on the upper first lower chip 203 is electrically connected to the first bonding pad 104 on the package substrate 101 through the first upper lead 209. At the same time, the first upper lead 209 is also connected to the upper edge pad 205 on the upper first upper chip 204. That is, the two memory chips in the upper first chip group 201 are electrically connected through the first upper lead 209, and then are electrically connected to the package substrate 101 through the first upper lead 209. The lower edge pad 206 on the lower first lower chip 203 is electrically connected to the second bonding pad 105 on the package substrate 101 through the first lower lead 210. At the same time, the first lower lead 210 is also connected to the upper edge pad 205 on the upper first upper chip 204. That is, the two memory chips in the lower first chip group 201 are electrically connected through the first lower lead 210, and then are electrically connected to the package substrate 101 through the first lower lead 210. In this embodiment, the first upper lead 209 and the first lower lead 210 may be defined as first leads, and the first bonding pad 104 and the second bonding pad 105 may be defined as contact signal pads. Figure 5 The black dots in the first bonding pad 104 are the solder joints of the first upper lead 209 on the first bonding pad 104 .

[0080] like Figure 6As shown, this embodiment takes the first chipset 201 above as an example to illustrate data signal transmission. The first upper chip 204, for example, belongs to the first column (rank0), and the first lower chip 203, for example, belongs to the second column (rank1). The data signal (DQ) can be transmitted from the first bonding pad 104 to the first lower chip 203 and the first upper chip 204 through the first upper lead 209. In some embodiments, the data DQ received by the first stack 200 includes an 8-bit data width, and the 8-bit data width can be divided into 4-bit low-order byte data DQ0~DQ3 and 4-bit high-order byte data DQ4~DQ7. When data transmission is performed, the first column or the second column is selected by transmitting a chip selection signal to store these data. For example, 4-bit low-order byte data DQ0~DQ3 and 4-bit high-order byte data DQ4~DQ7 can be stored in the first upper chip 204 or the first lower chip 203. In some embodiments, the data DQ received by the first stack 200 includes a data width of 16 bits, and the 16-bit data width can be divided into 8-bit low-byte data DQ0~DQ7 and 8-bit high-byte data DQ8~DQ15. The 8-bit low-byte data DQ0~DQ7 and the 8-bit high-byte data DQ8~DQ15 can be stored in the first lower chip 203 or the first upper chip 204.

[0081] like Figure 5 and Figure 7As shown, a third bonding pad 106 is also provided on the package substrate 101, and the width of the third bonding pad 106 in the X direction is greater than the sum of the width of the first bonding pad 104 and the width of the second bonding pad 105, so that the area of ​​the third bonding pad 106 is greater than the sum of the area of ​​the first bonding pad 104 and the area of ​​the second bonding pad 105, that is, the area of ​​the third bonding pad 106 is relatively large. An upper edge control signal pad 207 is also provided on the side of the first upper chip 204, and a lower edge control signal pad 208 is also provided on the side of the first lower chip 203. The upper edge control signal pad 207 can be aligned with the upper edge pad 205, that is, the upper edge control signal pad 207 and the upper edge pad 205 are on the same straight line. The lower edge control signal pad 208 can be aligned with the lower edge pad 204, that is, the lower edge control signal pad 208 and the lower edge pad 204 are on the same straight line. The upper edge control signal pad 207 on the upper first upper chip 204 is connected to the lower edge control signal pad 208 on the upper first lower chip 203 through the first upper lead 209, that is, the two chips in the upper first chip group 201 are connected through the first upper lead 209, and then the first upper lead 209 is also connected to the third bonding pad 106. The upper edge control signal pad 207 on the lower first upper chip 204 is connected to the lower edge control signal pad 208 on the lower first lower chip 203 through the first lower lead 210, that is, the two chips in the lower first chip group 201 are connected through the first lower lead 210, and then the first lower lead 210 is also connected to the third bonding pad 106. In this embodiment, since the third bonding pad 106 is used to transmit the control signal, the upper first chip group 201 and the lower first chip group 201 can be connected to the same control signal pad. That is, the third bonding pad 106 may also be referred to as a first control signal pad, and the third bonding pad 106 may be used to transmit the CA (CMD / ADDR) signals of rank 0 and rank 1. It should be noted that: Figure 5 The dot on the third bonding pad 106 is a soldering point of the first upper lead 209 on the third bonding pad 106 .

[0082] like Figure 8As shown, in some embodiments, an intermediate signal pad 211 and an intermediate control signal pad 212 are provided on the middle area of ​​the first upper chip 204. The intermediate signal pad 211 can be on the same straight line as the intermediate control signal pad 212. After the signal passes through the intermediate signal pad 211 and the intermediate control signal pad 212, the signal is transmitted to the first upper chip 204. Of course, other signal pads can also be provided on the middle area of ​​the first upper chip 204. At the same time, there is an upper edge pad 205 on the side of the first upper chip 204, and the upper edge pad 205 can include an upper edge power pad 205P, an upper edge signal pad 205S and an upper edge ground pad 205G. The upper edge pad 205 can be connected to the middle signal pad 211 through the upper metal trace 213, that is, the upper edge power pad 205P can be connected to the middle power pad through the metal trace 213, the upper edge signal pad 205S can be connected to the middle signal pad through the upper metal trace 213, and the upper edge ground pad 205G can be connected to the middle ground pad through the upper metal trace 213. At the same time, two adjacent upper edge signal pads 205S can be separated by the upper edge ground pad 205G or the upper edge power pad 205P, that is, the two upper edge signal pads 205S are not closely arranged, so that the crosstalk between the signals can be improved. In some embodiments, an upper edge control signal pad 207 is also arranged at the edge of the first upper chip 204, and the upper edge control signal pad 207 can be connected to the middle control signal pad 212 through the upper metal trace 213. Since the structure of the first upper chip 204 is the same as that of the first lower chip 203, a lower middle signal pad and a lower edge signal pad are also provided on the first lower chip 203. At this time, the lower middle signal pad can also be connected to the lower edge signal pad through a lower metal trace.

[0083] like Figure 3-Figure 4 and Fig. 9 As shown, in this embodiment, the number of chips in the first stack 200 and the second stack 300 is different. For example, the first stack 200 includes four memory chips, and the second stack 300 includes six memory chips. In the first stack 200 and the second stack 300, the two memory chips in each chipset belong to different ranks, and the two memory chips in the same chipset are also connected by leads, thereby shortening the transmission path of the data signal in the same chipset and reducing signal loss. In some embodiments, if the number of chips in the first stack 200 and the second stack 300 is the same, that is, the first stack 200 and the second stack 300 both include five memory chips ( Fig. 9 ).like Fig. 9 (a) shows that the first stack 200 includes five first lower chips 203, Fig. 9(b) shows that the second stack 300 includes five second lower chips 303. In some embodiments, the five memory chips in the first stack 200, for example, belong to the same column (rank 0), and the five memory chips in the second stack 300, for example, belong to the same column (rank 1). At this time, each memory chip in the first stack 200 and the second stack 300 can be connected to the package substrate 101 with a separate lead. Then, the data path side length of the two chips belonging to the same data signal (DQ) in the first stack 200 and the second stack 300 is increased, thereby increasing signal loss. Fig. 9 The first stack 200 and the second stack 300 in the embodiment include an odd number of memory chips, even if the first stack 200 and the second stack 300 adopt Figure 4 The connection method will also result in at least one group of chips belonging to the same data signal in different columns in the first stack 200 and the second stack 300, respectively, thereby increasing the signal transmission path of the group. Therefore, this embodiment adopts an even number of memory chips in the first stack 200 and the second stack 300, respectively, thereby reducing the signal transmission path.

[0084] In some embodiments, if there is only one group of first chipsets 201 in the first stack 200, the second stack 300 can be provided with four groups of second chipsets 301. In this case, the height of the second stack 300 will be further increased, and the bonding wires of the top second chipset 301 in the second stack 300 will also be longer, which is not conducive to reducing the package volume.

[0085] like Fig.10 As shown, in some embodiments, a virtual chipset 201a may be further provided on the first stack 200, and the virtual chipset 201a may include two virtual chips 204a. The virtual chips 204a are not used to store signals. The virtual chipset 204a is located on the first chipset 201, so that the height of the first stack 200 can be the same as the height of the second stack 300, thereby improving the warping problem caused by the different heights of the first stack 200 and the second stack 300. Of course, if the height of the second stack 300 is less than the height of the first stack 200, that is, the number of chipsets in the second stack 300 is less than the number of chipsets in the first stack 200, the virtual chipset 201a may also be provided on the second stack 300, thereby improving the warping problem.

[0086] like Fig.11As shown, the embodiment of the present disclosure also discloses another packaging device 1000, which may include a packaging substrate 101, a first stack 200 and a second stack 300. The first stack 200 and the second stack 300 are placed on the packaging substrate 101. The first stack 200 is connected to the packaging pad 216 on the packaging substrate 101 through a first lead 214. The second stack 300 is connected to the packaging pad 216 on the packaging substrate 101 through a second lead 215. The first lead 214 and the second lead 215 are located on the same side of the packaging substrate 101. The first stack 200 and the second stack 300 are connected to different packaging pads 216. The structure of the first stack 200 can refer to Figure 3 The structure of the second stack 300 can refer to Figure 4 The first lead 214 may include a first upper lead 209 and a first lower lead 210. The first upper lead 209 and the first lower lead 210 may refer to Figure 6 Since the first stack 200 and the second stack 300 have the same wiring method, the second lead 215 can also refer to the first lead 214 .

[0087] like Figure 5 , Figure 6 and Fig.11 As shown, in this embodiment, the package pad 216 may include a first bonding pad 104, a second bonding pad 105, and a third bonding pad 106. The first bonding pad 104 is connected to the lower edge signal pad 206 on the upper first lower chip 203 through a first upper lead 209, and the first upper lead 209 is also connected to the upper edge signal pad 205 on the upper first upper chip 204. The second bonding pad 105 is connected to the lower edge signal pad 206 on the lower first lower chip 203 through a first lower lead 210, and the first lower lead 210 is also connected to the upper edge signal pad 205 on the lower first upper chip 204. At the same time, the two chip groups in the first stack 200 are connected to the same third bonding pad 106 through the first upper lead 209 and the first lower lead 210, respectively. In this embodiment, the first bonding pad 104 and the second bonding pad 105 can also be called contact signal pads, and the third bonding pad 106 can be defined as a first control signal pad.

[0088] like Fig.12As shown, the package substrate 101 may further include a fourth bonding pad 217, a fifth bonding pad 218, a sixth bonding pad 219, and a second control signal pad 220. A plurality of fourth bonding pads 217 may be arranged in a column, a plurality of fifth bonding pads 218 may be arranged in a column, a sixth bonding pad 219 may be arranged in a column, and a plurality of second control signal pads 220 may be arranged in a column. The fourth bonding pad 217, the fifth bonding pad 218, the sixth bonding pad 219, and the second control signal pad 220 are used to provide signals for the second stack 300. The fourth bonding pad 217, the fifth bonding pad 218, the sixth bonding pad 219, and the second control signal pad 220 may be located on the same side of the package substrate 101. At the same time, the first bonding pad 104 may be located in the same column as the fifth bonding pad 218, and the second bonding pad 105 may be located in the same column as the sixth bonding pad 219. The fourth bonding pad 217 can be connected to the uppermost second chipset 301 in the second stack 300 through the second lead 215, the fifth bonding pad 218 can be connected to the middle second chipset 301 in the second stack 300 through the second lead 215, and the sixth bonding pad 219 can be connected to the lowermost second chipset 301 in the second stack 300 through the second lead 215. The second control signal pad 220 can be connected to all the second chipsets 301 through the second lead 215, that is, the three second chipsets 301 in the second stack 300 are connected to the same second control signal pad 220.

[0089] like Fig.13 As shown, in this embodiment, the first stack 200 and the second stack 300 are arranged on the front side of the package substrate 101, and there is an external terminal 1011 on the back side of the package substrate 101. The external terminal 1011 can be a welding ball, a welding bump, a micro bump, etc. The package device 1000 can be directly welded on the main board (PCB) through the external terminal 1011. The package device 1000 can be a ball grid array (BGA), a chip scale package (CSP), a plastic lead chip carrier (PLCC), a plastic dual in-line package (PDIP), a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system-level package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), and a wafer-level processing stack package (WSP).

[0090] like Fig.14As shown, the embodiment of the present disclosure also discloses another packaging device 1000. The packaging device 1000 may include a packaging substrate 101, a first stack 200 and a second stack 300. The first stack 200 and the second stack 300 are located on the front of the packaging substrate 101. The first stack 200, for example, includes four first lower chips 203, which are offset and stacked to form a step shape. The first stack 200 may include two chipsets, the two lower first chips 203 below form a chipset, and the two lower first chips 203 above form a chipset. The two chips in each chipset are connected by a first lead 214, and are connected to the packaging substrate 101 by the first lead 214. The second stack 300, for example, includes six second lower chips 303, which are offset and stacked to form a step shape, and at the same time, the offset direction of the first stack 200 is opposite to the offset direction of the second stack 300. The second stack 300 may include three chipsets, wherein the two lower second chips 303 below form a chipset, the two lower second chips 303 above form a chipset, and the two lower second chips 303 in the middle form a chipset. The two chips in each chipset are connected by the second lead 215, and are also connected to the package substrate 101 by the second lead 215. The second lead 215 and the first lead 214 are located on opposite sides of the package substrate 101. There are external terminals 1011 on the back of the package substrate 101, and the external terminals 1011 are, for example, solder balls, through which the package device 1000 can be directly fixed on the mainboard.

[0091] like Fig.14As shown, in this embodiment, the first stack 200 and the second stack 300 are arranged on the package substrate 101, the memory chip of the first stack 200 is offset in the direction of the second stack 300, and the memory chip in the second stack 300 is offset in the direction of the first stack 200. Since the number of memory chips in the first stack 200 and the second stack 300 is different, the heights of the first stack 200 and the second stack 300 are different, which leads to the first protrusion 221 of the first stack 200 being located directly below the second protrusion 222 of the second stack 300, that is, the second protrusion 222 and the first protrusion 221 are vertically overlapped. In this embodiment, the first protrusion 221 is the protruding portion of the uppermost first lower chip 203 in the first stack 200, and the second protrusion 222 is the protruding portion of the uppermost second lower chip 303 in the second stack 300. In this embodiment, the first protrusion 221 may protrude toward the second stack 300, and the second protrusion 222 may protrude toward the first stack 200. Therefore, the first protrusion 221 may be located directly below the second protrusion 222 and may be spaced apart from the second protrusion 221, so that the first protrusion 221 and the second protrusion 222 overlap each other in the vertical direction. Therefore, the first stack 200 and the second stack 300 are arranged side by side on the packaging substrate 101, and the total width of the first stack 200 and the second stack 300 can also be reduced, thereby reducing the width of the packaging device 1000, thereby reducing the packaging volume.

[0092] like Fig.15 As shown, the embodiment of the present disclosure also discloses another electronic device 10, which may include a mainboard 15, on which there are a processor 11 and a plurality of semiconductor packages 14, and the processor 11 communicates with the plurality of semiconductor packages 14 through a signal channel 13. The structure of the semiconductor package 14 can refer to the above-mentioned package device 1000. The electronic device 10 may include one or more of the following: for example, a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop PC, a laptop PC, a netbook computer, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MPEG-1 audio layer 3 (MP3) player, a mobile medical device, a camera, a household appliance, a medical device, an Internet of Things (IoT) device, and a wearable device. The wearable device may be an accessory type, a fabric or clothing type, a body attachment type, or an implantable circuit type. The accessory wearable device may be, for example, a watch, a ring, a bracelet, an anklet, a necklace, glasses, contact lenses, or a head-mounted device (HMD). The electronic device 10 may also be used in large servers, such as data centers, AI computers, and other fields.

[0093] In summary, the embodiment of the present disclosure discloses a packaging structure, which includes two stacking members, which are arranged side by side, so that the height of a single stacking member is low, and the volume of the packaging structure can be reduced. The packaging structure includes a first stacking member and a second stacking member, the first stacking member and the second stacking member share the same signal channel, the number of first chipsets in the first stacking member is different from the number of second chipsets in the second stacking member, and the chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns, so that the first chipset and the second chipset can use different data signals respectively, thereby shortening the path of the data signal in the same chipset and reducing signal loss.

[0094] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A packaging structure, characterized in that: include: Package substrate; A first stack, located on the packaging substrate, includes a plurality of first chip groups; A second stack, located on the packaging substrate, includes a plurality of second chip groups; The first stack and the second stack are connected to the same signal channel, the number of the first chipset is different from the number of the second chipset, the chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns.

2. The packaging structure according to claim 1, characterized in that: Each of the first chipsets is connected to each data signal respectively, and a plurality of the first chipsets are connected to the same control signal. Each of the second chipsets is connected to each data signal respectively, and a plurality of the second chipsets are connected to the same control signal.

3. The packaging structure according to claim 1 or 2, characterized in that: The first chipset comprises: Chip down; an upper chip, offset and arranged on the lower chip; The lower chip and the upper chip are connected via leads, and the leads are connected to the packaging substrate.

4. The packaging structure according to claim 3, characterized in that: In the vertical direction, the projection areas of the plurality of first chip groups overlap, and the projection areas of the plurality of second chip groups overlap.

5. The packaging structure according to claim 3, characterized in that: The structure of the upper chip is the same as that of the lower chip, and the lower chip comprises: A plurality of edge data pads, located on the side of the lower chip; A plurality of intermediate data pads located at the center of the lower chip; Wherein, each of the edge data pads is connected to each of the middle data pads via a signal wiring.

6. The packaging structure according to claim 5, characterized in that: The lower chip comprises: A plurality of edge control signal pads, located on the side of the lower chip; A plurality of intermediate control signal pads located at the center of the lower chip; Wherein, each of the edge control signals is connected to each of the intermediate control signal pads via a metal wiring.

7. The packaging structure according to claim 5 or 6, characterized in that: The plurality of edge control signal pads and the plurality of edge data pads are located on the same straight line.

8. The packaging structure according to claim 5 or 6, characterized in that: A ground pad or a power pad is disposed between adjacent edge data pads and between adjacent edge control signal pads.

9. The packaging structure according to claim 1, characterized in that: Two adjacent chips in the first stack belong to different columns, two adjacent chips in the second stack belong to different columns, and some chips in the first stack and some chips in the second stack belong to the same column.

10. The packaging structure according to claim 1, characterized in that: A dummy chip group is further included on the first stack or the second stack, so that a height of the first stack is the same as a height of the second stack.

11. A packaging device, characterized in that: include: Package substrate; A first stack, located on the packaging substrate, includes a plurality of first chip groups; A second stack, located on the packaging substrate, includes a plurality of second chip groups; a first lead, connecting each of the first chipsets to the packaging substrate; a second lead, connecting each of the second chipsets to the packaging substrate; The first stack and the second stack are connected to the same signal channel, the number of the first chipset is different from the number of the second chipset, the chips in the first chipset belong to different columns, and the chips in the second chipset belong to different columns.

12. The packaged device according to claim 11, characterized in that: The chips in the first chipset are connected via the first leads, and the chips in the second chipset are connected via the second leads.

13. The packaged device according to claim 11, characterized in that: The first chipset comprises: A lower chip, located on the packaging substrate; An upper chip is offset and arranged on the lower chip to expose a lower edge signal pad on the lower chip; Wherein, a contact signal pad is arranged on the packaging substrate, and an upper edge signal pad is arranged on the side of the upper chip; The first lead connects the contact signal pad, the lower edge signal pad and the upper edge signal pad.

14. The packaged device according to claim 13, characterized in that: The lower chip further includes a lower middle signal pad, which is connected to the lower edge signal pad via a lower metal trace, and the upper chip further includes an upper middle signal pad, which is connected to the lower edge signal pad via an upper metal trace.

15. The packaged device according to claim 13 or 14, characterized in that: A ground pad or a power pad is disposed between the lower edge signal pads and between the upper edge pads.

16. The packaged device according to claim 13 or 14, characterized in that: Multiple first chipsets are stacked and connected to the same first control signal pad on the packaging substrate through the first leads, and multiple second chipsets are stacked and connected to the same second control signal pad on the packaging substrate through the second leads.

17. An electronic device, characterized in that: include: Motherboard, including processor; A semiconductor package is soldered on the mainboard, and the processor communicates with the semiconductor package through a signal channel; Wherein, the semiconductor package includes the packaging structure described in any one of claims 1-10, or includes the packaging device described in any one of claims 11-16.

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