MOS tube dead zone adjusting circuit
Through the MOS tube dead zone adjustment circuit, the charge and discharge characteristics of the MOS tube are used to introduce dead zones, which solves the problems of high power consumption and large integrated area of the existing RC delay circuit, and realizes high-precision signal control at low voltages.
Patent Information
- Application Number
- CN202411917483.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-04-25
AI Technical Summary
The existing RC delay circuits have high power consumption and large integrated chip area in deadband regulation, making it difficult to meet the requirements of low voltage and high precision.
The MOS tube dead-band adjustment circuit is adopted to introduce dead-band by controlling the charging and discharging of the MOS tube, and the signal delay is achieved using the parasitic capacitance characteristics of the MOS tube to accurately adjust the dead-band time.
It reduces the power consumption of the circuit and the integrated chip area, improves the working ability and accuracy at low voltages, and enhances the stability and reliability of signal control.
Smart Images
Figure CN119891739A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of signal control, and in particular to a MOS tube dead zone regulating circuit. Background Art
[0002] Dead zone adjustment circuits are widely used in motor control, power supply control, LED drive and other fields. By introducing dead zones in the drive signal and setting the dead zone time reasonably, the high-frequency noise and oscillation problems in the system can be effectively reduced, thereby improving the stability and reliability of the system. The existing technology usually uses RC delay circuits to implement the dead zone adjustment function, but the circuit has the problems of high power consumption and large integrated chip area, and it is difficult to meet the low voltage and high precision requirements of some technical fields for dead zone adjustment circuits. Summary of the invention
[0003] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a MOS tube dead zone adjustment circuit, which introduces a dead zone into a signal and adjusts and controls it by controlling the charge and discharge of the MOS tube. Compared with the RC delay circuit, the circuit has lower power consumption, a smaller integrated chip area, can operate at a low voltage, and has higher precision.
[0004] In order to achieve the above object, the present invention adopts the following technical solutions:
[0005] A MOS tube dead zone adjustment circuit comprises a signal delay circuit and a waveform conversion unit. The signal delay circuit comprises at least three MOS tubes. The output end of the signal delay circuit is connected to the input end of the waveform conversion unit. The signal delay circuit is used to introduce a dead zone to the rising edge or falling edge of an input signal. The waveform conversion unit is used to perform waveform conversion on the input signal processed by the signal delay circuit and output it.
[0006] The signal delay circuit includes a rising edge delay unit and a falling edge delay unit, each of which includes at least three MOS tubes, and the output ends of the rising edge delay unit and the falling edge delay unit are connected to the input end of the waveform conversion unit. The rising edge delay unit is used to introduce a dead zone to the rising edge of the input signal, and the falling edge delay unit is used to introduce a dead zone to the falling edge of the input signal.
[0007] The signal delay circuit also includes a level control terminal S, which is connected to the rising edge delay unit and the falling edge delay unit respectively, and is used to control the signal delay circuit to switch the working state between the rising edge delay unit and the falling edge delay unit.
[0008] The rising edge delay unit includes a field effect transistor M1, a field effect transistor M3, and a field effect transistor M5. The gate of the field effect transistor M1 is the first signal input terminal Vin1, the source thereof is the reference voltage terminal Vref, and the drain thereof is respectively connected to the drain of the field effect transistor M3 and the input terminal of the waveform conversion unit. The gate of the field effect transistor M3 is connected to the level control terminal S, and the source thereof is connected to the drain of the field effect transistor M5. The gate of the field effect transistor M5 is the dead time adjustment terminal Vc1, and the source thereof is the ground terminal VSS.
[0009] The falling edge delay unit includes a field effect transistor M2, a field effect transistor M4, and a field effect transistor M6. The gate of the field effect transistor M2 is the dead time adjustment terminal Vc2, the source thereof is the reference voltage terminal Vref, the drain thereof is connected to the drain of the field effect transistor M4, the gate of the field effect transistor M4 is connected to the level control terminal S, the source thereof is respectively connected to the drain of the field effect transistor M6 and the input terminal of the waveform conversion unit, the gate of the field effect transistor M6 is the second signal input terminal Vin2, and the source thereof is the ground terminal VSS.
[0010] When the level control terminal S is at a high level, the field effect tube M3 is turned on, the rising edge delay unit is in a working state, the field effect tube M4 is turned off, and the falling edge delay unit is in a non-working state; when the level control terminal S is at a low level, the field effect tube M3 is turned off, the rising edge delay unit is in a non-working state, the field effect tube M4 is turned on, and the falling edge delay unit is in a working state.
[0011] The field effect transistors M1 , M2 and M5 are enhanced PMOS transistors, and the field effect transistors M3 , M4 and M6 are enhanced NMOS transistors.
[0012] The dead time adjustment terminal Vc1 and the dead time adjustment terminal Vc2 are both constant voltage sources. The dead time adjustment terminal Vc1 controls the field effect transistor M5 to work in the saturation region, and the dead time adjustment terminal Vc2 controls the field effect transistor M2 to work in the saturation region.
[0013] The input signals of the first signal input terminal Vin1 and the second signal input terminal Vin2 are both square wave signals with the same period.
[0014] The waveform conversion unit is a comparator, the output end of the signal delay circuit is connected to the inverting input end of the comparator, and the non-inverting input end of the comparator is connected to the reference voltage end Vref.
[0015] Beneficial effects:
[0016] The present invention provides a MOS tube dead zone adjustment circuit. The signal delay circuit in the circuit utilizes the characteristics of the parasitic capacitance of the MOS tube and introduces a dead zone to the rising edge or falling edge of the input signal by controlling and adjusting the charging and discharging mode of the MOS tube. In addition, based on the sensitivity of the MOS tube, the dead zone time can be accurately adjusted to remove the oscillation noise in the input signal, thereby improving the stability and reliability of signal control. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A circuit structure diagram of a MOS tube dead zone adjustment circuit provided by the present invention;
[0018] Figure 2 A rising edge dead zone timing diagram based on a MOS tube dead zone adjustment circuit provided by the present invention;
[0019] Figure 3 The falling edge dead zone timing diagram based on the MOS tube dead zone adjustment circuit provided by the present invention;
[0020] Explanation of main component symbols: 1- signal delay circuit, 11- rising edge delay unit, 12- falling edge delay unit, 2- waveform conversion unit. DETAILED DESCRIPTION
[0021] The present invention provides a MOS tube dead zone adjustment circuit. In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not used to limit the present invention.
[0022] In the description of the present invention, it should be understood that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
[0023] See also Figure 1-3 The present invention provides a MOS tube dead zone adjustment circuit, including a signal delay circuit 1 and a waveform conversion unit 2. The signal delay circuit 1 includes at least three MOS tubes, and the output end of the signal delay circuit 1 is connected to the input end of the waveform conversion unit 2. The signal delay circuit 1 utilizes the characteristics of the parasitic capacitance charging and discharging current of the MOS tube to perform delay processing when the input signal jumps, that is, at the rising edge or falling edge of the input signal, that is, introduces a dead zone. Due to the introduction of the dead zone, the rising edge or falling edge of the input signal is converted into an oblique waveform signal. The waveform conversion unit 2 is used to perform waveform conversion and output the input signal processed by the signal delay circuit 1, that is, the input signal with an oblique waveform signal.
[0024] Specifically, the signal delay circuit 1 may include a rising edge delay unit 11 and a falling edge delay unit 12, so that the signal delay circuit 1 can realize two functions of introducing a dead zone into the rising edge and the falling edge of the input signal. The rising edge delay unit 11 and the falling edge delay unit 12 are also provided with at least three MOS tubes, the rising edge delay unit 11 is used to introduce a dead zone into the rising edge of the input signal, and the falling edge delay unit 12 is used to introduce a dead zone into the falling edge of the input signal.
[0025] Furthermore, the signal delay circuit 1 can be connected to the rising edge delay unit 11 and the falling edge delay unit 12 respectively through the level control terminal S, and control the signal delay circuit 1 to switch the working state between the rising edge delay unit 11 and the falling edge delay unit 12, thereby respectively realizing the two functions of introducing a dead zone into the rising edge of the input signal and introducing a dead zone into the falling edge of the input signal.
[0026] See also Figure 1 In the present embodiment, specifically, the rising edge delay unit 11 includes a field effect transistor M1, a field effect transistor M3, and a field effect transistor M5. The gate of the field effect transistor M1 is the first signal input terminal Vin1, the source thereof is the reference voltage terminal Vref, and the drain thereof is respectively connected to the drain of the field effect transistor M3 and the input terminal of the waveform conversion unit 2, the gate of the field effect transistor M3 is connected to the level control terminal S, and the source thereof is connected to the drain of the field effect transistor M5, the gate of the field effect transistor M5 is the dead time adjustment terminal Vc1, and the source thereof is the ground terminal VSS.
[0027] The falling edge delay unit 12 includes a field effect transistor M2, a field effect transistor M4, and a field effect transistor M6. The gate of the field effect transistor M2 is the dead time adjustment terminal Vc2, the source thereof is the reference voltage terminal Vref, the drain thereof is connected to the drain of the field effect transistor M4, the gate of the field effect transistor M4 is connected to the level control terminal S, the source thereof is respectively connected to the drain of the field effect transistor M6 and the input terminal of the waveform conversion unit 2, the gate of the field effect transistor M6 is the second signal input terminal Vin2, and the source thereof is the ground terminal VSS.
[0028] Furthermore, the field effect transistors M1, M2 and M5 are enhanced PMOS transistors, and the field effect transistors M3, M4 and M6 are enhanced NMOS transistors.
[0029] Further, the dead time adjustment terminal Vc1 and the dead time adjustment terminal Vc2 are both constant voltage sources, the dead time adjustment terminal Vc1 is used to adjust the dead time introduced by the rising edge delay unit 11 to the rising edge of the input signal, and the dead time adjustment terminal Vc2 is used to adjust the dead time introduced by the falling edge delay unit 12 to the falling edge of the input signal. Preferably, the dead time adjustment terminal Vc1 controls the field effect transistor M5 to work in the saturation region, and the dead time adjustment terminal Vc2 controls the field effect transistor M2 to work in the saturation region.
[0030] In this embodiment, when the field effect transistor M5 works in the saturation region, ignoring the channel length modulation effect, its drain discharge current is a fixed current; similarly, when the field effect transistor M2 works in the saturation region, its drain discharge current is a fixed current.
[0031] Furthermore, the input signals of the first signal input terminal Vin1 and the second signal input terminal Vin2 are square wave signals with the same period.
[0032] Furthermore, the waveform conversion unit 2 uses a comparator, the output end of the signal delay circuit is connected to the inverting input end of the comparator, and the non-inverting input end of the comparator is connected to the reference voltage end Vref. Figure 2-3 The signal output by the comparator is a square wave signal which is inverted and has a dead zone introduced.
[0033] In this embodiment, the working states are divided into the following two types:
[0034] Working status 1, see Figure 2 When the level control terminal S inputs a high level, the field effect tube M3 is turned on, the rising edge delay unit 11 is in a working state, the field effect tube M4 is turned off, and the falling edge delay unit 12 is in a non-working state. As the square wave signal input by the first signal input terminal Vin1 changes, the following situations occur:
[0035] 1. When the square wave signal inputted by the first signal input terminal Vin1 is at a low level, the field effect tube M1 is turned on, and the current flows through the field effect tube M1 to the output terminal Vo1 of the rising edge delay unit 11, and the output terminal Vo1 is at a high level state;
[0036] 2. When the square wave signal inputted by the first signal input terminal Vin1 is at a high level, the field effect tube M1 is turned off, and the output terminal Vo1 of the rising edge delay unit 11 is grounded through the field effect tube M5, that is, the output terminal Vo1 is at a low level state;
[0037] 3. When the square wave signal inputted by the first signal input terminal Vin1 is in the rising edge jump, the field effect tube M1 changes from on to off, the output terminal Vo1 of the rising edge delay unit 11 is grounded through the field effect tube M5, and the drain of the field effect tube M5 discharges, delaying the time for the output terminal Vo1 to change from a high level to a low level, that is, the dead time Td;
[0038] 4. When the square wave signal inputted by the first signal input terminal Vin1 is in a falling edge transition, the field effect tube M1 changes from cut-off to conduction, and the current flows directly through the field effect tube M1 to the output terminal Vo1 of the rising edge delay unit 11, and the output terminal Vo1 changes from a low level to a high level state instantly.
[0039] Working state 2, when the level control terminal S inputs a low level, the field effect tube M3 is turned off, the rising edge delay unit 11 is in a non-working state, the field effect tube M4 is turned on, and the falling edge delay unit 12 is in a working state. As the square wave signal input by the second signal input terminal Vin2 changes, the following situations occur:
[0040] 1. When the square wave signal inputted by the second signal input terminal Vin2 is at a high level, the field effect tube M6 is turned on. At this time, the output terminal Vo1 of the falling edge delay unit 12 is grounded through the field effect tube M6, that is, the output terminal Vo1 is at a low level state;
[0041] 2. When the square wave signal inputted by the second signal input terminal Vin2 is at a low level, the field effect transistor M6 is turned off, and the current flows to the output terminal Vo1 of the falling edge delay unit 12 through the field effect transistors M2 and M4, and the output terminal Vo1 is at a high level state;
[0042] 3. When the square wave signal input by the second signal input terminal Vin2 is in the rising edge jump, the field effect tube M6 changes from cut-off to conduction, the output terminal Vo1 of the falling edge delay unit is grounded through the field effect tube M6, and the output terminal Vo1 instantly changes from a high level to a low level state.
[0043] 4. When the square wave signal input by the second signal input terminal Vin2 is in a falling edge transition, the field effect tube M6 changes from on to off, and the current flows through the field effect tube M2 and the field effect tube M4 to the output terminal Vo1 of the falling edge delay unit, and at the same time charges the field effect tube M2. During the charging process of the field effect tube M2, a reverse current is generated, which delays the time for Vo1 to change from a low level to a high level, that is, the dead time Td.
[0044] In summary, the signal delay circuit 1 in this circuit utilizes the characteristics of the parasitic capacitance of the MOS tube and introduces a dead zone to the rising edge or falling edge of the input signal by controlling and adjusting the charging and discharging of the MOS tube. In addition, based on the sensitivity of the MOS tube, the dead zone time can be accurately adjusted to remove the oscillation noise in the input signal, thereby improving the stability and possibility of signal control.
[0045] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of the present invention, and all these changes or substitutions should fall within the protection scope of the claims attached to the present invention.
Claims
1. A MOS tube dead zone adjustment circuit, characterized in that: It includes a signal delay circuit and a waveform conversion unit. The signal delay circuit includes at least three MOS tubes. The output end of the signal delay circuit is connected to the input end of the waveform conversion unit. The signal delay circuit is used to introduce a dead zone to the rising edge or falling edge of the input signal. The waveform conversion unit is used to perform waveform conversion on the input signal processed by the signal delay circuit and output it.
2. The MOS tube dead zone adjustment circuit according to claim 1, characterized in that: The signal delay circuit includes a rising edge delay unit and a falling edge delay unit, each of which includes at least three MOS tubes, and the output ends of the rising edge delay unit and the falling edge delay unit are connected to the input end of the waveform conversion unit. The rising edge delay unit is used to introduce a dead zone to the rising edge of the input signal, and the falling edge delay unit is used to introduce a dead zone to the falling edge of the input signal.
3. The MOS tube dead zone adjustment circuit according to claim 2, characterized in that: The signal delay circuit also includes a level control terminal S, which is connected to the rising edge delay unit and the falling edge delay unit respectively, and is used to control the signal delay circuit to switch the working state between the rising edge delay unit and the falling edge delay unit.
4. The MOS tube dead zone adjustment circuit according to claim 3, characterized in that: The rising edge delay unit includes a field effect transistor M1, a field effect transistor M3, and a field effect transistor M5. The gate of the field effect transistor M1 is the first signal input terminal Vin1, the source thereof is the reference voltage terminal Vref, and the drain thereof is respectively connected to the drain of the field effect transistor M3 and the input terminal of the waveform conversion unit. The gate of the field effect transistor M3 is connected to the level control terminal S, and the source thereof is connected to the drain of the field effect transistor M5. The gate of the field effect transistor M5 is the dead time adjustment terminal Vc1, and the source thereof is the ground terminal VSS.
5. The MOS tube dead zone adjustment circuit according to claim 4, characterized in that: The falling edge delay unit includes a field effect transistor M2, a field effect transistor M4, and a field effect transistor M6. The gate of the field effect transistor M2 is the dead time adjustment terminal Vc2, the source thereof is the reference voltage terminal Vref, the drain thereof is connected to the drain of the field effect transistor M4, the gate of the field effect transistor M4 is connected to the level control terminal S, the source thereof is respectively connected to the drain of the field effect transistor M6 and the input terminal of the waveform conversion unit, the gate of the field effect transistor M6 is the second signal input terminal Vin2, and the source thereof is the ground terminal VSS.
6. The MOS tube dead zone adjustment circuit according to claim 5, characterized in that: When the level control terminal S is at a high level, the field effect tube M3 is turned on, the rising edge delay unit is in a working state, the field effect tube M4 is turned off, and the falling edge delay unit is in a non-working state; when the level control terminal S is at a low level, the field effect tube M3 is turned off, the rising edge delay unit is in a non-working state, the field effect tube M4 is turned on, and the falling edge delay unit is in a working state.
7. The MOS tube dead zone adjustment circuit according to claim 5, characterized in that: The field effect transistors M1 , M2 and M5 are enhanced PMOS transistors, and the field effect transistors M3 , M4 and M6 are enhanced NMOS transistors.
8. The MOS tube dead zone adjustment circuit according to claim 7, characterized in that: The dead time adjustment terminal Vc1 and the dead time adjustment terminal Vc2 are both constant voltage sources. The dead time adjustment terminal Vc1 controls the field effect transistor M5 to work in the saturation region, and the dead time adjustment terminal Vc2 controls the field effect transistor M2 to work in the saturation region.
9. The MOS tube dead zone adjustment circuit according to claim 5, characterized in that: The input signals of the first signal input terminal Vin1 and the second signal input terminal Vin2 are square wave signals with the same period.
10. The MOS tube dead zone adjustment circuit according to claim 1, characterized in that: The waveform conversion unit is a comparator, the output end of the signal delay circuit is connected to the inverting input end of the comparator, and the non-inverting input end of the comparator is connected to the reference voltage end Vref.