Low-phase noise series resonance D-type oscillator
By using the combination of LC series resonance, differential CMOS active circuit and RC self-biasing circuit in the voltage-controlled oscillator, the problem that traditional oscillators are difficult to achieve low phase noise at low power consumption is solved, and a Class D oscillator with low noise and low power consumption is realized.
Patent Information
- Application Number
- CN202411944843.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-27
- Publication Date
- 2025-04-25
AI Technical Summary
While maintaining low power consumption, traditional voltage-controlled oscillators are difficult to achieve low phase noise performance, especially because series resonance requires a large operating current, which increases power consumption.
Low-phase noise series resonant Class D oscillators are adopted, including LC series resonant circuit, differential CMOS active circuit and RC self-biasing circuit. Through the cross-coupling of inductor capacitor series resonance and differential CMOS active circuit, combined with RC self-biasing circuit, low noise and low power consumption performance are achieved.
A Class D oscillator with low phase noise and low power consumption is realized. By improving the oscillation amplitude and current efficiency, the impact of current noise on phase noise is reduced, ensuring excellent low noise and low power consumption performance.
Smart Images
Figure CN119891956A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of oscillators, and in particular to a low phase noise series resonant class D oscillator. Background Art
[0002] An integrated voltage-controlled oscillator (VCO) is a circuit that can generate an oscillation signal under the control of an input voltage. Voltage-controlled oscillators are widely used in phase-locked loop clock generation, phase modulation, frequency modulation, and other scenarios. By adjusting the control voltage, the resonant frequency of the resonant circuit can be smoothly changed within a specific range, thereby achieving precise control of the output frequency.
[0003] The most challenging problem in voltage-controlled oscillator design is to achieve low phase noise performance while maintaining low power consumption. Low power design usually limits the supply of current and voltage, which may lead to a reduction in the gain of the device, directly affecting the phase noise performance.
[0004] In the traditional LC parallel resonant voltage-controlled oscillator, the LC resonant circuit voltage is equal to the drain voltage of the active circuit. Therefore, based on the reliability of the transistor, the drain voltage V0 is the maximum voltage swing of the resonant circuit. In the series resonant circuit, due to the series connection of the inductor and capacitor, the maximum voltage swing can be Q times the drain voltage V0, where Q is the quality factor of the resonant circuit, which greatly reduces the phase noise. However, the series resonance consumes a large operating current, which increases the power consumption. Summary of the invention
[0005] A low phase noise series resonant class D oscillator proposed by the present invention can solve at least one of the above technical problems.
[0006] To achieve the above object, the present invention adopts the following technical solutions:
[0007] A low phase noise series resonant class D oscillator comprises an LC series resonant circuit, a differential CMOS active circuit and an RC self-bias circuit; the resonant voltage of the series resonant circuit can reach QV0, the drain end or the gate end of the differential CMOS active circuit is connected to the LC series resonant circuit, and the RC self-bias circuit connects the gate end of one side of the CMOS active circuit and the drain end of the opposite side.
[0008] Furthermore, the LC series resonant circuit includes variable capacitor Cv1 and variable capacitor Cv2, inductor L1 and inductor L2, variable capacitor Cv1 and variable capacitor Cv2 are connected in series and connected to the ground in the middle; inductor L1, variable capacitor Cv1, variable capacitor Cv2, and inductor L2 are connected in series in sequence.
[0009] The differential CMOS active circuit includes PMOS switch tubes PM1 and PM2, and NMOS switch tubes NM1 and NM2, wherein:
[0010] The gate terminals of PM1 and NM1 are connected, and the gate terminals of PM2 and NM2 are connected;
[0011] The drain terminals of PM1 and NM1 are connected, and the drain terminals of PM2 and NM2 are connected;
[0012] The source ends of NM1 and NM2 are connected, and the ground is connected in the middle;
[0013] The LC series resonant circuit is connected to the drain terminals of PM2 and NM2 respectively;
[0014] The LC series resonant circuit is connected to the drain terminals of PM1 and NM1 respectively.
[0015] Further, the RC self-bias circuit includes resistors R1 and R2, capacitors C1, C2, C3 and C4, wherein:
[0016] The first end of the resistor R1 is connected to the drain end of PM1 and NM1 respectively, and the second end is connected to the gate end of PM2 and NM2 respectively;
[0017] The first end of the resistor R2 is connected to the gate end of PM1 and NM1 respectively, and the second end is connected to the drain end of PM1 and NM2 respectively;
[0018] The first end of the capacitor C1 is connected to the drain terminals of PM1 and NM1 respectively, and the second end is connected to the gate terminals of PM2 and NM2 respectively;
[0019] The first end of the capacitor C2 is connected to the gate end of PM1 and NM1 respectively, and the second end is connected to the drain end of PM1 and NM2 respectively;
[0020] The capacitor C1 is connected in parallel with the resistor R1, and the capacitor C2 is connected in parallel with the resistor R2;
[0021] A first end of C3 is connected to the ground, and a second end is connected to the drain ends of PM1 and NM1. A first end of C4 is connected to the ground, and a second end is connected to the drain ends of PM2 and NM2.
[0022] In the second aspect, both ends of the LC series resonant circuit are connected to the drain end of the switch tube respectively; capacitors C3 and C4 are respectively composed of parasitic capacitances from PM1 and NM1, PM2 and NM2 to ground.
[0023] It can be seen from the above technical solution that the low phase noise series resonant class D oscillator of the present invention includes a differential CMOS cross-coupling circuit, an inductor capacitor (LC) series resonant circuit and a resistor capacitor (RC) self-bias circuit. This circuit increases the oscillation amplitude on the one hand and improves the current efficiency on the other hand through the inductor capacitor series resonance, thereby realizing a low noise, low power consumption class D oscillator.
[0024] The LC series resonant class D oscillator of the present invention increases the oscillation amplitude and reduces the influence of current noise on phase noise compared to class A and class B oscillators. In addition, the efficient switch mode operation of the class D oscillator ensures its excellent low noise and low power consumption performance.
[0025] In general, since the LC resonant circuit voltage of the traditional LC parallel resonant voltage-controlled oscillator is equal to the drain voltage of the active circuit, based on the reliability of the transistor, its drain voltage V0 is the maximum voltage swing of the resonant circuit. Since the inductor and capacitor are connected in series, the maximum voltage swing of the series resonant circuit can be Q times the drain voltage V0, where Q is the quality factor of the resonant circuit, thereby greatly reducing the phase noise. However, the series resonance consumes a large operating current and increases the power consumption. The present invention can achieve low power consumption and low phase noise performance through the RC self-biased D-type active circuit structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 is a schematic structural diagram of Embodiment 1 of the present invention;
[0027] Figure 2 It is a structural diagram of embodiment 2 of the present invention. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.
[0029] The voltage controlled oscillator provided by the embodiment of the present invention is as follows Figure 1 As shown, it includes an LC series resonant circuit, a differential CMOS active circuit and an RC self-bias circuit; wherein:
[0030] The drain terminal or gate terminal of the differential CMOS active circuit is connected to an LC series resonant circuit, and the RC self-bias circuit connects the gate terminal on one side of the CMOS active circuit and the drain terminal on the opposite side.
[0031] The LC series resonant circuit includes a variable capacitor Cv1 and a variable capacitor Cv2, an inductor L1 and an inductor L2, the variable capacitor Cv1 and the variable capacitor Cv2 are connected in series and connected to the ground in the middle; the inductor L1, the variable capacitor Cv1, the variable capacitor Cv2, and the inductor L2 are connected in series in sequence.
[0032] The series resonant structure enables the oscillator to maintain the oscillation power of a given frequency and consume the generated thermal noise. It has good selectivity and stability near the resonant frequency, effectively suppresses unnecessary frequency components, and provides a clear signal.
[0033] The differential CMOS active circuit includes PMOS switch tubes PM1 and PM2, and NMOS switch tubes NM1 and NM2, wherein:
[0034] The gate terminals of PM1 and NM1 are connected, and the gate terminals of PM2 and NM2 are connected;
[0035] The drain terminals of PM1 and NM1 are connected, and the drain terminals of PM2 and NM2 are connected;
[0036] The source ends of PM1 and PM2 are connected, and the power supply voltage is connected in between;
[0037] The source ends of NM1 and NM2 are connected, and the ground is connected in the middle;
[0038] The LC series resonant circuit is connected to the drain terminals of PM2 and NM2 respectively;
[0039] The LC series resonant circuit is connected to the drain terminals of PM1 and NM1 respectively.
[0040] Due to internal resistance and other losses, the oscillation in the resonant cavity will decay. The differential CMOS active circuit can compensate for the loss in the resonant cavity, ensure the normal operation of the oscillator, and reduce the impact of the load effect on the oscillator.
[0041] The RC self-bias circuit includes resistors R1 and R2, capacitors C1, C2, C3 and C4, wherein:
[0042] The first end of the resistor R1 is connected to the drain terminals of PM1 and NM1, and the second end is connected to the gate terminals of PM2 and NM2;
[0043] The first end of the resistor R2 is connected to the gate terminals of PM1 and NM1, and the second end is connected to the drain terminals of PM1 and NM2;
[0044] The first end of capacitor C1 is connected to the drain terminals of PM1 and NM1, and the second end is connected to the gate terminals of PM2 and NM2;
[0045] A first end of the capacitor C2 is connected to the gate terminals of PM1 and NM1, and a second end is connected to the drain terminals of PM1 and NM2;
[0046] The capacitor C1 is connected in parallel with the resistor R1, and the capacitor C2 is connected in parallel with the resistor R2.
[0047] A first end of C3 is connected to the ground, and a second end is connected to the drain ends of PM1 and NM1. A first end of C4 is connected to the ground, and a second end is connected to the drain ends of PM2 and NM2.
[0048] Specifically, the maximum voltage swing of the inductor and capacitor in series can be Q times the drain voltage V0, where Q is the quality factor of the resonant circuit, which increases the oscillation amplitude on the one hand and improves the current efficiency on the other. The series resonance is driven by a voltage source with an ideally negligible small series impedance. The voltage amplitude across L and C can be expressed as:
[0049]
[0050] ω0 represents the resonant frequency, I0 represents V DD The sinusoidal current at ω0, r s represents the combined loss of L and C, and Q represents the quality factor of the series resonance. Usually the quality factor is around 20, so a large oscillation amplitude can be achieved even when the power supply voltage is very small, which is very beneficial for obtaining a small phase noise. At the same time, the cross-coupled switch pair not only adds more negative resistance to the LC resonant circuit, but also plays a role in shaping more rectangular waveforms at the output drain output node.
[0051] In combination with the voltage-controlled oscillator provided in the first aspect, the two ends of the LC series resonant circuit may also be directly connected to the drain end of the switch tube, such as Figure 2 As shown; directly connecting the drain end of the switch tube can increase the circuit operating speed and avoid the problem of poor frequency characteristics.
[0052] In combination with the voltage-controlled oscillator provided in the first aspect, the capacitors C3 and C4 may also be formed by parasitic capacitance at the drain end of the MOS tube; the capacitor and inductor are connected in series to form an LC resonant circuit, and the order may be reversed, and the capacitor includes at least one of a fixed capacitor, a variable capacitor and a digitally controlled capacitor array.
[0053] In summary, since the LC resonant circuit voltage of the traditional LC parallel resonant voltage-controlled oscillator is equal to the drain voltage of the active circuit, based on the reliability of the transistor, its drain voltage V0 is the maximum voltage swing of the resonant circuit. Since the inductor and capacitor are connected in series, the maximum voltage swing of the series resonant circuit can be Q times the drain voltage V0, where Q is the quality factor of the resonant circuit, thereby greatly reducing the phase noise. However, the series resonance consumes a large operating current, which increases the power consumption. The present invention can achieve low power consumption and low phase noise performance through the RC self-biased D-type active circuit structure.
[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A low phase noise series resonant class D oscillator, comprising a differential CMOS active circuit, an LC series resonant circuit and an RC self-bias circuit, characterized in that: The drain terminal or gate terminal of the differential CMOS active circuit is connected to an LC series resonant circuit, and the RC self-bias circuit connects the gate terminal on one side of the CMOS active circuit and the drain terminal on the opposite side.
2. The low phase noise series resonant class D oscillator according to claim 1, characterized in that: The LC series resonant circuit includes a variable capacitor Cv1 and a variable capacitor Cv2, an inductor L1 and an inductor L2, the variable capacitor Cv1 and the variable capacitor Cv2 are connected in series and connected to the ground in the middle; the inductor L1, the variable capacitor Cv1, the variable capacitor Cv2, and the inductor L2 are connected in series in sequence.
3. The low phase noise series resonant class D oscillator according to claim 2, characterized in that: The differential CMOS active circuit includes PMOS switch tubes PM1 and PM2, and NMOS switch tubes NM1 and NM2; Among them, the gate terminals of PM1 and NM1 are connected, and the gate terminals of PM2 and NM2 are connected; the drain terminals of PM1 and NM1 are connected, and the drain terminals of PM2 and NM2 are connected; the source terminals of PM1 and PM2 are connected, and a control voltage is connected in the middle; the source terminals of NM1 and NM2 are connected, and a ground is connected in the middle; The LC series resonant circuit is connected to the drain terminals of PM2 and NM2 respectively; The LC series resonant circuit is connected to the drain terminals of PM1 and NM1 respectively.
4. The low phase noise series resonant class D oscillator according to claim 3, characterized in that: The RC self-bias circuit includes resistors R1 and R2, capacitors C1, C2, C3 and C4, wherein: The first end of the resistor R1 is connected to the drain end of PM1 and NM1 respectively, and the second end of the resistor R1 is connected to the gate end of PM2 and NM2 respectively; The first end of the resistor R2 is connected to the gate end of PM1 and NM1 respectively, and the second end of the resistor R2 is connected to the drain end of PM1 and NM2 respectively; The first end of the capacitor C1 is connected to the drain end of PM1 and NM1 respectively, and the second end of the capacitor C1 is connected to the gate end of PM2 and NM2 respectively; The first end of the capacitor C2 is connected to the gate end of PM1 and NM1 respectively, and the second end of the capacitor C2 is connected to the drain end of PM1 and NM2 respectively; The capacitor C1 is connected in parallel with the resistor R1, and the capacitor C2 is connected in parallel with the resistor R2; A first end of the capacitor C3 is connected to the ground, and a second end of the capacitor C3 is connected to the drain ends of PM1 and NM1 respectively; A first terminal of the capacitor C4 is connected to the ground, and a second terminal of the capacitor C4 is connected to the drain terminals of PM2 and NM2 respectively.