High-gain low-noise amplifier circuit with adjustable power consumption
Through a two-stage common source structure and negative feedback circuit combined with a dual active bias circuit and a low-power switching circuit, the problem of low-noise amplifier chip being difficult to balance power consumption while improving small signal gain and reducing noise figure is solved, achieving high gain, low noise and stable amplifier performance, and having the flexibility of adjustable power consumption.
Patent Information
- Application Number
- CN202411757489.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-03
- Publication Date
- 2025-04-25
AI Technical Summary
While improving the gain of small signals and reducing the noise coefficient, existing low-noise amplifier chips are difficult to balance power consumption, resulting in the deterioration of large signal indicators when power consumption is too low, or there is a risk of self-excitation oscillation when power consumption is too high.
The two-stage common source structure and negative feedback circuit are adopted, combined with dual active bias circuits and low-power switching circuits, to achieve signal amplification and reduce forward self-excitation signals, ensuring the amplifier operates stably at high gain, and at the same time adjusting power consumption through low-power switching circuits.
It realizes high gain, low noise and stable amplifier performance, and has the flexibility of adjustable power consumption, suitable for applications in different communication modules.
Smart Images
Figure CN119891962A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of amplifier chips, and in particular to a high-gain low-noise amplifier circuit with adjustable power consumption. Background Art
[0002] As an important semiconductor device in the RF front-end system, the low noise amplifier chip has the function of small signal amplification. Its small signal gain, noise figure and power consumption will determine the quality of the subsequent link signal processing. With the wide application of low noise amplifiers in data links, radio stations, vehicle-mounted and other communication modules, higher requirements are put forward for the small signal gain, noise figure and power consumption of low noise amplifiers.
[0003] The main performance indicators of low-noise amplifier chips include small signal gain, noise figure and power consumption. In order to obtain a lower noise figure, the existing technology usually increases the small signal gain of the amplifier, but the higher the gain, the more unstable the amplifier will be, and there is a risk of self-oscillation. At the same time, the lower the power consumption of the low-noise amplifier chip, the lower the power consumption of the entire communication system, thereby increasing the battery life of the device, but too low power consumption will cause the large signal indicators of the low-noise amplifier chip to deteriorate seriously. Therefore, balancing the restrictive relationship between the noise figure, small signal gain and power consumption of the amplifier, and improving the versatility of the low-noise amplifier, has become an urgent problem to be solved. Summary of the invention
[0004] The present application provides a high-gain low-noise amplifier circuit with adjustable power consumption to solve the problem of the restrictive relationship between the noise figure, small signal gain and power consumption of a traditional low-noise amplifier. The circuit includes an input circuit, a first-stage amplifier circuit, a second-stage amplifier circuit and an output circuit connected in sequence; the first-stage amplifier circuit is matched with a first-stage feedback circuit and a first-stage active bias circuit; the power supply circuit provides a bias voltage for the first-stage amplifier circuit through the first-stage active bias circuit; the second-stage amplifier circuit is matched with a second-stage feedback circuit and a second-stage active bias circuit; the power supply circuit provides a bias voltage for the second-stage amplifier circuit through the second-stage active bias circuit;
[0005] The second-stage active bias circuit integrates a low-power switching circuit; the first-stage amplifier circuit includes a transistor M1; the source of the transistor M1 is grounded; the second-stage amplifier circuit includes a transistor M2; the source of the transistor M2 is grounded through a source feedback circuit.
[0006] In order to obtain a lower noise figure, the high-gain low-noise amplifier circuit with adjustable power consumption in the present application adopts a two-stage common source structure, which can amplify the signal twice to obtain a higher gain. At the same time, in order to prevent the amplifier from being unstable due to excessive gain, each stage of the amplifier circuit is configured with a negative feedback circuit to reduce the positive self-excitation signal in the circuit, thereby ensuring the high gain, low noise and stable excellent performance of the amplifier.
[0007] At the same time, the bias circuit of the present application adopts a dual active bias circuit to provide a stable bias voltage for the two-stage amplifier circuit transistors, ensuring that its static bias point does not change with the high or low external temperature. In addition, a low-power consumption function is integrated in the second-stage active bias circuit inside the low-noise amplifier chip, and a normal power consumption mode and a low power consumption mode can be selected. The implementation method is that if the PAD end is left floating and not connected, the amplifier is in a normal power consumption mode, and if the PAD end is grounded, the amplifier is in a low power consumption mode, realizing the switching of high and low power consumption, improving the flexibility of the application of the low-noise amplifier chip, and enabling the low-noise amplifier chip to be applied to communication modules with higher power consumption requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0009] Figure 1 This is a schematic diagram of the structure of a high-gain low-noise amplifier circuit with adjustable power consumption in the present application;
[0010] Figure 2 The simulation results of the static current of the low noise amplifier chip of this application in high and low power consumption modes;
[0011] Figure 3 The simulation results of the small signal gain variation with frequency in the low noise amplifier chip of the present application in high and low power consumption modes;
[0012] Figure 4 The simulation results of the stability of the low noise amplifier chip of the present application changing with frequency;
[0013] Figure 5 The simulation results of the noise coefficient of the low noise amplifier chip of the present application changing with frequency;
[0014] Figure 6 for Figure 1 Schematic diagram of the equivalent circuit structure of the second-stage active bias circuit in the circuit;
[0015] Figure 7This is the equivalent schematic diagram of the two-port network of the amplifier. DETAILED DESCRIPTION
[0016] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.
[0017] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can also be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0018] The embodiments of the present application will be described in further detail below in conjunction with the accompanying drawings. Figure 1 ;
[0019] Specifically, in an embodiment of the present application, a high-gain low-noise amplifier circuit with adjustable power consumption includes an input circuit, a first-stage amplifier circuit, a second-stage amplifier circuit, and an output circuit connected in sequence; the first-stage amplifier circuit is matched with a first-stage feedback circuit and a first-stage active bias circuit; the power supply circuit provides a bias voltage for the first-stage amplifier circuit through the first-stage active bias circuit; the second-stage amplifier circuit is matched with a second-stage feedback circuit and a second-stage active bias circuit; the power supply circuit provides a bias voltage for the second-stage amplifier circuit through the second-stage active bias circuit;
[0020] The second-stage active bias circuit integrates a low-power switching circuit; the first-stage amplifier circuit includes a transistor M1; the source of the transistor M1 is grounded; the second-stage amplifier circuit includes a transistor M2; the source of the transistor M2 is grounded through a source feedback circuit.
[0021] Further, the power supply circuit includes: a power supply Vdd, a choke inductor L1, a choke inductor L2, a filter capacitor C7, a filter capacitor C8, a filter capacitor C9 and a resistor R10;
[0022] The first-stage active bias circuit includes: a transistor M3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a resistor R9;
[0023] The first-stage feedback circuit includes: a feedback resistor R1 and a feedback capacitor C3;
[0024] Among them, the choke inductor L1, the resistor R10 and the filter capacitor C7 are connected in series between the power supply Vdd and the ground line in sequence; the choke inductor L1 and the filter capacitor C8 are connected in series between the power supply Vdd and the ground line in sequence; the choke inductor L1, the choke inductor L2 and the filter capacitor C9 are connected in series between the power supply Vdd and the ground line in sequence; the choke inductor L2 and the resistor R9 are connected in series between the power supply Vdd and the drain of the transistor M1 in sequence; the choke inductor L1 is connected between the power supply Vdd and the drain of the transistor M2;
[0025] The source of the transistor M3 is grounded through the resistor R5; the resistor R4 is connected between the gate and the drain of the transistor M3; the resistor R6 and the resistor R8 are connected in series between the drain of the transistor M3 and the drain of the transistor M1; the feedback resistor R1 and the feedback capacitor C3 are connected in series between the gate and the drain of the transistor M1; one end of the resistor R7 is connected to the middle point of the resistor R6 and the resistor R8, and the other end is connected to the middle point of the feedback resistor R1 and the feedback capacitor C3; one end of the resistor R9 is connected to the drain of the transistor M1, and the other end is connected to the power supply Vdd through the choke inductor L2 and the choke inductor L1.
[0026] Further, the second-stage active bias circuit includes: a transistor M4, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15 and a wire bonding PAD;
[0027] The second-stage feedback circuit includes: a feedback resistor R2 and a feedback capacitor C5;
[0028] The resistor R14 and the resistor R15 are connected in series between the source and the ground of the transistor M4; the resistor R12 and the resistor R13 are connected in series between the drain of the transistor M4 and the gate of the transistor M2; one end of the resistor R11 is connected to the gate of the transistor M4 and is also connected to the middle point of the resistor R12 and the resistor R13, and the other end of the resistor R11 is connected to the power supply Vdd through the choke inductor L1; the binding wire PAD is connected to the middle point of the resistor R14 and the resistor R15;
[0029] In the specific operation of the amplifier circuit, when the power supply Vdd supplies 5V, the low-noise amplifier circuit works normally, and the RF signal enters the DC-blocking capacitor C1 from the signal input terminal RFin, and is output by the DC-blocking capacitor C2 after passing through the two-stage amplification circuit configured by the bias circuit; when the pad of the wire-binding PAD in the second-stage bias circuit is grounded through the wire-binding, the low-noise amplifier enters the low-power consumption mode, while ensuring good small-signal performance.
[0030] The specific implementation principle is as follows:
[0031] As attached Figure 6 As shown, when the gate and drain of the transistor M4 in the second-stage bias circuit are short-circuited by the resistor R13, it is equivalent to the diode D1. At this time, the source of the transistor M4 is equivalent to the N-pole of the diode D1. The N-pole of the transistor D1 is grounded through the resistor R14 and the resistor R15, and the binding wire PAD is connected to the middle point of the resistor R14 and the resistor R15.
[0032] In this process, resistor R11 and resistors R14 and R15 form a voltage divider circuit to provide a gate bias voltage Vg2 for transistor M2. When the pad of the wire-binding PAD in the second-stage bias circuit is suspended and not connected, the resistor R14 and the resistor R15 are connected in series, and the gate bias voltage Vg2 controlled increases, and the gate static bias point of the transistor M2 increases, so its static current increases, and the low-noise amplifier is in a high-power operation mode.
[0033] When the pad of the wire-binding PAD in the second-stage bias circuit is grounded through the wire-binding, the resistor R15 will be short-circuited, and only the resistor R14 will be left to divide the voltage in the second active bias circuit. Therefore, the controlled gate bias voltage Vg2 becomes lower, and the gate static bias point of the transistor M2 becomes lower, so its static current becomes smaller, so that the low-noise amplifier is in a low-power operation mode.
[0034] At the same time, if attached Figure 1 As shown, since the resistance of resistor R15 is small, the gate static bias point of transistor M2 is adjusted by adjusting the voltage divider value connected in series with resistor R14. The change in the resistance of resistor R15 will not have a significant impact on the RF small signal S parameter of the low noise amplifier. Therefore, good small signal S parameter performance can be guaranteed.
[0035] The feedback resistor R2 and the feedback capacitor C5 are connected in series between the gate and the drain of the transistor M2 .
[0036] Furthermore, the input circuit includes: a radio frequency signal input terminal RFin and a DC blocking capacitor C1; the original radio frequency signal enters the DC blocking capacitor C1 from the radio frequency signal input terminal RFin, and is then input into the gate of the transistor M1.
[0037] Furthermore, the output circuit includes: a DC blocking capacitor C2 and a radio frequency signal output terminal RFout; the amplified radio frequency signal is input into the DC blocking capacitor C2 from the drain of the transistor M2, and then output from the radio frequency signal output terminal RFout.
[0038] Furthermore, an inter-stage matching capacitor C4 is connected between the drain of the transistor M1 and the gate of the transistor M2.
[0039] Furthermore, it also includes a source feedback circuit; the source feedback circuit includes: a source feedback resistor R3 and a source feedback capacitor C6; the source feedback resistor R3 and the source feedback capacitor C6 are connected in parallel between the source of the transistor M2 and the ground line.
[0040] Furthermore, the wire-binding PAD can be switched between being suspended and unconnected or being grounded. When it is suspended and unconnected, the amplifier is in normal power consumption mode; when it is grounded, the amplifier is in low power consumption mode, thereby controlling the amplifier to switch between normal power consumption and low power consumption modes.
[0041] For details, please refer to the attached Figure 1 It can be seen from the circuit that when the pad of the wire-binding PAD in the second-stage bias circuit is suspended and not connected, the resistor R14 and the resistor R15 form a series voltage divider, and the controlled gate bias voltage Vg2 is relatively high, so the gate static bias point of the transistor M2 is high, so its static current is large, and the low-noise amplifier is in a high power consumption working mode;
[0042] When the pad of the wire-binding PAD in the second-stage bias circuit is grounded through the wire-binding, the resistor R15 is short-circuited, and only the resistor R14 divides the voltage, so the controlled gate bias voltage Vg2 becomes lower, and the gate static bias point of the transistor M2 becomes low, so its static current becomes smaller, so that the low-noise amplifier is in a low-power working mode. Therefore, the switching of the amplifier high and low power modes can be controlled by configuring the wire-binding PAD to be suspended or grounded.
[0043] Furthermore, the transistor M1, the transistor M2, the transistor M3 and the transistor M4 are all GaAspHEMT transistors.
[0044] Specifically, the working principle of the high-gain low-noise amplifier chip with low power consumption function of the present application is as follows:
[0045] As attached Figure 1As shown, transistor M1 and transistor M2 form a two-stage common source amplifier circuit structure, which can amplify the signal twice to obtain a higher gain. At the same time, in order to prevent the amplifier from being unstable due to excessive gain, a negative feedback circuit composed of feedback resistors R1, R2, R3 and feedback capacitors C3, C5, C6 is used. By changing the value of the feedback resistance and the value of the capacitance, the strength of the negative feedback signal is controlled.
[0046] The principle is that when the feedback resistance and capacitance values become larger, the low-frequency feedback signal of the amplifier is weak, and the ability to suppress the low-frequency gain of the amplifier is weak, then the low-frequency gain of the amplifier will be too high, causing the amplifier to work in an unstable state and there is a risk of self-oscillation; when the feedback resistance and capacitance values are reduced, the signal fed back to the input of the amplifier will be strong, which can offset the excessively high low-frequency gain of the amplifier, thereby ensuring the stability of the amplifier's working state, preventing the amplifier from self-oscillating, and allowing the amplifier to guarantee stable performance at high gain.
[0047] At the same time, a dual active bias circuit consisting of a first-stage bias circuit and a second-stage bias circuit is used to provide a stable bias voltage for the transistors of the two-stage amplifier circuit, ensuring that the static bias point does not change with the external temperature.
[0048] In particular, a low power consumption function is integrated in the second-stage active bias circuit. The implementation method is that when the PAD end is left floating and not connected, the amplifier is in a normal high power consumption mode, and when the PAD end is grounded, the amplifier is in a low power consumption mode. This realizes the switching between high and low power consumption, making the application of the low noise amplifier chip more flexible.
[0049] As attached Figure 2 As shown, when the low noise amplifier chip is in high power mode, the quiescent current is 95mA and the power consumption is 0.475 watts; when the low noise amplifier chip is in low power mode, the quiescent current is 76mA and the power consumption is 0.38 watts, and the power consumption of the amplifier is significantly reduced;
[0050] As attached Figure 3 As shown, the operating frequency band of the low noise amplifier chip is up to 4 GHz. When the low noise amplifier chip is in high power consumption mode, it can provide a small signal gain of 30 dB; when the low noise amplifier chip is in low power consumption mode, it can provide a small signal gain greater than 29 dB.
[0051] As attached Figure 4 As shown, the stability K value of the low noise amplifier chip is greater than 1, the chip is absolutely stable and there is no risk of self-excitation;
[0052] Specifically, the following statement is made regarding the relationship between the K value, absolute stability and self-excitation risk.
[0053] In the design of low-noise amplifiers, stability (expressed by the range of K values) is a key measure to determine whether the amplifier will self-oscillate within the operating frequency range. The circuit's ability to suppress self-oscillation determines whether the amplifier can ultimately be used normally, so stability is a key factor to consider in the engineering design of amplifiers.
[0054] As attached Figure 7 As shown, the amplifier can be equivalent to a two-port network. The key reason for the self-oscillation phenomenon in the amplifier circuit is the existence of negative impedance at the input and output ends of the two-port network.
[0055] For unidirectional transmission devices, if the input return loss |S11|>1 or the output return loss
[0056] |S22|>1, making the input reflection coefficient of the circuit |ΓIN|>1 or the output reflection coefficient |ΓOUT|>1, the circuit will experience self-oscillation. Because ΓIN and ΓOUT are related to the source and load matching networks, the stability of the amplifier depends on the source reflection coefficient ΓS and the load reflection coefficient ΓL provided by the network matching. Therefore, the conditions for the input and output terminals of the transistor to present negative resistance are |S11|>1 and |S22|>1.
[0057] Generally, the results of circuit stability determination can be divided into two types: absolute stability and conditional stability. If a network is absolutely stable, then the reflection coefficients of all signal source impedances and load impedances have the relationship of |ΓIN|<1 and |ΓOUT|<1 or |ΓS|<1 and |ΓL|<1. On the contrary, if a network is conditionally stable, then the reflection coefficients of its signal source impedance and load impedance have the relationship of |ΓIN|<1 and |ΓOUT|<1 only within certain specific ranges.
[0058] As attached Figure 7 In the two-port network shown, if the real parts of the input impedance and output impedance of the network are greater than zero for all signal source and load impedances, then the network is absolutely stable, otherwise the network is conditionally stable. On the contrary, if the real parts of the input impedance and output impedance of the network are less than zero, then the network is potentially unstable.
[0059] According to the relationship between the reflection coefficients within a certain frequency range, the conditionally stable expression is as follows:
[0060] |Γ S |<1 (1)
[0061] |Γ L |<1 (2)
[0062]
[0063] All parameters are normalized parameters to the characteristic impedance Z0. Equations (1) and (2) indicate that the source and load are passive, and equations (3) and (4) indicate that the input and output impedances are also passive, that is, their real parts are non-negative.
[0064] By solving equations (1) to (4), we can obtain the necessary and sufficient conditions for a two-port network to reach an absolutely stable state, as shown in the following equation:
[0065] K>1;
[0066] 1-|S 11 | 2 >|S 12 S 21 |;
[0067] 1-|S 22 | 2 >|S 12 S 21 |;
[0068] in,
[0069]
[0070] Δ=S 11 S 22 -S 12 S 21 ;
[0071] Therefore, the necessary and sufficient conditions for the amplifier to be absolutely stable are as follows:
[0072] K>1 and |Δ|<1.
[0073] In order to prevent the amplifier from being unstable due to excessive gain, the circuit of this application adopts a negative feedback circuit to reduce the positive self-excitation signal in the circuit, so that the amplifier can ensure stable performance at high gain. Figure 4 As shown, the simulation results of the low noise amplifier circuit of the present application show that its K value curve is above 1 as a whole, and there is no risk of self-excitation.
[0074] As attached Figure 5 As shown, the noise figure of a high-gain low-noise amplifier circuit with adjustable power consumption of the present application is less than 1.1dB@100MHz~4GHz, with a typical value of 0.7dB, and has excellent noise performance, which can effectively improve the sensitivity of the RF receiver.
[0075] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.
[0076] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units can be a logical function division, and there can be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of units or modules can be electrical or other forms.
[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed over multiple units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.
[0078] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0079] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.
[0080] The above are only preferred embodiments of the present application and do not have any limiting effect on the present application. Any technical personnel in the relevant technical field, without departing from the scope of the technical solution of the present application, may make any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present application, which shall be deemed as the content of the technical solution of the present application and still fall within the protection scope of the present application.
Claims
1. A high-gain low-noise amplifier circuit with adjustable power consumption, comprising an input circuit, a first-stage amplifier circuit, a second-stage amplifier circuit and an output circuit connected in sequence; characterized in that: The first-stage amplifier circuit is matched with a first-stage feedback circuit and a first-stage active bias circuit; The power supply circuit provides a bias voltage for the first-stage amplifier circuit through the first-stage active bias circuit; the second-stage amplifier circuit is matched with a second-stage feedback circuit and a second-stage active bias circuit; the power supply circuit provides a bias voltage for the second-stage amplifier circuit through the second-stage active bias circuit; The second-stage active bias circuit integrates a low-power switching circuit; the first-stage amplifier circuit includes a transistor M1; the source of the transistor M1 is grounded; the second-stage amplifier circuit includes a transistor M2; the source of the transistor M2 is grounded through a source feedback circuit.
2. According to claim 1, a high-gain low-noise amplifier circuit with adjustable power consumption, characterized in that: The power supply circuit includes: a power supply Vdd, a choke inductor L1, a choke inductor L2, a filter capacitor C7, a filter capacitor C8, a filter capacitor C9 and a resistor R10; The first-stage active bias circuit includes: a transistor M3, a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, and a resistor R9; The first-stage feedback circuit includes: a feedback resistor R1 and a feedback capacitor C3; Wherein, the choke inductor L1, the resistor R10 and the filter capacitor C7 are sequentially connected in series between the power supply Vdd and the ground line; the choke inductor L1 and the filter capacitor C8 are sequentially connected in series between the power supply Vdd and the ground line; the choke inductor L1, the choke inductor L2 and the filter capacitor C9 are sequentially connected in series between the power supply Vdd and the ground line; the choke inductor L1, the choke inductor L2 and the filter capacitor C9 are sequentially connected in series between the power supply Vdd and the ground line; the choke inductor L1, the choke inductor L2 and the resistor R9 are sequentially connected in series between the power supply Vdd and the drain of the transistor M1; the choke inductor L1 is connected between the power supply Vdd and the drain of the transistor M2; The source of the transistor M3 is grounded through the resistor R5; the resistor R4 is connected between the gate and the drain of the transistor M3; the resistor R6 and the resistor R8 are connected in series between the drain of the transistor M3 and the drain of the transistor M1; the feedback resistor R1 and the feedback capacitor C3 are connected in series between the gate and the drain of the transistor M1; one end of the resistor R7 is connected to the middle point of the resistor R6 and the resistor R8, and the other end is connected to the middle point of the feedback resistor R1 and the feedback capacitor C3; one end of the resistor R9 is connected to the drain of the transistor M1, and the other end is connected to the power supply Vdd through the choke inductor L2 and the choke inductor L1.
3. A high-gain low-noise amplifier circuit with adjustable power consumption according to claim 2, characterized in that: The second-stage active bias circuit includes: a transistor M4, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15 and a wire bonding PAD; The second-stage feedback circuit includes: a feedback resistor R2 and a feedback capacitor C5; The resistor R14 and the resistor R15 are connected in series between the source and the ground of the transistor M4; the resistor R12 and the resistor R13 are connected in series between the drain of the transistor M4 and the gate of the transistor M2; one end of the resistor R11 is connected to the gate of the transistor M4 and is also connected to the middle point of the resistor R12 and the resistor R13, and the other end of the resistor R11 is connected to the power supply Vdd through the choke inductor L1; the binding wire PAD is connected to the middle point of the resistor R14 and the resistor R15; The feedback resistor R2 and the feedback capacitor C5 are connected in series between the gate and the drain of the transistor M2 .
4. The high-gain low-noise amplifier circuit with adjustable power consumption according to claim 1, characterized in that: The input circuit includes: a radio frequency signal input terminal RFin and a DC blocking capacitor C1; the original radio frequency signal enters the DC blocking capacitor C1 from the radio frequency signal input terminal RFin, and then is input into the gate of the transistor M1.
5. The high-gain low-noise amplifier circuit with adjustable power consumption according to claim 1, characterized in that: The output circuit includes: a DC blocking capacitor C2 and a radio frequency signal output terminal RFout; the amplified radio frequency signal is input into the DC blocking capacitor C2 from the drain of the transistor M2, and then output from the radio frequency signal output terminal RFout.
6. The high-gain low-noise amplifier circuit with adjustable power consumption according to claim 1, characterized in that: An inter-stage matching capacitor C4 is connected between the drain of the transistor M1 and the gate of the transistor M2.
7. The high-gain low-noise amplifier circuit with adjustable power consumption according to claim 1, characterized in that: It also includes a source feedback circuit; the source feedback circuit includes: a source feedback resistor R3 and a source feedback capacitor C6; the source feedback resistor R3 and the source feedback capacitor C6 are connected in parallel between the source of the transistor M2 and the ground line.
8. The high-gain low-noise amplifier circuit with adjustable power consumption according to claim 3, characterized in that: The wire-binding PAD can be switched between being suspended and unconnected or being grounded. When it is suspended and unconnected, the amplifier is in a normal power consumption mode. When the wire-binding PAD is grounded, the amplifier is in a low power consumption mode, thereby controlling the amplifier to switch between normal power consumption and low power consumption modes.
9. A high-gain low-noise amplifier circuit with adjustable power consumption according to any one of claims 1 to 8, characterized in that: The transistor M1 , the transistor M2 , the transistor M3 and the transistor M4 are all GaAs pHEMT transistors.