Error amplifier

Abstract

The invention discloses an error amplifier, relates to the field of integrated circuit design, and aims to solve the problem of poor DC precision of output voltage of a DC power converter in the prior art. The error amplifier comprises a first steering stage circuit, an amplification stage circuit, a second steering stage circuit and an output stage circuit; connecting the first steering stage circuit with the amplification stage circuit, connecting the amplification stage circuit with the second steering stage circuit, and connecting the second steering stage circuit with the output stage circuit; the first steering stage circuit, the second steering stage circuit and the output stage circuit are used for adjusting the common-mode level of the common-mode voltage output by the output stage circuit, so that the common-mode voltage is not influenced by the change of the power supply voltage, the drift of the offset voltage of an error amplifier system is effectively reduced, and the direct-current precision of the output voltage of the direct-current power converter is improved.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit design, in particular to an error amplifier. Background Art

[0002] At present, the common COT architecture BUCK type DCDC converter (DC-to-DC Converter) system structure is as follows: Figure 1 As shown, its working principle waveform is as follows Figure 2 As shown; the steady-state working principle of the DCDC converter is: when the feedback voltage signal VFB drops below the error amplifier output signal EA_OUT, the comparator output flips, triggering the M1 tube to conduct a time pulse, and the feedback signal VFB rises linearly. After the conduction timing is over, M1 is turned off, and the M2 tube is turned on at the same time, and the feedback signal VFB begins to decrease linearly. The above process works in each cycle. The main function of the error amplifier in the loop is to calibrate the output signal VOUT so that the output signal DC voltage can be determined by the voltage division ratio of the reference signal and the feedback resistor. However, the error amplifier itself has a system offset voltage, and the input power supply of the DCDC converter can generally have a range of several volts. The offset voltage will drift greatly due to the change in the power supply voltage, which has an adverse effect on the DC accuracy of the converter output voltage, resulting in poor DC accuracy of the DC power converter output voltage.

[0003] In view of this, it is urgent to design a more advanced error amplifier to solve the problem in the prior art that the DC accuracy of the output voltage of the DC power converter is poor due to the large drift of the offset voltage of the error amplifier. Summary of the invention

[0004] The present invention aims to provide an error amplifier which adopts a common-mode voltage matching technology to reduce the sensitivity of power supply voltage changes to the common-mode level of the error amplifier output, thereby reducing the drift of the system offset voltage of the error amplifier and improving the DC accuracy of the output voltage of a BUCK type DC power converter; and solves the problem of poor DC accuracy of the output voltage of a DC power converter in the prior art.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides an error amplifier, which may include:

[0007] A first steering stage circuit, an amplifier stage circuit, a second steering stage circuit and an output stage circuit;

[0008] The first steering stage circuit is connected to the amplifier stage circuit, the amplifier stage circuit is connected to the second steering stage circuit, and the second steering stage circuit is connected to the output stage circuit;

[0009] The first steering stage circuit, the second steering stage circuit and the output stage circuit are used to adjust the common mode level of the common mode voltage output by the output stage circuit to reduce the drift of the offset voltage of the error amplifier system.

[0010] Preferably, the amplifier stage circuit may include: a first PMOS tube, a second PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor and a second resistor;

[0011] The source of the tenth PMOS tube is connected to the voltage end, the gate of the tenth PMOS tube is connected to the first terminal, and the drain of the tenth PMOS tube is connected to the source of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the second terminal; one end of the first resistor is connected to the drain of the ninth PMOS tube, and the other end of the first resistor is connected to the source of the first PMOS tube; one end of the second resistor is connected to the drain of the ninth PMOS tube, and the other end of the second resistor is connected to the source of the second PMOS tube; the gate of the first PMOS tube is connected to the feedback voltage source end, and the drain of the first PMOS tube is connected to the gate of the first NMOS tube; the gate of the second PMOS tube is connected to the reference voltage source end, and the drain of the second PMOS tube is connected to the gate of the second NMOS tube; the gate of the third NMOS tube is connected to the third terminal, and the drain of the third NMOS tube is connected to the The source of the first PMOS tube is connected, and the source of the third NMOS tube is connected to the drain of the first NMOS tube; the gate of the fourth NMOS tube is connected to the third terminal, the drain of the fourth NMOS tube is connected to the source of the second PMOS tube, and the source of the fourth NMOS tube is connected to the drain of the second NMOS tube; the gate of the first NMOS tube is connected to the first steering stage circuit, and the source of the first NMOS tube is grounded; the gate of the second NMOS tube is connected to the second steering stage circuit, and the source of the second NMOS tube is grounded; the drain of the fifth NMOS tube is connected to the gate of the first NMOS tube, the gate of the fifth NMOS tube is connected to the fourth terminal, and the source of the fifth NMOS tube is grounded; the drain of the sixth NMOS tube is connected to the gate of the second NMOS tube, the gate of the sixth NMOS tube is connected to the fourth terminal, and the source of the sixth NMOS tube is grounded.

[0012] Preferably, the first steering stage circuit may include: a third PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, a seventh NMOS transistor, a ninth NMOS transistor, an eleventh NMOS transistor and a third resistor;

[0013] The source of the fifth PMOS tube is connected to the power supply terminal, the gate of the fifth PMOS tube is connected to the gate of the third PMOS tube, and the drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube; the source of the third PMOS tube is connected to the power supply terminal, the drain of the third PMOS tube is connected to the drain of the seventh NMOS tube, and the drain of the third PMOS tube is connected to the gate of the third PMOS tube; the gate of the seventh PMOS tube is connected to the second terminal, and the drain of the seventh PMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected to the third terminal, the source of the eleventh NMOS tube is connected to the drain of the ninth NMOS tube, and the drain of the eleventh NMOS tube is connected to the gate of the ninth NMOS tube; the gate of the ninth NMOS tube is connected to the second steering stage circuit; one end of the third resistor is connected to the source of the ninth NMOS tube, and the other end of the third resistor is grounded; the gate of the seventh NMOS tube is connected to the gate of the first NMOS tube, and the source of the seventh NMOS tube is grounded.

[0014] Preferably, the second steering stage circuit may include: a fourth PMOS transistor, a sixth PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, a twelfth NMOS transistor and a fourth resistor;

[0015] The source of the sixth PMOS tube is connected to the power supply terminal, the gate of the sixth PMOS tube is connected to the gate of the fourth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube; the source of the fourth PMOS tube is connected to the power supply terminal, the drain of the fourth PMOS tube is connected to the drain of the eighth NMOS tube, and the drain of the fourth PMOS tube is connected to the gate of the fourth PMOS tube; the gate of the eighth PMOS tube is connected to the second terminal, and the drain of the eighth PMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the twelfth NMOS tube is connected to the third terminal, the source of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube, and the drain of the twelfth NMOS tube is connected to the output stage circuit; the gate of the tenth NMOS tube is connected to the gate of the ninth NMOS tube; one end of the fourth resistor is connected to the source of the tenth NMOS tube, and the other end of the fourth resistor is grounded; the gate of the eighth NMOS tube is connected to the gate of the second NMOS tube, and the source of the eighth NMOS tube is grounded.

[0016] Preferably, the output stage circuit may include: a thirteenth NMOS tube, a fourteenth NMOS tube and a charging capacitor;

[0017] One end of the charging capacitor is connected to the gate of the fourteenth NMOS tube, and the other end of the charging capacitor is grounded; the drain of the fourteenth NMOS tube is connected to the power supply terminal, the gate of the fourteenth NMOS tube is connected to the drain of the twelfth NMOS tube, the source of the fourteenth NMOS tube is connected to the drain of the thirteenth NMOS tube, and the source of the fourteenth NMOS tube is connected to the output terminal; the gate of the thirteenth NMOS tube is connected to the fourth terminal, and the source of the thirteenth NMOS tube is grounded.

[0018] Preferably, when the voltage at the feedback voltage source terminal is equal to the voltage at the reference voltage source terminal, the formula can be used:

[0019]

[0020] Calculate the common-mode voltage at the error amplifier output; where V OUT,CM The common-mode voltage at the output of the error amplifier, V GS,MN9,10 represents the voltage difference between the gate and source of MN9 or MN10, I D1 represents the current flowing through the third resistor, I D2 represents the current flowing through MN13, R d Indicates the resistance value of the third resistor or the fourth resistor, V GS,MN14 represents the voltage difference between the gate and source of MN14, V th,MN9,10 Indicates the threshold voltage of MN9 or MN10, V th,MN14 represents the threshold voltage of MN14, kn represents the calculation constant in the circuit, (W / L) MN9,10 Indicates the width-to-length ratio of MN9 or MN10 (W / L) MN14 Indicates the width-to-length ratio of MN14.

[0021] Preferably, when the body effect of the transistor is neglected, the formula can be used:

[0022]

[0023] Calculate the common-mode voltage at the error amplifier output; where V OUT,CM The common-mode voltage at the output of the error amplifier, V GS,MN9,10 represents the voltage difference between the gate and source of MN9 or MN10, I D1 represents the current flowing through the third resistor, I D2 represents the current flowing through MN13, R d Indicates the resistance value of the third resistor or the fourth resistor, V GS,MN14 represents the voltage difference between the gate and source of MN14, kn represents the calculation constant in the circuit, (W / L) MN9,10 Indicates the width-to-length ratio of MN9 or MN10 (W / L)MN14 Indicates the width-to-length ratio of MN14.

[0024] Preferably, the first resistor and the second resistor are of the same model.

[0025] Preferably, the third resistor and the fourth resistor are of the same model.

[0026] Preferably, the model of the ninth NMOS tube is the same as the model of the tenth NMOS tube.

[0027] Compared with the prior art, the error amplifier provided by the present invention is provided with a first steering stage circuit, an amplifying stage circuit, a second steering stage circuit and an output stage circuit; the first steering stage circuit is connected to the amplifying stage circuit, the amplifying stage circuit is connected to the second steering stage circuit, and finally the second steering stage circuit is connected to the output stage circuit; the first steering stage circuit, the second steering stage circuit and the output stage circuit are used to adjust the common mode level of the common mode voltage output by the output stage circuit to reduce the drift of the error amplifier system offset voltage. Based on this, the MOS tubes and the resistors connected in series with the MOS tubes are used to be provided in the first steering stage circuit, the second steering stage circuit and the output stage circuit, and the common mode voltage matching technology is adopted, so that the common mode level of the common mode voltage output by the error amplifier is almost equal to the reference voltage source, thereby avoiding the sensitivity of the common mode level of the error amplifier output to the change of the power supply voltage, reducing the drift of the system offset voltage of the error amplifier, and improving the DC accuracy of the output voltage of the BUCK type DC power converter; solving the problem of poor DC accuracy of the output voltage of the DC power converter in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0029] Figure 1 It is a schematic diagram of the structure of a COT architecture BUCK circuit in the prior art;

[0030] Figure 2 It is a schematic diagram of steady-state working waveform of a COT architecture BUCK circuit system in the prior art;

[0031] Figure 3 It is a schematic diagram of the circuit structure of a narrow bandwidth error amplifier in the prior art;

[0032] Figure 4 A schematic diagram of the main structure of an error amplifier provided by the present invention;

[0033] Figure 5A schematic diagram comparing the change of the common mode voltage output by the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with the power supply voltage;

[0034] Figure 6 A schematic diagram comparing the variation of the offset voltage inputted by the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with the power supply voltage;

[0035] Figure 7 The figure is a schematic diagram comparing the response curves of the phase margin and loop gain of the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with respect to the frequency change under the power supply voltage of 3.3V.

[0036] Figure markings: 400-error amplifier, 410-first steering stage circuit, 420-amplifier stage circuit, 430-second steering stage circuit, 440-output stage circuit, VB1-first terminal, VB2-second terminal, VB3-third terminal, VB4-fourth terminal, VN-feedback voltage source terminal, VP-reference voltage source terminal, VOUT-output terminal, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor. DETAILED DESCRIPTION

[0037] In order to facilitate the clear description of the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and do not limit their order of precedence. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit them to be different.

[0038] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0039] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects in the previous time are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0040] First, some English abbreviations involved in the present invention are explained as follows:

[0041]

[0042] See also Figure 1 to Figure 2 , Figure 1 It is a schematic diagram of the structure of a COT architecture BUCK circuit in the prior art; Figure 2 Schematic diagram of steady-state operating waveform of a COT architecture BUCK circuit system in the prior art.

[0043] Figure 1 The circuit structure shown is a common COT architecture BUCK type DCDC converter system structure. Figure 2 The waveform diagram is a steady-state working waveform of the COT architecture BUCK circuit system. Its steady-state working principle is: when the feedback voltage signal VFB drops below the error amplifier output signal EA_OUT, the comparator output flips, triggering the M1 tube to conduct a time pulse, and the feedback signal VFB rises linearly; after the conduction timing ends, M1 is turned off, and the M2 tube is turned on at the same time, and the feedback signal VFB begins to decline linearly, and the above process works in each cycle. The main function of the error amplifier in the loop is to calibrate the output signal VOUT so that the output signal DC voltage can be determined by the voltage division ratio of the reference signal and the feedback resistor. However, the error amplifier itself has a system offset voltage, and the input power supply of the DCDC converter has a variation range of several volts. The offset voltage will be affected by the change of the power supply voltage and produce a large drift, which will have an adverse effect on the DC accuracy of the converter output voltage, making the DC accuracy of the DC power converter output voltage poor.

[0044] To solve the problem of poor DC accuracy of the output voltage of the DC power converter, refer to Figure 3 , Figure 3 Schematic diagram of a narrow bandwidth error amplifier circuit structure in the prior art. It should be noted that: Figure 3The circuit structure corresponds to Figure 1 The internal structure of the EA error amplifier.

[0045] Figure 3 The circuit structure shown is a narrow bandwidth error amplifier structure in the prior art, in which the first stage adopts a negative feedback enhanced transconductance structure; the formula can be used:

[0046]

[0047] Calculate the first-stage gain of the error amplifier, A1; where g mn1,2 represents the transconductance of MN1 or MN2, R s Represents the resistance in series in the circuit. Compared with the traditional method of reducing equivalent transconductance by source series resistance, it is necessary to ensure that g mn1,2 ·R s >>1. If formula (1) is to be satisfied, a larger resistor R is required. s ; However, a larger resistor will sacrifice the input common-mode range of the error amplifier and introduce greater noise. Therefore, after analysis, we designed a negative feedback equivalent enhanced transconductance structure, which can effectively reduce R s resistance value, avoiding R s Too much adverse effects.

[0048] Based on this, the formula can be used:

[0049] A2≈g mn7,8 ·(g mn10 ·r on10 ·r on8 / / g mp6 ·r op6 ·r op4 ) (2)

[0050] Calculate the error amplifier second stage gain A2; where g mp7,8 Indicates the transconductance of MN7 or MN8, g mp10 represents the transconductance of MN10, g mp6 represents the transconductance of MP6, r on10 represents the output resistance of MN10, r on8 represents the output resistance of MN8, r op6 represents the output resistance of MP6, r op4 Indicates the output resistance of MP4.

[0051] Furthermore, the main pole is located at the output node, and the formula can be used:

[0052]

[0053] Calculate the frequency f p1; Where C represents the output capacitance.

[0054] Further, the formula can be used:

[0055]

[0056] Calculate the unity gain bandwidth GBW of the error amplifier. Due to the stability requirements of the COT architecture system loop, it is necessary to ensure that the GBW of the error amplifier is not too large. Based on formula (4), if the GBW needs to be reduced, it can be mainly achieved by using a larger output capacitor and / or a larger source degeneration resistor R s to achieve.

[0057] For further information, please refer to Figure 1 and Figure 3 When the system is working stably, the feedback signal VFB is compared with the output EA_OUT of the error amplifier. Since the error amplifier clamps the DC value of the feedback signal VFB near the reference signal VREF, and the ripple of the feedback signal is smaller than the DC voltage and can be approximately ignored, the steady-state value of the output signal of the error amplifier should be near the reference voltage signal VREF; the formula can be used:

[0058] V OUT,CM ≈VDD-V SG,MP3 (5)

[0059] The common-mode potential of the error amplifier output is V OUT,CM ; Where VDD represents the power supply voltage, V SG,MP3 Represents the voltage difference between the source and gate of the MP3 tube.

[0060] Further, the formula can be used:

[0061]

[0062] Calculate the system offset voltage V os,sys ; Wherein, VDD represents the power supply voltage, VREF represents the reference voltage, A1 and A2 represent the gains of the first and second stages of the error amplifier respectively.

[0063] Because the system offset voltage V os,sys Will deteriorate the converter output voltage accuracy, so the formula can be used:

[0064]

[0065] Calculate the output voltage DC error to express V out,DCDC,err ; Among them, V os,sys represents the system offset voltage, R fb1 , R fb2Represents the feedback voltage divider resistor of the output terminal VOUT.

[0066] Based on this, we can get Figure 3 In the narrowband error amplifier structure shown in FIG. 1 , the system offset voltage is directly related to the DC common-mode voltage output by the amplifier. It can be clearly seen from Equation 6 that its magnitude is linearly related to the power supply voltage. For a DC converter with a wide input voltage, a larger input voltage will cause the system offset voltage to increase, thus deteriorating the DC accuracy of the output voltage. Figure 3 This improved circuit structure cannot solve the problem of poor DC accuracy of the output voltage of the DC power converter.

[0067] In addition, a common method to reduce the system offset voltage is to increase the DC gain of the error amplifier. From formula (1) to formula (4), it can be seen that the main method to increase the DC gain is to reduce the source negative feedback resistor R s However, this method will increase the GBW of the error amplifier, which is not conducive to the stability of the converter loop. Therefore, a larger output capacitor is usually used, which increases the layout area.

[0068] In view of this, the present invention provides an error amplifier, and proposes an error amplifier composed of a first steering stage circuit, an amplification stage circuit, a second steering stage circuit and an output stage circuit. The first steering stage circuit, the second steering stage circuit and the output stage circuit are used to adjust the common-mode level of the common-mode voltage output by the output stage circuit, so that the common-mode voltage is not affected by changes in the power supply voltage, effectively reducing the drift of the offset voltage of the error amplifier system and improving the DC accuracy of the output voltage of the DC power converter.

[0069] It should be noted that common-mode voltage matching is a key factor in amplifier design, especially for differential amplifiers and operational amplifiers. Common-mode voltage refers to the average voltage at two input terminals in a differential input signal. When designing and applying an amplifier, it is very important to ensure that the common-mode voltage is within the operating range of the amplifier; the common-mode voltage affects the performance of the amplifier, including linearity, distortion, and noise level. If the common-mode voltage exceeds the allowable range of the amplifier, it may cause output nonlinearity, distortion, and even damage the amplifier. The circuit structure corresponding to an error amplifier provided by the present invention can effectively match and control the common-mode voltage in the amplifier, thereby improving the performance and reliability of the amplifier.

[0070] Next, the technical solution of the present invention is described in detail with reference to the accompanying drawings:

[0071] See also Figure 4 , Figure 4 A schematic diagram of the main structure of an error amplifier provided by the present invention. Figure 4 The circuit structure shown corresponds to Figure 1The internal circuit structure of the EA error amplifier.

[0072] exist Figure 4 In the embodiment, the error amplifier 400 may include a first steering stage circuit 410 , an amplifying stage circuit 420 , a second steering stage circuit 430 , and an output stage circuit 440 .

[0073] Specifically, the first steering stage circuit 410 is connected to the amplifier stage circuit 420, the amplifier stage circuit 420 is connected to the second steering stage circuit 430, and the second steering stage circuit 430 is connected to the output stage circuit 440; wherein, the first steering stage circuit 410, the second steering stage circuit 430 and the output stage circuit 440 are used to adjust the common-mode level of the common-mode voltage output by the output stage circuit; thereby achieving the use of the first steering stage circuit 410, the second steering stage circuit 430 and the output stage circuit 440 to adjust the common-mode level of the common-mode voltage output by the error amplifier 400, thereby reducing the drift of the offset voltage of the error amplifier system.

[0074] Based on this, the present invention provides an error amplifier, which uses the MOS tubes arranged in the first steering stage circuit, the second steering stage circuit and the output stage circuit and the resistors connected in series with the MOS tubes, and adopts the common-mode voltage matching technology to set the output common-mode level near the reference voltage VREF, so that the common-mode level of the common-mode voltage output by the error amplifier is almost equal to the reference voltage source, thereby avoiding the sensitivity of the common-mode level of the error amplifier output to the change of the power supply voltage, reducing the drift of the system offset voltage of the error amplifier, and improving the DC accuracy of the output voltage of the BUCK type DC power converter; solving the problem of poor DC accuracy of the output voltage of the DC power converter in the prior art.

[0075] It should be noted that the error amplifier provided by the present invention is suitable for different types of DC voltage converters. For different types of converters, it is only necessary to adjust the width-to-length ratio of the transistor and the resistance value of the series resistor to satisfy the problem of poor DC accuracy of the output voltage of the DC power converter by setting the amplifier output common-mode level near the reference voltage VREF. In the embodiment of the present invention, only a BUCK type DC power converter is used as an example.

[0076] Preferably, the amplifier stage circuit 420 may include: a first PMOS tube, a second PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor R1 and a second resistor R2.

[0077] Specifically, the source of the tenth PMOS tube can be connected to the voltage terminal VDD, the gate of the tenth PMOS tube can be connected to the first terminal VB1, and the drain of the tenth PMOS tube can be connected to the source of the ninth PMOS tube; the gate of the ninth PMOS tube can be connected to the second terminal VB2; one end of the first resistor R1 can be connected to the drain of the ninth PMOS tube, and the other end of the first resistor R1 can be connected to the source of the first PMOS tube; one end of the second resistor R2 can be connected to the drain of the ninth PMOS tube, and the other end of the second resistor R2 can be connected to the source of the second PMOS tube; the gate of the first PMOS tube can be connected to the feedback voltage source terminal VN, and the drain of the first PMOS tube can be connected to the gate of the first NMOS tube; the gate of the second PMOS tube can be connected to the reference voltage source terminal VP, and the drain of the second PMOS tube can be connected to the gate of the second NMOS tube; the gate of the third NMOS tube can be connected to the third terminal VB3 , the drain of the third NMOS tube is connected to the source of the first PMOS tube, and the source of the third NMOS tube is connected to the drain of the first NMOS tube; the gate of the fourth NMOS tube is connected to the third terminal VB3, the drain of the fourth NMOS tube is connected to the source of the second PMOS tube, and the source of the fourth NMOS tube is connected to the drain of the second NMOS tube; the gate of the first NMOS tube is connected to the first steering stage circuit, and the source of the first NMOS tube is grounded; the gate of the second NMOS tube is connected to the second steering stage circuit, and the source of the second NMOS tube is grounded; the drain of the fifth NMOS tube is connected to the gate of the first NMOS tube, the gate of the fifth NMOS tube is connected to the fourth terminal VB4, and the source of the fifth NMOS tube is grounded; the drain of the sixth NMOS tube is connected to the gate of the second NMOS tube, the gate of the sixth NMOS tube is connected to the fourth terminal VB4, and the source of the sixth NMOS tube is grounded. Based on this, the circuit structure corresponding to the amplifier stage circuit in the error amplifier provided by the present invention can be obtained.

[0078] Preferably, in order to realize the source series resistance to reduce the equivalent transconductance, negative feedback resistors of the same type may be used, that is, the first resistor R1 and the second resistor R2 are negative feedback resistors, and the first resistor R1 and the second resistor R2 are of the same type.

[0079] It should be noted that, combined with Figure 1 In an amplifier stage circuit 420 of an error amplifier provided by the present invention, a feedback voltage source terminal VN is connected to a feedback signal VFB, and a reference voltage source terminal VP is connected to a reference voltage signal VREF.

[0080] Preferably, the first steering stage circuit 410 may include: a third PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, a seventh NMOS transistor, a ninth NMOS transistor, an eleventh NMOS transistor and a third resistor R3.

[0081] Specifically, the source of the fifth PMOS tube can be connected to the power supply terminal VDD, the gate of the fifth PMOS tube can be connected to the gate of the third PMOS tube, and the drain of the fifth PMOS tube can be connected to the source of the seventh PMOS tube; the source of the third PMOS tube can be connected to the power supply terminal, the drain of the third PMOS tube can be connected to the drain of the seventh NMOS tube, and the drain of the third PMOS tube can be connected to the gate of the third PMOS tube; the gate of the seventh PMOS tube can be connected to the second terminal VB2, and the drain of the seventh PMOS tube can be connected to the drain of the eleventh NMOS tube; the gate of the eleventh NMOS tube can be connected to the third terminal VB3, the source of the eleventh NMOS tube can be connected to the drain of the ninth NMOS tube, and the drain of the eleventh NMOS tube can be connected to the gate of the ninth NMOS tube; the gate of the ninth NMOS tube can be connected to the second steering stage circuit 430; one end of the third resistor R3 can be connected to the source of the ninth NMOS tube, and the other end of the third resistor R3 can be grounded; the gate of the seventh NMOS tube can be connected to the gate of the first NMOS tube, and the source of the seventh NMOS tube can be grounded. Based on this, the circuit structure corresponding to the first steering stage circuit in the error amplifier provided by the present invention can be obtained.

[0082] It should be noted that the I marked in the first steering stage circuit 410 D1 Represents the current flowing through the third resistor R3.

[0083] Preferably, the second steering stage circuit 430 may include: a fourth PMOS transistor, a sixth PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, a twelfth NMOS transistor and a fourth resistor R4.

[0084] Specifically, the source of the sixth PMOS tube can be connected to the power supply terminal VDD, the gate of the sixth PMOS tube can be connected to the gate of the fourth PMOS tube, and the drain of the sixth PMOS tube can be connected to the source of the eighth PMOS tube; the source of the fourth PMOS tube can be connected to the power supply terminal, the drain of the fourth PMOS tube can be connected to the drain of the eighth NMOS tube, and the drain of the fourth PMOS tube can be connected to the gate of the fourth PMOS tube; the gate of the eighth PMOS tube can be connected to the second terminal VB2, and the drain of the eighth PMOS tube can be connected to the drain of the twelfth NMOS tube; the gate of the twelfth NMOS tube can be connected to the third terminal VB3, the source of the twelfth NMOS tube can be connected to the drain of the tenth NMOS tube, and the drain of the twelfth NMOS tube can be connected to the output stage circuit; the gate of the tenth NMOS tube can be connected to the gate of the ninth NMOS tube; one end of the fourth resistor R4 can be connected to the source of the tenth NMOS tube, and the other end of the fourth resistor R4 can be grounded; the gate of the eighth NMOS tube can be connected to the gate of the second NMOS tube, and the source of the eighth NMOS tube can be grounded. Based on this, the circuit structure corresponding to the second steering stage circuit in the error amplifier provided by the present invention can be obtained.

[0085] Preferably, in order to match the common mode level of the output node of the output stage, series resistors of the same model and MOS tubes of the same model are introduced into the common source circuit, that is, the third resistor R3 and the fourth resistor R4 are of the same model, and the ninth NMOS tube and the tenth NMOS tube are of the same model.

[0086] Preferably, the output stage circuit 440 may include: a thirteenth NMOS transistor, a fourteenth NMOS transistor and a charging capacitor C.

[0087] Specifically, one end of the charging capacitor C can be connected to the gate of the fourteenth NMOS tube, and the other end of the charging capacitor C can be grounded; the drain of the fourteenth NMOS tube can be connected to the power supply terminal, the gate of the fourteenth NMOS tube can be connected to the drain of the twelfth NMOS tube, the source of the fourteenth NMOS tube can be connected to the drain of the thirteenth NMOS tube, and the source of the fourteenth NMOS tube can be connected to the output terminal VOUT; the gate of the thirteenth NMOS tube can be connected to the fourth terminal VB4, and the source of the thirteenth NMOS tube can be grounded. Based on this, the circuit structure corresponding to the output stage circuit in the error amplifier provided by the present invention can be obtained.

[0088] It should be noted that the I marked in the output stage circuit 440 D2 Represents the current flowing through the thirteenth NMOS tube.

[0089] Preferably, when the voltage of the feedback voltage source terminal VN is equal to the voltage of the reference voltage source terminal VP, the formula can be used:

[0090]

[0091] Calculate the common-mode voltage V at the error amplifier output OUT,CM ; Among them, V GS,MN9,10 represents the voltage difference between the gate and source of MN9 or MN10, I D1 represents the current flowing through the third resistor R3, I D2 represents the current flowing through MN13, R d represents the resistance value of the third resistor R3 or the fourth resistor R4, V GS,MN14 represents the voltage difference between the gate and source of MN14, V th,MN9,10 Indicates the threshold voltage of MN9 or MN10, V th,MN14 represents the threshold voltage of MN14, kn represents the calculation constant in the circuit, (W / L) MN9,10 Indicates the width-to-length ratio of MN9 or MN10 (W / L) MN14 Indicates the width-to-length ratio of MN14.

[0092] Preferably, when the body effect of the transistor is neglected, the formula can be used:

[0093]

[0094] Calculate the common-mode voltage at the error amplifier output; where V OUT,CM The common-mode voltage at the output of the error amplifier, V GS,MN9,10 represents the voltage difference between the gate and source of MN9 or MN10, I D1 represents the current flowing through the third resistor R3, I D2 represents the current flowing through MN13, R d represents the resistance value of the third resistor R3 or the fourth resistor R4, V GS,MN14 represents the voltage difference between the gate and source of MN14, kn represents the calculation constant in the circuit, (W / L) MN9,10 Indicates the width-to-length ratio of MN9 or MN10 (W / L) MN14 Indicates the width-to-length ratio of MN14.

[0095] By adjusting the width-to-length ratio of MN9, MN10 and MN14 and the resistance values ​​of the third resistor R3 and the fourth resistor R4, the output common-mode level can be set near the reference voltage VREF. From formula (8) and formula (9), it can be obtained that the output common-mode voltage is not sensitive to the change of the power supply voltage, and the input offset voltage drift caused by the change of the power supply voltage can be effectively reduced.

[0096] It should be noted that the width-to-length ratio of MN9, MN10 and MN14, and the resistance values ​​of the third resistor R3 and the fourth resistor R4 can be adjusted differently according to the process parameters of each electrical component in actual application and the simulation results of the amplifier output common-mode level. When the amplifier output common-mode level is near the reference voltage VREF, the corresponding width-to-length ratio of MN9, MN10 and MN14, and the corresponding resistance values ​​of the third resistor R3 and the fourth resistor R4 are obtained.

[0097] In summary, the DC gain of the error amplifier provided by the present invention can be approximated as:

[0098]

[0099] Furthermore, the main pole frequency of the error amplifier provided by the present invention is approximately:

[0100]

[0101] In formula (10) to formula (11), C represents the charging capacitor, R S Indicates the resistance value of the first resistor R1 or the second resistor R2, R d represents the resistance value of the third resistor R3 or the fourth resistor R4, g mn1,2 Indicates the transconductance of MN1 or MN2, g mn7,8Indicates the transconductance of MN7 or MN8, g mn3,4 Indicates the transconductance of MN3 or MN4, g mp5,6 Indicates the transconductance of MP5 or MP6, g mn12 represents the transconductance of MN12, g mn10 represents the transconductance of MN10, g mp8 represents the transconductance of MP8, r on12 Indicates the resistance value of MN12, r on10 Indicates the resistance value of MN10, r op8 Indicates the resistance value of MP8, r op6 Indicates the resistance value of MP6.

[0102] Furthermore, the unit gain bandwidth GBW of the error amplifier provided by the present invention is approximately:

[0103]

[0104] Combined with formula (4), it can be seen that the GBW results calculated by formula (12) and formula (4) are the same; this indicates that after the common-mode level matching technology is adopted, the unit gain bandwidth of the error amplifier provided by the present invention remains approximately unchanged and has not changed. When the system offset voltage is reduced, the error amplifier provided by the present invention will not affect the original circuit system; compared with the prior art, the use of a larger capacitor to ensure the system stability of the converter is avoided, saving chip area.

[0105] Furthermore, in order to verify that the error amplifier provided by the present invention can solve the problem of poor DC accuracy of the output voltage of the DC power converter in the prior art, the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention are subjected to the following experimental verification.

[0106] As an example, the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention are implemented in a commercial 0.18μm BCD process, the currents of the corresponding branches are set equal, and the simulation parameters are compared to obtain the beneficial effects of the technical solution of the present invention; please refer to Figures 5 to 7 , Figure 5 A schematic diagram comparing the change of the common mode voltage output by the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with the power supply voltage; Figure 6 A schematic diagram comparing the variation of the offset voltage inputted by the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with the power supply voltage; Figure 7 The figure is a schematic diagram comparing the response curves of the phase margin and loop gain of the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with respect to the frequency change under the power supply voltage of 3.3V.

[0107] exist Figure 5In the figure, the horizontal axis represents the power supply voltage in V; the vertical axis represents the output common-mode voltage of the error amplifier in V; Figure 5 In The curve is a curve showing the variation of the common mode voltage of a narrow bandwidth error amplifier with the power supply voltage in the prior art. Figure 5 In The curve is a curve showing the change of the common mode voltage output by the error amplifier provided by the present invention with the power supply voltage. Figure 6 In the figure, the horizontal axis represents the power supply voltage in V, and the vertical axis represents the input offset voltage of the error amplifier in uV. Figure 6 In The curve is a curve showing the variation of the offset voltage of a narrow bandwidth error amplifier with the power supply voltage in the prior art. Figure 6 In The curve is a curve showing the variation of the offset voltage input to the error amplifier provided by the present invention with the power supply voltage.

[0108] It should be noted that for the sake of simplicity, Figure 5 and Figure 6 The curve shown in FIG. 1 is a curve showing the change in common-mode voltage and input offset voltage when the power supply voltage changes from 2.5V to 5.5V.

[0109] from Figure 5 The curves shown clearly show that the output common-mode voltage of the narrow-bandwidth error amplifier in the prior art is approximately linear with the power supply voltage, and the voltage drift variation is approximately 2.9V; while the output common-mode voltage of the error amplifier provided by the present invention is approximately near the reference voltage (0.6V), and is insensitive to power supply voltage variations, and the variation with power supply voltage drift is approximately 128mV.

[0110] from Figure 6 The curve shown clearly shows that the drift of the input offset voltage of the narrow bandwidth error amplifier in the prior art as the power supply voltage changes is about 635uV, while the drift of the input offset voltage of the error amplifier provided by the present invention as the power supply voltage changes is about 16.5uV.

[0111] based on Figure 5 and Figure 6The curve shown verifies the advantages of the error amplifier provided by the present invention, and its output common-mode voltage is approximately near the reference voltage, almost equal, and the drift change with the power supply voltage is about 128mV, which is insensitive to the power supply voltage change, and the drift change of the input offset voltage with the power supply voltage change is about 16.5uV; compared with the prior art, the sensitivity of the error amplifier output common-mode level to the power supply voltage change is avoided, the drift of the system offset voltage of the error amplifier is reduced, and the DC accuracy of the output voltage of the BUCK type DC power converter is improved, thereby better solving the problem of poor DC accuracy of the output voltage of the DC power converter in the prior art.

[0112] Furthermore, the relationship between the change in the error amplifier output common-mode voltage and the input offset voltage can be approximately expressed as follows:

[0113]

[0114] It can be seen from formula (13) that a larger output common-mode voltage obviously corresponds to a larger input offset voltage; this further illustrates that the error amplifier provided by the present invention reduces the output common-mode voltage while also reducing its input offset voltage, which can better improve the DC accuracy of the output voltage of the DC power converter.

[0115] Further, in Figure 7 middle, Figure 7 The response curves of the phase margin and loop gain of the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with respect to the frequency change under the power supply voltage of 3.3V are given, wherein: Figure 7 The two curves in the upper part are the curves of the phase margin of the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention versus frequency, that is, the horizontal axis represents the frequency in Hz, and the vertical axis represents the phase margin in degrees; wherein, The curve is a curve showing the variation of the noise of the narrow bandwidth error amplifier with the loop frequency in the prior art. The curve is a curve showing the variation of the noise of the error amplifier provided by the present invention with the loop frequency; Figure 7 The two curves in the lower part are the loop gain variation curves of the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention with frequency, that is, the horizontal axis represents the frequency in Hz, and the vertical axis represents the loop gain in dB; wherein, The curve is a curve showing the change of the unit gain bandwidth of the narrow bandwidth error amplifier with the loop frequency in the prior art. The curve is a curve showing the change of the unit gain bandwidth of the error amplifier provided by the present invention with the loop frequency.

[0116] from Figure 7It can be obtained without doubt that the unit gain bandwidth of the narrow bandwidth error amplifier in the prior art and the error amplifier provided by the present invention has basically the same trend with the loop frequency, but the DC gain of the narrow bandwidth error amplifier in the prior art is 81.78dB, and the DC gain of the error amplifier of the present invention is 85.62dB, and the DC gain of the error amplifier in the prior art is about 4dB higher than the DC gain of the error amplifier provided by the present invention. It is further explained that the significant effect of the error amplifier provided by the present invention is that the error amplifier can output a common mode voltage with lower power supply sensitivity and higher DC gain, thereby being able to obtain a lower input offset voltage; improve the DC accuracy of the output voltage of the BUCK type DC power converter; solve the problem of poor DC accuracy of the output voltage of the DC power converter in the prior art.

[0117] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0118] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. An error amplifier, characterized in that: include: A first steering stage circuit, an amplifier stage circuit, a second steering stage circuit and an output stage circuit; The first steering stage circuit is connected to the amplifier stage circuit, the amplifier stage circuit is connected to the second steering stage circuit, and the second steering stage circuit is connected to the output stage circuit; The first steering stage circuit, the second steering stage circuit and the output stage circuit are used to adjust the common mode level of the common mode voltage output by the output stage circuit to reduce the drift of the offset voltage of the error amplifier system.

2. The error amplifier according to claim 1, wherein: The amplifier stage circuit includes: a first PMOS tube, a second PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a first resistor and a second resistor; The source of the tenth PMOS tube is connected to the voltage end, the gate of the tenth PMOS tube is connected to the first terminal, and the drain of the tenth PMOS tube is connected to the source of the ninth PMOS tube; the gate of the ninth PMOS tube is connected to the second terminal; one end of the first resistor is connected to the drain of the ninth PMOS tube, and the other end of the first resistor is connected to the source of the first PMOS tube; one end of the second resistor is connected to the drain of the ninth PMOS tube, and the other end of the second resistor is connected to the source of the second PMOS tube; the gate of the first PMOS tube is connected to the feedback voltage source end, and the drain of the first PMOS tube is connected to the gate of the first NMOS tube; the gate of the second PMOS tube is connected to the reference voltage source end, and the drain of the second PMOS tube is connected to the gate of the second NMOS tube; the gate of the third NMOS tube is connected to the third terminal, and the drain of the third NMOS tube is connected to the The source of the first PMOS tube is connected, and the source of the third NMOS tube is connected to the drain of the first NMOS tube; the gate of the fourth NMOS tube is connected to the third terminal, the drain of the fourth NMOS tube is connected to the source of the second PMOS tube, and the source of the fourth NMOS tube is connected to the drain of the second NMOS tube; the gate of the first NMOS tube is connected to the first steering stage circuit, and the source of the first NMOS tube is grounded; the gate of the second NMOS tube is connected to the second steering stage circuit, and the source of the second NMOS tube is grounded; the drain of the fifth NMOS tube is connected to the gate of the first NMOS tube, the gate of the fifth NMOS tube is connected to the fourth terminal, and the source of the fifth NMOS tube is grounded; the drain of the sixth NMOS tube is connected to the gate of the second NMOS tube, the gate of the sixth NMOS tube is connected to the fourth terminal, and the source of the sixth NMOS tube is grounded.

3. The error amplifier according to claim 2, wherein: The first steering stage circuit includes: a third PMOS transistor, a fifth PMOS transistor, a seventh PMOS transistor, a seventh NMOS transistor, a ninth NMOS transistor, an eleventh NMOS transistor and a third resistor; The source of the fifth PMOS tube is connected to the power supply terminal, the gate of the fifth PMOS tube is connected to the gate of the third PMOS tube, and the drain of the fifth PMOS tube is connected to the source of the seventh PMOS tube; the source of the third PMOS tube is connected to the power supply terminal, the drain of the third PMOS tube is connected to the drain of the seventh NMOS tube, and the drain of the third PMOS tube is connected to the gate of the third PMOS tube; the gate of the seventh PMOS tube is connected to the second terminal, and the drain of the seventh PMOS tube is connected to the drain of the eleventh NMOS tube; the gate of the eleventh NMOS tube is connected to the third terminal, the source of the eleventh NMOS tube is connected to the drain of the ninth NMOS tube, and the drain of the eleventh NMOS tube is connected to the gate of the ninth NMOS tube; the gate of the ninth NMOS tube is connected to the second steering stage circuit; one end of the third resistor is connected to the source of the ninth NMOS tube, and the other end of the third resistor is grounded; the gate of the seventh NMOS tube is connected to the gate of the first NMOS tube, and the source of the seventh NMOS tube is grounded.

4. The error amplifier according to claim 3, wherein: The second steering stage circuit includes: a fourth PMOS transistor, a sixth PMOS transistor, an eighth PMOS transistor, an eighth NMOS transistor, a tenth NMOS transistor, a twelfth NMOS transistor and a fourth resistor; The source of the sixth PMOS tube is connected to the power supply terminal, the gate of the sixth PMOS tube is connected to the gate of the fourth PMOS tube, and the drain of the sixth PMOS tube is connected to the source of the eighth PMOS tube; the source of the fourth PMOS tube is connected to the power supply terminal, the drain of the fourth PMOS tube is connected to the drain of the eighth NMOS tube, and the drain of the fourth PMOS tube is connected to the gate of the fourth PMOS tube; the gate of the eighth PMOS tube is connected to the second terminal, and the drain of the eighth PMOS tube is connected to the drain of the twelfth NMOS tube; the gate of the twelfth NMOS tube is connected to the third terminal, the source of the twelfth NMOS tube is connected to the drain of the tenth NMOS tube, and the drain of the twelfth NMOS tube is connected to the output stage circuit; the gate of the tenth NMOS tube is connected to the gate of the ninth NMOS tube; one end of the fourth resistor is connected to the source of the tenth NMOS tube, and the other end of the fourth resistor is grounded; the gate of the eighth NMOS tube is connected to the gate of the second NMOS tube, and the source of the eighth NMOS tube is grounded.

5. The error amplifier according to claim 4, wherein: The output stage circuit comprises: a thirteenth NMOS tube, a fourteenth NMOS tube and a charging capacitor; One end of the charging capacitor is connected to the gate of the fourteenth NMOS tube, and the other end of the charging capacitor is grounded; the drain of the fourteenth NMOS tube is connected to the power supply terminal, the gate of the fourteenth NMOS tube is connected to the drain of the twelfth NMOS tube, the source of the fourteenth NMOS tube is connected to the drain of the thirteenth NMOS tube, and the source of the fourteenth NMOS tube is connected to the output terminal; the gate of the thirteenth NMOS tube is connected to the fourth terminal, and the source of the thirteenth NMOS tube is grounded.

6. The error amplifier according to claim 5, wherein: When the voltage at the feedback voltage source terminal is equal to the voltage at the reference voltage source terminal, the formula is used: Calculate the common-mode voltage at the error amplifier output; where V OUT,CM The common-mode voltage at the output of the error amplifier, V GS,MN9,10 represents the voltage difference between the gate and source of MN9 or MN10, I D1 represents the current flowing through the third resistor, I D2 represents the current flowing through MN13, R d Indicates the resistance value of the third resistor or the fourth resistor, V GS,MN14 represents the voltage difference between the gate and source of MN14, V th,MN9,10 Indicates the threshold voltage of MN9 or MN10, V th,MN14 represents the threshold voltage of MN14, kn represents the calculation constant in the circuit, (W / L) MN9,10 Indicates the width-to-length ratio of MN9 or MN10 (W / L) MN14 Indicates the width-to-length ratio of MN14.

7. The error amplifier according to claim 5, wherein: When the body effect of the transistor is neglected, the formula is used: Calculate the common-mode voltage at the error amplifier output; where V OUT,CM The common-mode voltage at the output of the error amplifier, V GS,MN9,10 represents the voltage difference between the gate and source of MN9 or MN10, I D1 represents the current flowing through the third resistor, I D2 represents the current flowing through MN13, R d Indicates the resistance value of the third resistor or the fourth resistor, V GS,MN14 represents the voltage difference between the gate and source of MN14, kn represents the calculation constant in the circuit, (W / L) MN9,10 Indicates the width-to-length ratio of MN9 or MN10 (W / L) MN14 Indicates the width-to-length ratio of MN14.

8. The error amplifier according to any one of claims 2 to 7, characterized in that: The first resistor and the second resistor have the same model.

9. The error amplifier according to any one of claims 4 to 7, characterized in that: The third resistor and the fourth resistor have the same model.

10. The error amplifier according to claim 6 or 7, characterized in that: The model of the ninth NMOS tube is the same as the model of the tenth NMOS tube.

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