Non-volatile unit-based operational amplifier offset voltage trimming and calibrating device and method

Abstract

The invention discloses an operational amplifier offset voltage trimming and calibrating device and method based on a nonvolatile unit. The device comprises a power supply, a differential voltage input stage, a tail current source, a current mirror with a memristor and a voltage output end, a differential voltage signal is input through the differential voltage input stage and passes through the current mirror with the memristor to obtain an output voltage, the output voltage is output through the voltage output end, the tail current source provides constant current for the differential voltage input stage, and the power supply provides voltage for the whole device. The circuit structure is regular and simple, the trimming range is large, and the system can be reprogrammed regularly.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and more specifically, relates to an operational amplifier offset voltage trimming and calibration device and method based on a non-volatile unit. Background Art

[0002] Operational amplifiers (op amps) are key components in signal processing systems and are widely used in various electronic devices and complex analog chips and mixed analog and digital chips. Op amps are mainly manufactured using CMOS technology. With the advancement of process technology, CMOS technology has continuously optimized the integration and power consumption of integrated circuits. Usually, the input stage of an op amp is composed of a differential amplifier. The internal structure of an ideal differential op amp is highly symmetrical, so that each branch of the circuit remains balanced.

[0003] Theoretically, when the two input voltages of an operational amplifier are completely equal, the output should be zero. However, as the size of devices gradually decreases, especially in advanced processes, when the process feature size approaches the atomic scale and the wavelength of the lithography machine's rays, the error ratio of the device channel length and width gradually increases, making it difficult to achieve devices with ideal parameters. The process mismatch leads to the asymmetry of the input branch, making it impossible for the output to be absolutely zero, which inevitably causes the operational amplifier to produce an offset voltage.

[0004] Several traditional input offset voltage trimming and calibration schemes have been proposed previously. The resistor and fuse trimming scheme has limited accuracy and occupies a large area; the metal film laser trimming requires expensive equipment and cannot be adjusted within the package; and the digital dynamic trimming system is complex and costly.

[0005] The invention patent with the prior art publication number CN115833761A proposes a method for trimming and calibrating the offset voltage of an operational amplifier using an adjustable current source. By adding an adjustable current source to the operational amplifier circuit, the offset voltage can be trimmed and calibrated during the packaging and testing stage to improve the accuracy of the operational amplifier. This solution can only trim and calibrate the offset voltage during the packaging and testing stage, which limits the adaptability to long-term drift or environmental changes. Summary of the invention

[0006] The present invention provides an operational amplifier offset voltage trimming calibration device and method based on a non-volatile unit to overcome the problems of the prior art offset voltage trimming calibration scheme, such as complex circuits, small adjustable range, and lack of adaptability to long-term drift or environmental changes.

[0007] The primary purpose of the present invention is to solve the above technical problems. The technical solution of the present invention is as follows:

[0008] The first aspect of the present invention provides an operational amplifier offset voltage trimming and calibration device based on a non-volatile unit, the device comprising: a power supply, a differential voltage input stage, a tail current source, a current mirror with a memristor, and a voltage output terminal; a differential voltage signal is input through the differential voltage input stage, passes through the current mirror with a memristor, and obtains an output voltage, and the output voltage is output through the voltage output terminal, the tail current source provides a constant current for the differential voltage input stage, and the power supply provides voltage for the entire device.

[0009] Further, the differential voltage input stage includes: a non-inverting input terminal Vinp, an inverting input terminal Vinn, an NMOS transistor M0 and an NMOS transistor M1, and the specific connection relationship is: the gate of the NMOS transistor M0 is connected to the inverting input terminal Vinn, the drain is connected to the drain of the PMOS transistor M3, the gate of the PMOS transistor M5 and the gate of the PMOS transistor M3, and the source is connected to the source of the NMOS transistor M1 and the drain of the NMOS transistor M2; the gate of the NMOS transistor M1 is connected to the non-inverting input terminal Vinp, the drain is connected to the drain of the PMOS transistor M4, the gate of the PMOS transistor M6 and the gate of the PMOS transistor M4, and the source is connected to the drain of the NMOS transistor M2 and the source of the NMOS transistor M0.

[0010] Further, the tail current source includes a current source I, an NMOS transistor M2 and an NMOS transistor M9, and the specific connection relationship is: the first connection end of the current source I is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9, and the gate of the NMOS transistor M2, and the second connection end is connected to the source of the PMOS transistor M5, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the gate of the NMOS transistor M2 is connected to the first connection end of the current source I, the gate of the NMOS transistor M9 and the drain of the NMOS transistor M9, and the drain is connected to the NMOS The source of the S transistor M0 is connected to the source of the NMOS transistor M1, and the source is connected to the source of the NMOS transistor M9, the drain of the NMOS transistor M7, the power supply VSS terminal, and the source of the NMOS transistor M8; the gate of the NMOS transistor M9 is connected to the drain of the NMOS transistor M9, the first connection terminal of the current source I, and the gate of the NMOS transistor M2, the drain is connected to the gate of the NMOS transistor M9, the first connection terminal of the current source I, and the gate of the NMOS transistor M2, and the source is connected to the drain of the NMOS transistor M7, the power supply VSS terminal, the source of the NMOS transistor M2, and the source of the NMOS transistor M8.

[0011] Further, the current mirror includes: PMOS transistors M3, M4, M5, M6, NMOS transistors M7, M8 and a voltage output terminal Vout, and the specific connection relationship is: the gate of the PMOS transistor M3 is connected to the drain of the NMOS transistor M0, the drain of the PMOS transistor M3 and the gate of the PMOS transistor M5, the drain is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M5 and the drain of the NMOS transistor M0, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the gate of the PMOS transistor M4 is connected to the drain of the NMOS transistor M0. The gate of the PMOS transistor M5 is connected to the drain of the NMOS transistor M1, the drain of the PMOS transistor M4, and the gate of the PMOS transistor M6, the drain is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M6, and the drain of the NMOS transistor M1, and the source is connected to the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M5, the source of the PMOS transistor M3, and the source of the PMOS transistor M6; the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M3, and the drain of the NMOS transistor M0, and the drain is connected to the source of the NMOS transistor M7, the gate of the NMOS transistor M7, and the NMOS The gate of the transistor M8 is connected, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M1, the drain is connected to the voltage output terminal Vout and the drain of the NMOS transistor M8, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M3, and the source of the PMOS transistor M4; the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M4, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M1. The source of M7 is connected to the drain of the PMOS transistor M5 and the gate of the NMOS transistor M8, the drain is connected to the source of the NMOS transistor M9, the power supply VSS terminal and the source of the NMOS transistor M8, the source is connected to the gate of the NMOS transistor M7, the gate of the NMOS transistor M8 and the drain of the PMOS transistor M5; the gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M7, the source of the NMOS transistor M7 and the drain of the PMOS transistor M5, the drain is connected to the drain of the PMOS transistor M6 and the voltage output terminal Vout, and the source is connected to the source of the NMOS transistor M9, the power supply VSS terminal and the drain of the NMOS transistor M7.

[0012] Further, the memristor includes a first memristor R1 and a second memristor R2, which are introduced into the circuit in parallel, and the specific connection relationship is: the first port of the first memristor is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M5, the drain of the PMOS transistor M3 and the drain of the NMOS transistor M0, and the second port is connected to the second port of the second memristor, the source of the PMOS transistor M5, the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the first port of the second memristor is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M6, the drain of the PMOS transistor M4 and the drain of the NMOS transistor M1, and the second port is connected to the second port of the first memristor, the source of the PMOS transistor M5, the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6.

[0013] Furthermore, the memristor includes a first memristor R1 and a second memristor R2, which are introduced into the circuit in series, and the specific connection relationship is: the first port of the first memristor is connected to the drain of the NMOS transistor M0, and the second port is connected to the drain of the PMOS transistor M3 and the gate of the PMOS transistor M3; the first port of the second memristor is connected to the drain of the NMOS transistor M1, and the second port is connected to the drain of the PMOS transistor M4 and the gate of the PMOS transistor M4.

[0014] A second aspect of the present invention provides an operational amplifier offset voltage trimming and calibration method based on a non-volatile unit, wherein the device is used to trim and calibrate an input differential voltage signal to implement a voltage following function, and the method comprises the following steps:

[0015] Apply voltage Vinp to the non-inverting input terminal of the operational amplifier, connect the inverting input terminal to Vout, record the voltage value of the output terminal, calculate the difference between the output terminal voltage and the non-inverting input terminal Vinp, and obtain the initial offset voltage;

[0016] According to the initial offset voltage and the current resistance of the memristor, the adjustment direction and amplitude of the resistance of the memristor are calculated;

[0017] updating the resistance value of the memristor, and using the updated memristor to fine-tune the current of the operational amplifier to compensate for the offset voltage;

[0018] The above steps are repeated until the offset voltage at the output terminal reaches a preset threshold range.

[0019] Furthermore, the resistance value of the memristor is quantitatively updated by applying a programming pulse.

[0020] Furthermore, when the memristor is introduced into the circuit in parallel, if the initial offset voltage is negative, the resistance of the first memristor is reduced or the resistance of the second memristor is increased; if the initial offset voltage is positive, the resistance of the first memristor is increased or the resistance of the second memristor is reduced. The adjustment range of the memristor resistance is estimated by the following expression:

[0021]

[0022] Where R1 is the resistance of the first memristor, R2 is the resistance of the second memristor, μ p is the carrier mobility, C ox is the gate oxide capacitance per unit area, V bottom1 is the voltage value at the first port of memristor R1, V bottom2 is the voltage value at the first port of memristor R2, V TH3 is the threshold voltage of the PMOS transistor M3, V TH4 is the threshold voltage of the PMOS transistor M4, (W / L)3 is the aspect ratio of the PMOS transistor M3, and (W / L)4 is the aspect ratio of the PMOS transistor M4.

[0023] Furthermore, when the memristor is introduced into the circuit in series, if the initial offset voltage is negative, the resistance of the first memristor is increased or the resistance of the second memristor is decreased; if the initial offset voltage is positive, the resistance of the first memristor is decreased or the resistance of the second memristor is increased. The adjustment range of the memristor resistance is estimated by the following expression:

[0024]

[0025] Where R1 is the resistance of the first memristor, R2 is the resistance of the second memristor, V bottom1 is the voltage value at the first port of memristor R1, V bottom2 is the voltage value at the first port of memristor R2, V top1 is the voltage value at the second port of memristor R1, V top2 is the voltage value at the second port of the memristor R2, and the adjustment range of the memristor resistance is estimated by this formula.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] The present invention proposes a regular circuit structure. For a standard differential operational amplifier, a memristor is only introduced in parallel with the MOS tube, so that the circuit structure is more concise, the adjustment circuit occupies a small area and has a wide adjustment range. Without adjustment, the input offset voltage range of the CMOS operational amplifier is -55.1mV to 52.5mV; after adjustment by the structure of the present invention, the offset voltage can be accurately controlled within 120uV. In addition, the memristor used in the present invention has an overwrite function, which can periodically reprogram the system to cope with long-term drift, and can be modified according to new requirements, thereby supporting conventional recalibration procedures. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to make the purpose and technical solution of the present invention clearer, the present invention provides the following drawings and descriptions:

[0029] Figure 1 A circuit diagram of a parallel connection scheme provided by an embodiment of the present invention;

[0030] Figure 2 A circuit diagram of a first series connection scheme provided by an embodiment of the present invention;

[0031] Figure 3 A circuit diagram of a second series connection scheme provided by an embodiment of the present invention;

[0032] Figure 4 A circuit diagram of a third series connection scheme provided by an embodiment of the present invention;

[0033] Figure 5 A circuit diagram of a voltage follower circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0036] Embodiment 1:

[0037] The present invention provides an operational amplifier offset voltage trimming and calibration device based on a non-volatile unit, such as Figure 1The figure shows a circuit diagram of an operational amplifier offset voltage trimming and calibration device based on a non-volatile unit, wherein the device comprises: a power supply, a differential voltage input stage, a tail current source, a current mirror with a memristor, and a voltage output terminal; a differential voltage signal is input through the differential voltage input stage, passes through the current mirror with a memristor, and obtains an output voltage, which is output through the voltage output terminal, the tail current source provides a constant current for the differential voltage input stage, and the power supply provides voltage for the entire device.

[0038] More specifically, the differential voltage input stage includes: a non-inverting input terminal Vinp, an inverting input terminal Vinn, an NMOS transistor M0 and an NMOS transistor M1, and the specific connection relationship is: the gate of the NMOS transistor M0 is connected to the inverting input terminal Vinn, the drain is connected to the drain of the PMOS transistor M3, the gate of the PMOS transistor M5 and the gate of the PMOS transistor M3, and the source is connected to the source of the NMOS transistor M1 and the drain of the NMOS transistor M2; the gate of the NMOS transistor M1 is connected to the non-inverting input terminal Vinp, the drain is connected to the drain of the PMOS transistor M4, the gate of the PMOS transistor M6 and the gate of the PMOS transistor M4, and the source is connected to the drain of the NMOS transistor M2 and the source of the NMOS transistor M0.

[0039] More specifically, the tail current source includes a current source I, an NMOS transistor M2 and an NMOS transistor M9, and the specific connection relationship is: the first connection end of the current source I is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9, and the gate of the NMOS transistor M2, and the second connection end is connected to the source of the PMOS transistor M5, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the gate of the NMOS transistor M2 is connected to the first connection end of the current source I, the gate of the NMOS transistor M9 and the drain of the NMOS transistor M9, and the drain is connected to the NMOS transistor M5. The source of the S transistor M0 is connected to the source of the NMOS transistor M1, and the source is connected to the source of the NMOS transistor M9, the drain of the NMOS transistor M7, the power supply VSS terminal, and the source of the NMOS transistor M8; the gate of the NMOS transistor M9 is connected to the drain of the NMOS transistor M9, the first connection terminal of the current source I, and the gate of the NMOS transistor M2, the drain is connected to the gate of the NMOS transistor M9, the first connection terminal of the current source I, and the gate of the NMOS transistor M2, and the source is connected to the drain of the NMOS transistor M7, the power supply VSS terminal, the source of the NMOS transistor M2, and the source of the NMOS transistor M8.

[0040] More specifically, the current mirror includes: PMOS transistors M3, M4, M5, M6, NMOS transistors M7, M8 and a voltage output terminal Vout, and the specific connection relationship is: the gate of the PMOS transistor M3 is connected to the drain of the NMOS transistor M0, the drain of the PMOS transistor M3 and the gate of the PMOS transistor M5, the drain is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M5 and the drain of the NMOS transistor M0, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M4 and the source of the PMOS transistor M6; the gate of the PMOS transistor M4 is connected to the drain of the NMOS transistor M0. The gate of the PMOS transistor M5 is connected to the drain of the NMOS transistor M1, the drain of the PMOS transistor M4, and the gate of the PMOS transistor M6, the drain is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M6, and the drain of the NMOS transistor M1, and the source is connected to the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M5, the source of the PMOS transistor M3, and the source of the PMOS transistor M6; the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M3, and the drain of the NMOS transistor M0, and the drain is connected to the source of the NMOS transistor M7, the gate of the NMOS transistor M7, and the NMOS The gate of the transistor M8 is connected, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M1, the drain is connected to the voltage output terminal Vout and the drain of the NMOS transistor M8, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M3, and the source of the PMOS transistor M4; the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M4, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M1. The source of M7 is connected to the drain of the PMOS transistor M5 and the gate of the NMOS transistor M8, the drain is connected to the source of the NMOS transistor M9, the power supply VSS terminal and the source of the NMOS transistor M8, the source is connected to the gate of the NMOS transistor M7, the gate of the NMOS transistor M8 and the drain of the PMOS transistor M5; the gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M7, the source of the NMOS transistor M7 and the drain of the PMOS transistor M5, the drain is connected to the drain of the PMOS transistor M6 and the voltage output terminal Vout, and the source is connected to the source of the NMOS transistor M9, the power supply VSS terminal and the drain of the NMOS transistor M7.

[0041] More specifically, the memristor includes a first memristor R1 and a second memristor R2. The memristor has an overwrite function, and the system can be reprogrammed regularly to cope with long-term drift, and can be modified according to new requirements to support conventional recalibration procedures. The circuit can be introduced in parallel, and the specific connection relationship is: the first port of the first memristor is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M5, the drain of the PMOS transistor M3, and the drain of the NMOS transistor M0, and the second port is connected to the second port of the second memristor, the source of the PMOS transistor M5, and the second connection of the current source I The first port of the second memristor is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M6, the drain of the PMOS transistor M4 and the drain of the NMOS transistor M1, and the second port is connected to the second port of the first memristor, the source of the PMOS transistor M5, the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M3, the source of the PMOS transistor M4 and the source of the PMOS transistor M6.

[0042] In addition to the parallel connection, the memristor can also be introduced into the circuit in series. The specific connection relationship is: the first port of the first memristor is connected to the drain of the NMOS transistor M0, and the second port is connected to the drain of the PMOS transistor M3 and the gate of the PMOS transistor M3; the first port of the second memristor is connected to the drain of the NMOS transistor M1, and the second port is connected to the drain of the PMOS transistor M4 and the gate of the PMOS transistor M4. The circuit diagram is shown in FIG. Figure 2 shown.

[0043] Alternatively, the series connection can also be realized by the following connection relationship: the first port of the first memristor is connected to the drain of the NMOS transistor M0, the gate of the PMOS transistor M3 and the gate of the PMOS transistor M5, and the second port is connected to the drain of the PMOS transistor M3; the first port of the second memristor is connected to the drain of the NMOS transistor M1, the gate of the PMOS transistor M4 and the gate of the PMOS transistor M6, and the second port is connected to the drain of the PMOS transistor M4. The circuit diagram is as shown in FIG. Figure 3 shown.

[0044] Furthermore, the series connection can also be realized by the following connection relationship: the first port of the first memristor is connected to the drain of the NMOS transistor M0 and the gate of the PMOS transistor M5, and the second port is connected to the drain of the PMOS transistor M3 and the gate of the PMOS transistor M3; the first port of the second memristor is connected to the drain of the NMOS transistor M1 and the gate of the PMOS transistor M6, and the second port is connected to the drain of the PMOS transistor M4 and the gate of the PMOS transistor M4. The circuit diagram is as shown in FIG. Figure 4 shown.

[0045] The working principle of the circuit is as follows: a differential voltage signal is input into PMOS transistors M0 and M1, and M0 and M1 output a differential signal current;

[0046] The differential signal current is input into the NMOS transistor M2, and the tail current bias is provided through M2; the current output from the current source I is input into the NMOS transistor M9 for replication, and a stable tail current is output through the NMOS transistor M2 to ensure the stability of the operating points of M0 and M1;

[0047] PMOS transistors M3, M4, M5, and M6, and NMOS transistors M7 and M8 form a basic current mirror. M4 amplifies the current flowing out of M1 by N times and transmits it to M6 to the output end. M3 amplifies the current flowing out of M0 by N times and transmits it to M5. N is determined by the aspect ratio of M3 and M5. If L3=500n and W3=900n of M3, and L5=500n and W5=3.6u of M5, then N=4. The current of M5 is mirrored to M8 through M7. A memristor is introduced between the gate and source of M3 and M5. Similarly, a memristor is introduced between the gate and source of M4 and M6. The current can be fine-tuned by changing the resistance of the memristor to achieve compensation for the offset voltage.

[0048] The present invention proposes a regular circuit structure. For a standard differential operational amplifier, a memristor is only introduced in parallel on the MOS tube, so that the circuit structure is more concise, the adjustment circuit occupies a small area and has a wide adjustment range. Without adjustment, the input offset voltage range of the CMOS operational amplifier is -55.1mV to 52.5mV; after adjustment by the structure of the present invention, the offset voltage can be accurately controlled within 120uV.

[0049] Embodiment 2:

[0050] This embodiment provides an operational amplifier offset voltage trimming and calibration method based on a non-volatile unit. The method trims and calibrates an input differential voltage signal by combining the offset voltage trimming and calibration device described in Embodiment 1, and includes the following steps:

[0051] like Figure 5The external circuit diagram of the present invention for realizing the voltage following function is shown, applying voltage Vinp to the in-phase input terminal of the operational amplifier, connecting the inverting input terminal to Vout, recording the voltage value of the output terminal, calculating the difference between the output terminal voltage and the in-phase input terminal Vinp, and obtaining the initial offset voltage;

[0052] According to the initial offset voltage and the current resistance of the memristor, the adjustment direction and amplitude of the resistance of the memristor are calculated;

[0053] updating the resistance value of the memristor, and using the updated memristor to fine-tune the current of the operational amplifier to compensate for the offset voltage;

[0054] The above steps are repeated until the offset voltage at the output terminal reaches a preset threshold range.

[0055] More specifically, the resistance value of the memristor is quantitatively updated by applying a programming pulse.

[0056] More specifically, when the memristor is introduced into the circuit in parallel, if the initial offset voltage is negative, the resistance of the first memristor is reduced or the resistance of the second memristor is increased; if the initial offset voltage is positive, the resistance of the first memristor is increased or the resistance of the second memristor is reduced. The adjustment range of the memristor resistance can be estimated by the following expression:

[0057]

[0058] Where R1 is the resistance of the first memristor, R2 is the resistance of the second memristor, μ p is the carrier mobility, C ox is the gate oxide capacitance per unit area, V bottom1 is the voltage value at the first port of memristor R1, V bottom2 is the voltage value at the first port of memristor R2, V TH3 is the threshold voltage of the PMOS transistor M3, V TH4 is the threshold voltage of the PMOS transistor M4, (W / L)3 is the aspect ratio of the PMOS transistor M3, and (W / L)4 is the aspect ratio of the PMOS transistor M4.

[0059] Alternatively, when the memristor is introduced into the circuit in series, if the initial offset voltage is negative, the resistance of the first memristor is increased or the resistance of the second memristor is decreased; if the initial offset voltage is positive, the resistance of the first memristor is decreased or the resistance of the second memristor is increased. The adjustment range of the memristor resistance can be estimated by the following expression:

[0060]

[0061] Where R1 is the resistance of the first memristor, R2 is the resistance of the second memristor, V bottom1is the voltage value at the first port of memristor R1, V bottom2 is the voltage value at the first port of memristor R2, V top1 is the voltage value at the second port of memristor R1, V top2 is the voltage value at the second port of the memristor R2, and the adjustment range of the memristor resistance is estimated by this formula.

[0062] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. An operational amplifier offset voltage trimming and calibration device based on a non-volatile unit, characterized in that: The device comprises: a power supply, a differential voltage input stage, a tail current source, a current mirror with a memristor, and a voltage output terminal; a differential voltage signal is input through the differential voltage input stage, passes through the current mirror with a memristor, and obtains an output voltage, and the output voltage is output through the voltage output terminal, the tail current source provides a constant current for the differential voltage input stage, and the power supply provides voltage for the entire device.

2. The operational amplifier offset voltage trimming and calibration device based on a non-volatile unit according to claim 1, characterized in that: The differential voltage input stage includes: a non-inverting input terminal Vinp, an inverting input terminal Vinn, an NMOS transistor M0 and an NMOS transistor M1, and the specific connection relationship is: the gate of the NMOS transistor M0 is connected to the inverting input terminal Vinn, the drain is connected to the drain of the PMOS transistor M3, the gate of the PMOS transistor M5 and the gate of the PMOS transistor M3, and the source is connected to the source of the NMOS transistor M1 and the drain of the NMOS transistor M2; the gate of the NMOS transistor M1 is connected to the non-inverting input terminal Vinp, the drain is connected to the drain of the PMOS transistor M4, the gate of the PMOS transistor M6 and the gate of the PMOS transistor M4, and the source is connected to the drain of the NMOS transistor M2 and the source of the NMOS transistor M0.

3. The operational amplifier offset voltage trimming and calibration device based on a non-volatile unit according to claim 1, characterized in that: The tail current source includes a current source I, an NMOS transistor M2 and an NMOS transistor M9, and the specific connection relationship is: the first connection end of the current source I is connected to the gate of the NMOS transistor M9, the drain of the NMOS transistor M9, and the gate of the NMOS transistor M2, and the second connection end is connected to the source of the PMOS transistor M5, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; the gate of the NMOS transistor M2 is connected to the first connection end of the current source I, the gate of the NMOS transistor M9 and the drain of the NMOS transistor M9, and the drain is connected to the NMOS transistor M5. The source of the NMOS transistor M0 is connected to the source of the NMOS transistor M1, the source is connected to the source of the NMOS transistor M9, the drain of the NMOS transistor M7, the power supply VSS terminal, and the source of the NMOS transistor M8; the gate of the NMOS transistor M9 is connected to the drain of the NMOS transistor M9, the first connection terminal of the current source I, and the gate of the NMOS transistor M2, the drain is connected to the gate of the NMOS transistor M9, the first connection terminal of the current source I, and the gate of the NMOS transistor M2, and the source is connected to the drain of the NMOS transistor M7, the power supply VSS terminal, the source of the NMOS transistor M2, and the source of the NMOS transistor M8.

4. The operational amplifier offset voltage trimming and calibration device based on a non-volatile unit according to claim 1, characterized in that: The current mirror includes: PMOS transistors M3, M4, M5, M6, NMOS transistors M7, M8 and a voltage output terminal Vout, and the specific connection relationship is: the gate of the PMOS transistor M3 is connected to the drain of the NMOS transistor M0, the drain of the PMOS transistor M3 and the gate of the PMOS transistor M5, the drain is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M5 and the drain of the NMOS transistor M0, the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M4 and the source of the PMOS transistor M6; the gate of the PMOS transistor M4 is connected to the NMOS transistor M0. The drain of the S transistor M1, the drain of the PMOS transistor M4 and the gate of the PMOS transistor M6 are connected, the drain is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M6 and the drain of the NMOS transistor M1, and the source is connected to the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M5, the source of the PMOS transistor M3 and the source of the PMOS transistor M6; the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M3, the drain of the PMOS transistor M3 and the drain of the NMOS transistor M0, and the drain is connected to the source of the NMOS transistor M7, the gate of the NMOS transistor M7 and the drain of the NMOS transistor M1. The gate of the PMOS transistor M6 is connected to the gate of the PMOS transistor M4, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M1, the drain is connected to the voltage output terminal Vout and the drain of the NMOS transistor M8, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M3, and the source of the PMOS transistor M4; the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M4, the drain of the PMOS transistor M4, and the drain of the NMOS transistor M1, the drain is connected to the voltage output terminal Vout and the drain of the NMOS transistor M8, and the source is connected to the second connection terminal of the current source I, the power supply VDD terminal, the source of the PMOS transistor M5, the source of the PMOS transistor M3, and the source of the PMOS transistor M4; the gate of the NMOS transistor M7 is connected to the gate of the NMOS transistor M The gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M7, the source of the NMOS transistor M7 and the drain of the PMOS transistor M5, the drain is connected to the drain of the PMOS transistor M6 and the voltage output terminal Vout, and the source is connected to the source of the NMOS transistor M9, the power supply VSS terminal and the source of the NMOS transistor M8. The source is connected to the gate of the NMOS transistor M7, the gate of the NMOS transistor M8 and the drain of the PMOS transistor M5; the gate of the NMOS transistor M8 is connected to the gate of the NMOS transistor M7, the source of the NMOS transistor M7 and the drain of the PMOS transistor M5, the drain is connected to the drain of the PMOS transistor M6 and the voltage output terminal Vout, and the source is connected to the source of the NMOS transistor M9, the power supply VSS terminal and the drain of the NMOS transistor M7.

5. The operational amplifier offset voltage trimming and calibration device based on a non-volatile unit according to claim 1, characterized in that: The memristor includes a first memristor R1 and a second memristor R2, which are introduced into the circuit in parallel, and the specific connection relationship is: the first port of the first memristor is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M5, the drain of the PMOS transistor M3 and the drain of the NMOS transistor M0, and the second port is connected to the second port of the second memristor, the source of the PMOS transistor M5, the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M6; The first port of the second memristor is connected to the gate of the PMOS transistor M4, the gate of the PMOS transistor M6, the drain of the PMOS transistor M4 and the drain of the NMOS transistor M1, and the second port is connected to the second port of the first memristor, the source of the PMOS transistor M5, the second connection end of the current source I, the power supply VDD end, the source of the PMOS transistor M3, the source of the PMOS transistor M4 and the source of the PMOS transistor M6.

6. The operational amplifier offset voltage trimming and calibration device based on a non-volatile unit according to claim 1, characterized in that: The memristor includes a first memristor R1 and a second memristor R2, which are introduced into the circuit in series. The specific connection relationship is: the first port of the first memristor is connected to the drain of the NMOS transistor M0, and the second port is connected to the drain of the PMOS transistor M3, the gate of the PMOS transistor M5 and the gate of the PMOS transistor M3; the first port of the second memristor is connected to the drain of the NMOS transistor M1, and the second port is connected to the drain of the PMOS transistor M4, the gate of the PMOS transistor M6 and the gate of the PMOS transistor M4.

7. An operational amplifier offset voltage trimming and calibration method based on a non-volatile unit, characterized in that: The method adjusts and calibrates the input differential voltage signal by combining the offset voltage adjustment and calibration device described in claims 1 to 6 to achieve a voltage following function, and includes the following steps: Apply voltage Vinp to the non-inverting input terminal of the operational amplifier, connect the inverting input terminal to Vout, record the voltage value of the output terminal, calculate the difference between the output terminal voltage and the non-inverting input terminal Vinp, and obtain the initial offset voltage; According to the initial offset voltage and the current resistance of the memristor, the adjustment direction and amplitude of the resistance of the memristor are calculated; updating the resistance value of the memristor, and using the updated memristor to fine-tune the current of the operational amplifier to compensate for the offset voltage; The above steps are repeated until the offset voltage at the output terminal reaches a preset threshold range.

8. The method for adjusting and calibrating offset voltage of an operational amplifier based on a non-volatile unit according to claim 7, characterized in that: The resistance value of the memristor is quantitatively updated by applying a programming pulse.

9. The method for adjusting and calibrating offset voltage of an operational amplifier based on a non-volatile unit according to claim 7, characterized in that: When the memristor is introduced into the circuit in parallel, if the initial offset voltage is negative, the resistance of the first memristor is reduced or the resistance of the second memristor is increased; if the initial offset voltage is positive, the resistance of the first memristor is increased or the resistance of the second memristor is reduced. The adjustment range of the memristor resistance is estimated by the following expression: Where R1 is the resistance of the first memristor, R2 is the resistance of the second memristor, μ p is the carrier mobility, C ox is the gate oxide capacitance per unit area, V bottom1 is the voltage value at the first port of memristor R1, V bottom2 is the voltage value at the first port of memristor R2, V TH3 is the threshold voltage of the PMOS transistor M3, V TH4 is the threshold voltage of the PMOS transistor M4, (W / L)3 is the aspect ratio of the PMOS transistor M3, and (W / L)4 is the aspect ratio of the PMOS transistor M4.

10. The method for adjusting and calibrating offset voltage of an operational amplifier based on a non-volatile unit according to claim 7, characterized in that: When the memristor is introduced into the circuit in series, if the initial offset voltage is negative, the resistance of the first memristor is increased or the resistance of the second memristor is decreased; if the initial offset voltage is positive, the resistance of the first memristor is decreased or the resistance of the second memristor is increased. The adjustment range of the memristor resistance is estimated by the following expression: Where R1 is the resistance of the first memristor, R2 is the resistance of the second memristor, V bottom1 is the voltage value at the first port of memristor R1, V bottom2 is the voltage value at the first port of memristor R2, V top1 is the voltage value at the second port of memristor R1, V top2 is the voltage value at the second port of the memristor R2, and the adjustment range of the memristor resistance is estimated by this formula.

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