Capacitive coupling type isolation device and receiving end circuit

Abstract

The invention discloses a capacitive coupling type isolation device and a receiving end circuit. The capacitive coupling type isolation device comprises an external coupling capacitor and a receiving end circuit. One end of the external coupling capacitor is electrically connected with a transmitting end circuit, and the other end is electrically connected with the receiving end circuit. The receiver circuit includes a protection circuit architecture. The protection circuit architecture includes an input bonding pad structure and a filter resistor. The input bonding pad structure is formed by staggering a plurality of patterned metal layers and a plurality of dielectric layers, and comprises a bonding pad capacitor and a filter capacitor. The first end of the pad capacitor is electrically connected to the external coupling capacitor, and the filter capacitor is electrically connected to the second end of the pad capacitor and the grounding end. The filter resistor is also electrically connected to the second end of the pad capacitor and the ground terminal. And the filter capacitor and the filter resistor form a low-pass filter. The external coupling capacitor is a built-in packaging capacitor. Through the protection circuit architecture, the receiving end circuit can be protected from being damaged by ESD events.

Description

Technical Field

[0001] The present application relates to an isolation device, and in particular to a capacitive coupling isolation device and a receiving end circuit. Background Art

[0002] There are two types of existing capacitive coupling isolators: one is an on-chip isolation and coupling capacitor, for example, a high-voltage isolation coupling capacitor is provided in a transmitter circuit and a receiver circuit; the other is a built-in package isolation and coupling capacitor isolator, in which a high-voltage isolation coupling capacitor is built into the package instead of being provided in the transmitter circuit and the receiver circuit.

[0003] For on-chip isolation and coupling capacitors, special semiconductor processes are required. In order to meet the isolation voltage requirements, the capacitor not only needs a certain capacitance dielectric thickness, but also a certain isolation distance between its electrodes and other circuits to prevent the influence of electric field coupling on other circuits, resulting in an increase in the chip size of the transmitter circuit and the receiver circuit.

[0004] In the isolator with built-in isolation coupling capacitor, high breakdown voltage (HV) capacitors are not set in the transmitter circuit and the receiver circuit (called off-chip transmitter circuit and off-chip receiver circuit). In this isolator, the input pad of the off-chip receiver circuit is connected to the built-in isolation coupling capacitor of the package through wire bonding. However, in the packaging process of this isolator, electrostatic discharge (ESD) problems will be faced, especially in the die bonding and wire bonding processes. Although the conventional method can directly add an ESD protection unit (for example, a Zener diode) to the input pad of the off-chip receiver circuit to protect the off-chip receiver circuit from damage caused by ESD events. However, this additional ESD protection unit will cause the common mode transient immunity (CMTI) performance of the built-in package isolation and coupling capacitor isolator to be poor, so the isolator cannot meet the CMTI requirements. Summary of the invention

[0005] The technical problem to be solved by the present application is to provide a receiving end circuit with a protection circuit architecture and a capacitive coupling isolation device with the receiving end circuit to prevent electrostatic discharge events from causing damage to the receiving end circuit.

[0006] In order to solve the above-mentioned technical problems, one of the technical solutions adopted in the present application is to provide a capacitive coupling isolation device, the capacitive coupling isolation device comprising: an external coupling capacitor, one end of the external coupling capacitor is electrically connected to a transmitting end circuit; and a receiving end circuit is electrically connected to the other end of the external coupling capacitor, the receiving end circuit comprises: a protection circuit architecture, comprising: an input bonding pad structure, formed by staggering a plurality of patterned metal layers and a plurality of dielectric layers, comprising: a pad capacitor, a first end of the pad capacitor is electrically connected to the other end of the external coupling capacitor; and a filter capacitor, electrically connected to the second end of the pad capacitor and a ground end; and a filter resistor, electrically connected to the second end of the pad capacitor and the ground end, wherein the filter capacitor and the filter resistor form a low-pass filter; wherein the external coupling capacitor is a built-in package (built-in The built-in package capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is electrically connected to the sending end circuit, and the second electrode plate is electrically connected to the first end of the pad capacitor.

[0007] Optionally, in the capacitive coupling isolation device as described above, the first electrode plate is electrically connected to the transmitting end circuit through a first wire by bonding, and the second electrode plate is electrically connected to the first end of the pad capacitor by bonding through a second wire.

[0008] Optionally, in the capacitive coupling isolation device as described above, the patterned metal layer includes at least a first patterned metal layer, a second patterned metal layer, a third patterned metal layer and a fourth patterned metal layer, the dielectric layer includes at least a first dielectric layer arranged between the first patterned metal layer and the second patterned metal layer, a second dielectric layer between the second patterned metal layer and the third patterned metal layer, and a third dielectric layer arranged between the third patterned metal layer and the fourth patterned metal layer, the first patterned metal layer, the first dielectric layer and the second patterned metal layer are used to form the pad capacitor, and the third patterned metal layer, the third dielectric layer and the fourth patterned metal layer are used to form the filter capacitor.

[0009] Optionally, in the capacitive coupling isolation device as described above, the second patterned metal layer is connected to the third patterned metal layer through a plurality of conductive connectors.

[0010] Optionally, in the capacitively coupled isolation device as described above, the first patterned metal layer, the second patterned metal layer, the third patterned metal layer and the fourth patterned metal layer are arranged in a circuit substrate, and are respectively located in a first metal layer, a second metal layer, an N-1th metal layer and an Nth metal layer arranged from top to bottom of the circuit substrate, where N is a positive integer.

[0011] Optionally, the capacitive coupling isolation device as described above further includes a DC isolation capacitor electrically connected to the second end of the pad capacitor and a core circuit of the receiving end circuit.

[0012] Optionally, in the capacitive coupling isolation device as described above, the DC isolation capacitor is a Metal-Insulator-Metal (MIM) capacitor.

[0013] Optionally, in the capacitive coupling isolation device as described above, the metal-insulator-metal capacitor is disposed in the circuit substrate and includes a fifth patterned metal layer and a sixth patterned metal layer.

[0014] Optionally, in the capacitive coupling isolation device as described above, the fifth patterned metal layer is located in a third metal layer of the circuit substrate, and the sixth patterned metal layer is located in a fourth metal layer or the N-1th metal layer of the circuit substrate.

[0015] In order to solve the above-mentioned technical problems, another technical solution adopted by the present application is to provide a capacitive coupling isolation device, which includes: an external coupling capacitor, whose first end is electrically connected to a transmitting end circuit; and a receiving end circuit, which is electrically connected to the second end of the external coupling capacitor, and the receiving end circuit includes: a protection circuit architecture, including: an input bonding pad structure, which is formed by alternating multiple patterned metal layers and multiple dielectric layers, and the input bonding pad structure includes a filter capacitor, which is electrically connected to the second end of the external coupling capacitor and a ground end; a filter resistor, which is electrically connected to the second end of the external coupling capacitor and the ground end, wherein the filter capacitor and the filter resistor form a low-pass filter; and a DC isolation capacitor, which is electrically connected to the second end of the external coupling capacitor and a core circuit of the receiving end circuit.

[0016] Optionally, in the capacitive coupling isolation device as described above, the patterned metal layer of the input bonding pad structure includes at least a first patterned metal layer, a second patterned metal layer and a third patterned metal layer, and the dielectric layer includes at least a first dielectric layer arranged between the first patterned metal layer and the second patterned metal layer and a second dielectric layer arranged between the second patterned metal layer and the third patterned metal layer, and the second patterned metal layer, the second dielectric layer and the third patterned metal layer are used to form the filter capacitor.

[0017] Optionally, in the capacitive coupling isolation device as described above, the first patterned metal layer is connected to the second patterned metal layer through a plurality of first conductive connectors.

[0018] Optionally, in the capacitive coupling isolation device as described above, the patterned metal layer of the input bonding pad structure also includes a fourth patterned metal layer, the dielectric layer also includes a third dielectric layer, the fourth patterned metal layer is located between the first patterned metal layer and the second patterned metal layer, and the first patterned metal layer, the fourth patterned metal layer and the third dielectric layer located between the first patterned metal layer and the fourth patterned metal layer constitute a pad capacitor, and the first patterned metal layer is electrically connected to the second end of the external coupling capacitor.

[0019] Optionally, in the capacitive coupling isolation device as described above, the external coupling capacitor is a built-in package capacitor, which includes a first electrode plate and a second electrode plate, the first electrode plate is electrically connected to the transmitting end circuit, and the second electrode plate is electrically connected to the first patterned metal layer.

[0020] Optionally, in the capacitive coupling isolation device as described above, the DC isolation capacitor is a finger capacitor, a parallel plate capacitor or a MIM capacitor, and at least includes a fifth patterned metal layer, a fourth dielectric layer and a sixth patterned metal layer, wherein the fourth dielectric layer is located between the fifth patterned metal layer and the sixth patterned metal layer.

[0021] Optionally, in the capacitive coupling isolation device as described above, the patterned metal layer is disposed in a circuit substrate, and the sixth patterned metal layer of the DC isolation capacitor is electrically connected to the filter capacitor via a patterned circuit.

[0022] In order to solve the above-mentioned technical problems, another technical solution adopted in the present application is to provide a receiving end circuit, which is suitable for an isolation device, and the receiving end circuit includes: a protection circuit architecture, including: an input bonding pad structure, including at least a first patterned metal layer, a second patterned metal layer, a first dielectric layer located between the first patterned metal layer and the second patterned metal layer, a third patterned metal layer and a second dielectric layer located between the second patterned metal layer and the third patterned metal layer, wherein the second patterned metal layer, the second dielectric layer and the third patterned metal layer constitute a filter capacitor, one end of the filter capacitor is electrically connected to an external coupling capacitor through the first patterned metal layer, and the other end of the filter capacitor is electrically connected to a ground terminal; and a filter resistor, electrically connected to the second patterned metal layer and the ground terminal, wherein the filter capacitor and the filter resistor form a low-pass filter.

[0023] Optionally, in the capacitive coupling isolation device as described above, the input bonding pad structure also includes a fourth patterned metal layer and a third dielectric layer, the fourth patterned metal layer is located between the first patterned metal layer and the second patterned metal layer, and the first patterned metal layer, the fourth patterned metal layer and the third dielectric layer located between the first patterned metal layer and the fourth patterned metal layer constitute a pad capacitor, and the first patterned metal layer is electrically connected to the external coupling capacitor.

[0024] Optionally, in the capacitive coupling isolation device as described above, the external coupling capacitor is a built-in package capacitor, which includes a first electrode plate and a second electrode plate, the first electrode plate is electrically connected to a transmitting end circuit, and the second electrode plate is electrically connected to the first patterned metal layer.

[0025] Optionally, in the capacitive coupling isolation device as described above, the receiving end circuit further includes a DC isolation capacitor electrically connected to the second patterned metal layer and a core circuit of the receiving end circuit.

[0026] Optionally, in the capacitive coupling isolation device as described above, the fourth patterned metal layer is connected to the second patterned metal layer through a plurality of first conductive connectors.

[0027] To further understand the features and technical contents of the present application, please refer to the following detailed description and drawings of the present application. However, the drawings provided are only for reference and illustration and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1FIG. 1 is a schematic diagram of a capacitive coupling isolation device according to a first embodiment of the present application.

[0029] Figure 2 FIG. 4 is an equivalent circuit diagram of a capacitive coupling isolation device according to the first embodiment of the present application.

[0030] Figure 3 The figure is a simulation result of the capacitive coupling isolation device according to the first embodiment of the present application.

[0031] Figure 4 FIG. 1 is a schematic diagram of a capacitive coupling isolation device according to a second embodiment of the present application.

[0032] Figure 5 FIG. 4 is an equivalent circuit diagram of a capacitive coupling isolation device according to a second embodiment of the present application.

[0033] Figure 6 The figure is a simulation result of the capacitive coupling isolation device according to the second embodiment of the present application. DETAILED DESCRIPTION

[0034] The following is an explanation of the implementation methods of the "capacitive coupling isolation device and receiving circuit" disclosed in the present application through specific examples. Those skilled in the art can understand the advantages and effects of the present application from the contents disclosed in this specification. The present application can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present application. In addition, the drawings of the present application are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following implementation methods will further explain the relevant technical content of the present application in detail, but the disclosed content is not intended to limit the scope of protection of the present application. In addition, the term "or" used in this article may include any one or more combinations of the associated listed items depending on the actual situation.

[0035] First embodiment

[0036] Figure 1 1 is a schematic diagram of a capacitive coupling isolation device according to a first embodiment of the present application. For ease of understanding and description, the capacitive coupling isolation device according to the present embodiment takes a built-in package capacitive coupling isolation device as an example.

[0037] See also Figure 1As shown, the first embodiment of the present application provides a capacitive coupling isolation device 1, which includes a transmitting component and a receiving component. The transmitting component is, for example, a transmitting integrated circuit chip (TX IC die), which includes a transmitting circuit TX; the receiving component is, for example, a receiving integrated circuit chip (RX IC die), which includes a receiving circuit RX. In addition, the capacitive coupling isolation device 1 also includes an external coupling capacitor Cc coupled between the transmitting component and the receiving component, and a protection circuit architecture (protection circuit architecture, PT). The protection circuit architecture PT is applicable to the receiving circuit RX. Specifically, the protection circuit architecture PT is formed in the receiving circuit RX, which includes an input bonding pad structure IPD and a filter resistor Rf. However, in other embodiments, the protection circuit architecture PT may also include a DC block capacitor (Cdb).

[0038] The external coupling capacitor Cc is a built-in package capacitor, which includes a first electrode plate E1, a second electrode plate E2, and a dielectric layer disposed between the first electrode plate E1 and the second electrode plate E2. For convenience of representation, Figure 1 The dielectric layer is not shown. The first end of the external coupling capacitor Cc (i.e., the first electrode plate E1) can be electrically connected to the transmitting end circuit TX. In some embodiments, the first electrode plate E1 is electrically connected to the transmitting end circuit TX by a first wire W1 by a wire bonding method, and the second electrode plate E2 is electrically connected to the input bonding pad structure IPD by a second wire W2 by a wire bonding method, but the present application is not limited thereto. The present application does not limit the manner in which the first electrode plate E1 is electrically connected to the transmitting end circuit TX, and the manner in which the second electrode plate E2 is electrically connected to the input bonding pad structure IPD.

[0039] Specifically, the input bonding pad of the receiving circuit RX forms an input bonding pad structure IPD, which includes a plurality of patterned metal layers and a plurality of dielectric layers. Figure 1 , for example, patterned metal layers M1, M2, M3 and M4 and dielectric layers D1, D2 and D3 are stacked alternately with each other. Among them, the patterned metal layers M1, M2, M3 and M4 can be made of conductive metal materials, such as copper; the dielectric layers D1, D2 and D3 can be made of non-conductive materials, such as silicon dioxide (SiO2). In the input bonding pad structure IPD, a pad capacitor Cp and a filter capacitor Cf can be further formed. In addition, the input bonding pad structure IPD can be composed of a pad capacitor Cp and a filter capacitor Cf connected in series, but is not limited to this.

[0040] From the circuit relationship point of view, the first end of the pad capacitor Cp can be electrically connected to the second end of the external coupling capacitor Cc (i.e., the second electrode plate E2) through the second wire W2. The filter capacitor Cf is electrically connected to the second end of the pad capacitor Cp and the ground terminal GND. In addition, the filter resistor Rf is also electrically connected to the second end of the pad capacitor Cp and the ground terminal GND, and together with the filter capacitor Cf, forms a low-pass filter.

[0041] In the present embodiment, in order to form the above-mentioned circuit relationship, for example, the patterned metal layers M1, M2 and the dielectric layer D1 disposed between the patterned metal layers M1, M2 are used to form a pad capacitor Cp, and the patterned metal layers M3, M4 and the dielectric layer D3 disposed between the patterned metal layers M3, M4 are used to form a filter capacitor Cf. The patterned metal layer M2 and the patterned metal layer M4 are insulated from each other by the dielectric layer D3, and as for the way in which the pad capacitor Cp is electrically connected to the filter capacitor Cf, in the present embodiment, for example, the patterned metal layer M2 can be connected to the patterned metal layer M3 through a plurality of conductive connectors (e.g., a plurality of conductive through holes), but the present application is not limited thereto. Specifically, the present application does not limit the number and position of the patterned metal layers and dielectric layers used to form the pad capacitor Cp and the filter capacitor Cf, nor does it limit the way in which the pad capacitor Cp is electrically connected to the filter capacitor Cf.

[0042] In addition, the patterned metal layers M1, M2, M3 and M4 can be arranged in a circuit substrate (e.g., an integrated circuit, a printed circuit board), and are respectively located in a plurality of metal layers arranged from top to bottom, for example, respectively located in the first layer (e.g., top layer), the second layer, ..., the N-1 layer (e.g., the fifth layer) and the N layer (e.g., bottom layer) of the circuit substrate, where N is a positive integer. Among them, the metal layers between the second layer and the N-1 layer (e.g., the fifth layer) can be reserved for forming a subsequent DC isolation capacitor Cdb, but this is not limited thereto.

[0043] On the other hand, the input end of the DC isolation capacitor Cdb is electrically connected to the second end of the pad capacitor, and the other end of the DC isolation capacitor Cdb is electrically connected to the core circuit of the receiving end circuit. In short, the DC isolation capacitor Cdb is configured between the second end of the pad capacitor Cp and the core circuit RXc of the receiving end circuit RX. The core circuit RXc may include, for example, a bias circuit 10, a load circuit 12, and a transistor 14, but is not limited thereto. The DC isolation capacitor Cdb may be, for example, disposed in a circuit substrate configured with patterned metal layers M1, M2, M3, and M4, and may be, for example, a Metal-Insulator-Metal (MIM) capacitor, a finger capacitor, or a parallel plate capacitor. In the present embodiment, in order to form the above-mentioned circuit relationship, the DC isolation capacitor Cdb may include patterned metal layers M5 and M6 (used as upper and lower electrodes), and a dielectric layer D4 disposed between the patterned metal layers M5 and M6. When the DC isolation capacitor Cdb is implemented with a MIM capacitor, the MIM capacitor may also include an additional patterned metal layer disposed between the patterned metal layers M5 and M6 to reduce the thickness of the dielectric layer between the upper and lower electrodes and increase the capacitance. In the MIM capacitor, the thickness of the dielectric layer between the patterned metal layers may be less than the thickness from metal layer to metal layer in the circuit substrate, so the MIM capacitor has a larger capacitance per unit area than the flat plate capacitor, but the breakdown voltage is about several volts.

[0044] In the present embodiment, the patterned metal layer M5 may be, for example, disposed in a metal layer (for example, the third layer of the circuit substrate) between a metal layer corresponding to the patterned metal layer M2 (for example, the second layer of the circuit substrate) and a metal layer corresponding to the patterned metal layer M3 (for example, the fifth layer of the circuit substrate); the patterned metal layer M6 may be, for example, disposed in a metal layer (for example, the fourth layer of the circuit substrate) between a metal layer corresponding to the patterned metal layer M2 (for example, the second layer of the circuit substrate) and a metal layer corresponding to the patterned metal layer M3 (for example, the fifth layer of the circuit substrate), or may be disposed in the same metal layer (for example, the fifth layer of the circuit substrate) as the patterned metal layer M3. Therefore, the patterned metal layer M6 may be electrically connected to the patterned metal layer M3 through the patterned circuit T1, and the filter resistor Rf may also be electrically connected to the patterned circuit T1 and the ground terminal GND.

[0045] like Figure 1As shown, an electrostatic discharge (ESD) event may occur during the chip mounting and bonding process, as shown in the position shown by the lightning-shaped pattern. When an ESD event occurs, it may cause damage to the receiving circuit RX. It should be noted that in order to improve the common mode transient immunity (CMTI) performance, the present application does not additionally set an electrostatic discharge (ESD) protection unit (for example, a Zener diode) under the input pad of the receiving circuit RX, but instead designs a protection circuit architecture and applies it to the receiving circuit RX, ultimately forming an off-chip receiving circuit architecture that is resistant to electrostatic discharge.

[0046] Please refer to Figure 2 , Figure 2 FIG. 1 is an equivalent circuit diagram of the capacitive coupling isolation device of the first embodiment of the present application, and for the convenience of description, the equivalent circuit of the transmitting end circuit TX is omitted. Figure 2 In the Figure 1 The equivalent circuit of the external coupling capacitor Cc and the receiving circuit RX (including the protection circuit architecture PT) is shown in FIG. However, taking two channels as an example, the capacitor C1 and the current source I1 can be used as one of the load circuits, and the capacitor C2 and the current source I2 can be used as the other load circuit. Figure 2 As shown, the pad capacitor Cp1 is connected in series with the external coupling capacitor Cc1, and the pad capacitor Cp2 is connected in series with the external coupling capacitor Cc2, which will cause the coupling capacitance to become smaller, but most of the voltage generated in the ESD event will fall on the pad capacitors Cp1 and Cp2.

[0047] Furthermore, the filter resistor Rf1 and the filter capacitor Cf1 together form an RC low-pass filter, and the filter resistor Rf2 and the filter capacitor Cf2 together form another RC low-pass filter, which helps to release the charge generated by the ESD event to the ground terminal GND. The DC isolation capacitors Cdb1 and Cdb2 can filter the input signal into a radio frequency signal without a DC component, and the DC bias is provided by the bias circuits 101 and 102. When the pad capacitors Cp1 / Cp2 and the DC isolation capacitors Cdb1 / Cdb2 work together, it will help to reduce the ESD voltage drop and the ESD voltage duration at the transistors MOS1 and MOS2. Therefore, this embodiment can protect the receiving end circuit RX from being damaged by the ESD event by setting a protection circuit architecture in the receiving end circuit RX without adding an ESD protection unit under the input pad of the receiving end circuit RX.

[0048] Figure 3The ESD simulation results of the mechanical discharge mode (MM) of the capacitive coupling isolation device of the first embodiment of the present application are shown, which shows the voltage at the ESD event location (located at the first end of the pad capacitor Cp), the voltage on the DC isolation capacitor Cdb, and the voltage at the core circuit RXc of the capacitive coupling isolation device 1 using the protection circuit architecture PT of the present embodiment. Figure 3 As shown in FIG. 1 , during the ESD event, the voltage at the ESD event location (located at the first end of the pad capacitor Cp) exceeds 200V, and the maximum voltage is as high as about 340V. After the input pad structure IPD and the filter resistor Rf, most of the charges generated by the ESD event can be released to the ground terminal GND, so Figure 3 It can be seen that the voltage applied to the DC isolation capacitor Cdb (such as a MIM capacitor) has been greatly reduced. Although there is still a certain degree of voltage peak (about 80V), the duration is only about 2ns. Therefore, it can be seen that the DC isolation capacitor Cdb (such as a MIM capacitor) is also protected by electrostatics.

[0049] In addition, the transistor 14 (reference Figure 1 The maximum voltage of the receiving circuit RX of the embodiment is less than 5V, and the duration is only 2ns, so it is obvious that it is protected from electrostatic discharge. In short, it can be seen from the simulation results that a protection circuit architecture PT is provided in the receiving circuit RX of the present embodiment, that is, the receiving circuit RX can be protected from damage by ESD events without additionally providing an ESD protection unit under the input pad of the receiving circuit RX. In other words, compared to the conventional knowledge, during the die bonding and packaging process, the off-chip receiving circuit RX of the present embodiment will not be damaged by ESD events even if no additional ESD protection unit is provided. On the contrary, it is worth mentioning that during the simulation process, if the protection circuit architecture PT of the present embodiment is not provided and no additional ESD protection unit is provided, the receiving circuit will be damaged by the ESD event.

[0050] Second embodiment

[0051] Figure 4 FIG. 1 is a schematic diagram of a capacitive coupling isolation device according to a second embodiment of the present application.

[0052] See also Figure 4 As shown, the second embodiment of the present application provides a capacitive coupling isolation device 2. It should be noted that: Figure 4 The capacitive coupling isolation device 2 is similar to Figure 1 Therefore, the repeated description is omitted and only the differences are described in detail.

[0053] Similarly, the external coupling capacitor Cc is a built-in package capacitor, which includes a first electrode plate E1, a second electrode plate E2, and a dielectric layer disposed between the first electrode plate E1 and the second electrode plate E2. The first end of the external coupling capacitor Cc (i.e., the first electrode plate E1) can be electrically connected to the transmitting end circuit TX. Similarly, the first electrode plate E1 is electrically connected to the transmitting end circuit TX by means of a first wire W1 by means of a wire bonding, and the second electrode plate E2 is electrically connected to the input bonding pad structure IPD by means of a second wire W2 by means of a wire bonding, but the present application is not limited thereto. The present application does not limit the manner in which the first electrode plate E1 is electrically connected to the transmitting end circuit TX, and the manner in which the second electrode plate E2 is electrically connected to the input bonding pad structure IPD.

[0054] Specifically, the input bonding pad of the receiving circuit RX forms an input bonding pad structure IPD', which includes a plurality of patterned metal layers and a plurality of dielectric layers, such as patterned metal layers M7, M8 and M9 and dielectric layers D5 and D6, which are stacked alternately with each other. The patterned metal layers M7, M8 and M9 can be made of conductive metal materials, such as copper. The dielectric layers D5 and D6 can be made of non-conductive materials, such as silicon dioxide (SiO2). Different from the first embodiment, in the input bonding pad structure IPD', the pad capacitor Cp is omitted and only the filter capacitor Cf is provided.

[0055] The patterned metal layer M7 can be electrically connected to the second end (i.e., the second electrode plate E2) of the external coupling capacitor Cc through the second wire W2, and can be connected to the patterned metal layer M8 through a plurality of conductive connectors, such as conductive through holes. The filter capacitor Cf includes patterned metal layers M8, M9 and a dielectric layer D6 disposed between the patterned metal layers M8, M9, the patterned metal layer M8 serving as the first end of the filter capacitor Cf, and the patterned metal layer M9 serving as the second end of the filter capacitor Cf and electrically connected to the ground terminal GND. From a circuit perspective, the filter capacitor Cf is electrically connected to the second end (i.e., the second electrode plate E2) of the external coupling capacitor Cc and the ground terminal GND. In addition, the filter resistor Rf is also electrically connected to the first end (i.e., the patterned metal layer M8) of the filter capacitor Cf and the ground terminal GND, and together with the filter capacitor Cf forms a low-pass filter.

[0056] In the present embodiment, in order to form the above-mentioned circuit relationship, the patterned metal layers M8, M9 and the dielectric layer D6 disposed between the patterned metal layers M8, M9 are used to form the filter capacitor Cf. Regarding the electrical connection method of the external coupling capacitor Cc, the filter capacitor Cf and the filter resistor Rf, for example, in the present embodiment, the patterned metal layer M7 can be connected to the patterned metal layer M8, for example, through a plurality of conductive connectors, such as conductive through holes, and the patterned metal layer M8 can further extend outward from the position where the filter capacitor Cf is disposed, and is connected to the patterned metal layer M10 through a plurality of conductive connectors, such as conductive through holes, and the filter resistor Rf is electrically connected to the patterned metal layer M10, and is electrically connected to the first end of the filter capacitor Cf (i.e., the patterned metal layer M8) and the second end of the external coupling capacitor Cc (i.e., the second electrode plate E2) through the patterned metal layer M10. However, the present application is not limited thereto. Specifically, the present application does not limit the number and position of the patterned metal layers and dielectric layers used to form the filter capacitor Cf, nor does it limit the electrical connection method among the external coupling capacitor Cc, the filter capacitor Cf and the filter resistor Rf.

[0057] In addition, the patterned metal layers M7, M8, M10 and M9 can be set in a circuit substrate (such as an integrated circuit, a printed circuit board), and are respectively located in multiple metal layers arranged from top to bottom, for example, respectively located in the first layer (for example: the top layer), the second layer,..., the N-1 layer (for example: the fifth layer), and the N layer (for example: the bottom layer) of the circuit substrate, wherein the metal layers from the second layer to the N-1 layer (for example: the fifth layer) can be reserved for forming a subsequent DC isolation capacitor C'db, but this is not limited to this.

[0058] On the other hand, the DC isolation capacitor C'db is electrically connected to the second end of the external coupling capacitor Cc and the core circuit RXc of the receiving circuit RX. The core circuit RXc may, for example, include a bias circuit 20, a load circuit 22 and a transistor 24, but is not limited thereto. In addition, unlike the first embodiment, in the second embodiment, the DC isolation capacitor C'db may, for example, be a parallel plate capacitor, which is configured in a circuit substrate provided with patterned metal layers M7, M8, M10 and M9. The DC isolation capacitor C'db may include patterned metal layers M11 and M12, and a dielectric layer D7 disposed between the patterned metal layers M11 and M12. The patterned metal layers M11 and M12 may be located in a portion of the metal layers of the circuit substrate, and may be located between the second to N-1th (e.g., fifth) metal layers of the circuit substrate. In the present embodiment, the patterned metal layers M11 and M12 may be located in the same metal layer of the circuit substrate as the adjacent patterned metal layer M8 (e.g., the second metal layer) and the patterned metal layer M10 (e.g., the third metal layer), but the present application is not limited thereto, and the patterned metal layers M11 and M12 may be located in other two adjacent metal layers. The patterned metal layer M10 may be electrically connected to the patterned metal layer M12 through the patterned circuit T2, and the filter resistor Rf may also be electrically connected to the patterned circuit T2 and the ground terminal GND.

[0059] It should be noted that the DC isolation capacitor C'db in the second embodiment is, for example, a parallel plate capacitor, and its area size is slightly larger than the DC isolation capacitor Cdb (MIM capacitor) in the first embodiment. Moreover, the dielectric layer D7 between the patterned metal layers M11 and M12 of the DC isolation capacitor C'db can be made of silicon dioxide, which has a greater thickness than the dielectric layer of the MIM capacitor. For example, the thickness can be greater than 700nm, so that the breakdown voltage of the DC isolation capacitor C'db can be greater than 500V, which is better than the MIM capacitor. In addition, since the pad capacitor Cp is omitted in this embodiment, the coupling capacitor is larger, and more RF signals are coupled to the core circuit RXc of the receiving IC, so the RF signal is stronger.

[0060] like Figure 4 As shown, an electrostatic discharge (ESD) event may occur during the chip mounting and bonding process, as shown in the position of the lightning-shaped pattern. When an ESD event occurs, the receiving circuit RX may be damaged. It should be noted that in order to improve the common mode transient immunity (CMTI) performance, the present application may not additionally set an electrostatic discharge (ESD) protection unit under the input pad of the receiving circuit RX, but instead designs a protection circuit architecture and applies it to the receiving circuit RX, ultimately forming an off-chip receiving circuit that is resistant to electrostatic discharge.

[0061] Please refer to Figure 5 , Figure 5FIG. 1 is an equivalent circuit diagram of a capacitive coupling isolation device according to the second embodiment of the present application, and for the convenience of explanation, the equivalent circuit of the transmitting end circuit TX is omitted. Figure 5 In the Figure 4 The equivalent circuit of the external coupling capacitor Cc and the receiving circuit RX (including the protection circuit architecture PT) is shown in FIG. However, taking two channels as an example, the capacitor C1 and the current source I1 can be used as one of the load circuits, and the capacitor C2 and the current source I2 can be used as the other load circuit. Figure 5 As shown, the first end of the external coupling capacitor Cc1 is electrically connected to the transmitting end circuit TX, the filter resistor Rf1 is connected in parallel with the filter capacitor Cf1 and together form a low-pass filter, and are both electrically connected to the second end of the external coupling capacitor Cc1 and the ground terminal GND. In addition, the first end of the external coupling capacitor Cc2 is electrically connected to the transmitting end circuit TX, the filter resistor Rf2 and the filter capacitor Cf2 together form another low-pass filter, and are both electrically connected to the second end of the external coupling capacitor Cc2 and the ground terminal GND. The above two low-pass filters help to release most of the charges generated by the ESD event occurring at the input pad of the receiving end circuit RX (i.e., the place coupled to the second electrode plate E2) to the ground terminal GND. The DC isolation capacitors C'db1 and C'db2 can filter the input signal into a radio frequency signal without a DC component, and the DC bias is provided by the bias circuits 201 and 202.

[0062] In detail, when an ESD event occurs, most of the voltage will be applied to the DC isolation capacitors C'db1 and C'db2, and the DC isolation capacitors C'db1 and C'db2 can withstand a voltage of at least 500V, thus helping to reduce the ESD voltage borne by the transistors MOS1 and MOS2 to below 5V. Therefore, the present application can protect the receiving circuit RX from being damaged by the ESD event even without an additional ESD protection unit under the input pad of the receiving circuit RX by providing a protection circuit architecture PT in the receiving circuit RX.

[0063] Figure 6 The electrostatic discharge (ESD) simulation results of the mechanical discharge mode (MM) of the capacitive coupling isolation device of the second embodiment of the present application are shown, which shows the voltage on the DC isolation capacitor C'db and the voltage at the core circuit RXc of the capacitive coupling isolation device 2 using the protection circuit architecture PT of the present embodiment. Figure 6 As shown in FIG. 1 , during the ESD event, the maximum voltage applied to the DC isolation capacitor C'db (plate capacitor) is about 200V, which does not exceed the maximum voltage that the DC isolation capacitor C'db can withstand (at least 500V), while the voltage applied to the transistor 24 (reference) as a preamplifier in the core circuit RXc is about 200V. Figure 4) is less than 5V. Through experiments, it can be known that the protection circuit architecture PT is provided in the receiving end circuit RX of the present embodiment, that is, the receiving end circuit RX can be protected from being damaged by ESD events without additionally providing an ESD protection unit under the input pad of the receiving end circuit RX. In other words, during the die bonding and packaging process, compared with the conventional method, the off-chip receiving end circuit RX of the present embodiment without additionally providing an ESD protection unit will not be damaged by ESD events.

[0064] Advantageous Effects of Embodiments

[0065] One of the beneficial effects of the present application is that in the capacitive coupling isolation device provided in the present application in which a protection circuit architecture is provided in the receiving circuit, the low-pass filter formed by the built-in package capacitor, pad capacitor, filter capacitor and filter resistor and the coordinated operation of the MIM capacitor can protect the receiving circuit from damage by ESD events without additionally providing an ESD protection unit under the input pad of the receiving circuit.

[0066] Furthermore, in another capacitive coupling isolation device provided in the present application in which a protection circuit architecture is set in the receiving circuit, it can protect the receiving circuit from damage by ESD events without additionally setting an ESD protection unit under the input pad of the receiving circuit through the coordinated operation of the built-in package capacitor, the low-pass filter formed by the filter capacitor and the filter resistor, and the high-voltage parallel plate capacitor.

[0067] The contents disclosed above are only preferred feasible embodiments of the present application, and are not intended to limit the protection scope of the claims of the present application. Therefore, all equivalent technical changes made using the contents of the present application specification and drawings are included in the protection scope of the claims of the present application.

Claims

1. A capacitive coupling isolation device, characterized in that: The capacitive coupling isolation device comprises: an external coupling capacitor, one end of which is electrically connected to a transmitting end circuit; and A receiving end circuit is electrically connected to the other end of the external coupling capacitor, and the receiving end circuit includes: A protection circuit architecture, comprising: An input bonding pad structure is formed by alternating a plurality of patterned metal layers and a plurality of dielectric layers, comprising: a pad capacitor, a first end of the pad capacitor being electrically connected to the other end of the external coupling capacitor; and a filter capacitor electrically connected to the second end of the pad capacitor and a ground terminal; and a filter resistor electrically connected to the second end of the pad capacitor and the ground terminal, wherein the filter capacitor and the filter resistor form a low-pass filter; Wherein, the external coupling capacitor is a built-in package capacitor, and the built-in package capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is electrically connected to the transmitting end circuit, and the second electrode plate is electrically connected to the first end of the pad capacitor.

2. The capacitive coupling isolation device according to claim 1, characterized in that: The first electrode plate is electrically connected to the transmitting end circuit through a first wire in a bonding manner, and the second electrode plate is electrically connected to the first end of the pad capacitor through a second wire in a bonding manner.

3. The capacitive coupling isolation device according to claim 1, characterized in that: The patterned metal layer at least includes a first patterned metal layer, a second patterned metal layer, a third patterned metal layer and a fourth patterned metal layer, the dielectric layer at least includes a first dielectric layer arranged between the first patterned metal layer and the second patterned metal layer, a second dielectric layer between the second patterned metal layer and the third patterned metal layer, and a third dielectric layer arranged between the third patterned metal layer and the fourth patterned metal layer, the first patterned metal layer, the first dielectric layer and the second patterned metal layer are used to form the pad capacitor, and the third patterned metal layer, the third dielectric layer and the fourth patterned metal layer are used to form the filter capacitor.

4. The capacitive coupling isolation device according to claim 3, characterized in that: The second patterned metal layer is connected to the third patterned metal layer through a plurality of conductive connectors.

5. The capacitive coupling isolation device according to claim 4, characterized in that: The first patterned metal layer, the second patterned metal layer, the third patterned metal layer and the fourth patterned metal layer are arranged in a circuit substrate, and are respectively located in a first metal layer, a second metal layer, an N-1th metal layer and an Nth metal layer arranged from top to bottom of the circuit substrate, where N is a positive integer.

6. The capacitive coupling isolation device according to claim 5, characterized in that: The capacitive coupling isolation device further includes a DC isolation capacitor electrically connected to the second end of the pad capacitor and a core circuit of the receiving end circuit.

7. The capacitive coupling isolation device according to claim 6, characterized in that: The DC isolation capacitor is a Metal-Insulator-Metal (MIM) capacitor.

8. The capacitive coupling isolation device according to claim 7, characterized in that: The metal-insulator-metal capacitor is disposed in the circuit substrate and includes a fifth patterned metal layer and a sixth patterned metal layer.

9. The capacitive coupling isolation device according to claim 8, characterized in that: The fifth patterned metal layer is located in a third metal layer of the circuit substrate, and the sixth patterned metal layer is located in a fourth metal layer or the N-1th metal layer of the circuit substrate.

10. A capacitive coupling isolation device, characterized in that: The capacitive coupling isolation device comprises: an external coupling capacitor, wherein a first end of the external coupling capacitor is electrically connected to a transmitting end circuit; and A receiving end circuit is electrically connected to the second end of the external coupling capacitor, and the receiving end circuit includes: A protection circuit architecture, comprising: An input bonding pad structure, formed by staggered patterned metal layers and dielectric layers, the input bonding pad structure comprising a filter capacitor, electrically connected to the second end of the external coupling capacitor and a ground end; a filter resistor electrically connected to the second end of the external coupling capacitor and the ground end, wherein the filter capacitor and the filter resistor form a low-pass filter; and A DC isolation capacitor is electrically connected to the second end of the external coupling capacitor and a core circuit of the receiving end circuit.

11. The capacitive coupling isolation device according to claim 10, characterized in that: The patterned metal layer of the input bonding pad structure includes at least a first patterned metal layer, a second patterned metal layer and a third patterned metal layer, and the dielectric layer includes at least a first dielectric layer arranged between the first patterned metal layer and the second patterned metal layer, and a second dielectric layer arranged between the second patterned metal layer and the third patterned metal layer, and the second patterned metal layer, the second dielectric layer and the third patterned metal layer are used to form the filter capacitor.

12. The capacitive coupling isolation device according to claim 11, characterized in that: The first patterned metal layer is connected to the second patterned metal layer through a plurality of first conductive connectors.

13. The capacitive coupling isolation device according to claim 11, characterized in that: The patterned metal layer of the input bonding pad structure also includes a fourth patterned metal layer, and the dielectric layer also includes a third dielectric layer. The fourth patterned metal layer is located between the first patterned metal layer and the second patterned metal layer, and the first patterned metal layer, the fourth patterned metal layer and the third dielectric layer located between the first patterned metal layer and the fourth patterned metal layer constitute a pad capacitor, and the first patterned metal layer is electrically connected to the second end of the external coupling capacitor.

14. The capacitive coupling isolation device according to claim 11, characterized in that: The external coupling capacitor is a built-in package capacitor, which includes a first electrode plate and a second electrode plate, the first electrode plate is electrically connected to the transmitting end circuit, and the second electrode plate is electrically connected to the first patterned metal layer.

15. The capacitive coupling isolation device according to claim 11 or 13, characterized in that: The DC isolation capacitor is a finger capacitor, a parallel plate capacitor or a MIM capacitor, and at least includes a fifth patterned metal layer, a fourth dielectric layer and a sixth patterned metal layer, wherein the fourth dielectric layer is located between the fifth patterned metal layer and the sixth patterned metal layer.

16. The capacitive coupling isolation device according to claim 15, characterized in that: The patterned metal layer is disposed in a circuit substrate, and the sixth patterned metal layer of the DC isolation capacitor is electrically connected to the filter capacitor through a patterned circuit.

17. A receiving end circuit, characterized in that: The receiving end circuit is applicable to an isolation device, and the receiving end circuit comprises: A protection circuit architecture, comprising: an input bonding pad structure, comprising at least a first patterned metal layer, a second patterned metal layer, a first dielectric layer between the first patterned metal layer and the second patterned metal layer, a third patterned metal layer, and a second dielectric layer between the second patterned metal layer and the third patterned metal layer, wherein the second patterned metal layer, the second dielectric layer, and the third patterned metal layer constitute a filter capacitor, one end of the filter capacitor is electrically connected to an external coupling capacitor through the first patterned metal layer, and the other end of the filter capacitor is electrically connected to a ground terminal; and A filter resistor is electrically connected to the second patterned metal layer and the ground terminal, wherein the filter capacitor and the filter resistor form a low-pass filter.

18. The receiving end circuit according to claim 17, characterized in that: The input bonding pad structure also includes a fourth patterned metal layer and a third dielectric layer, the fourth patterned metal layer is located between the first patterned metal layer and the second patterned metal layer, and the first patterned metal layer, the fourth patterned metal layer and the third dielectric layer located between the first patterned metal layer and the fourth patterned metal layer constitute a pad capacitor, and the first patterned metal layer is electrically connected to the external coupling capacitor.

19. The receiving end circuit according to claim 17, characterized in that: The external coupling capacitor is a built-in package capacitor, which includes a first electrode plate and a second electrode plate, the first electrode plate is electrically connected to a transmitting end circuit, and the second electrode plate is electrically connected to the first patterned metal layer.

20. The receiving end circuit according to claim 17, characterized in that: The receiving end circuit also includes a DC isolation capacitor electrically connected to the second patterned metal layer and a core circuit of the receiving end circuit.

21. The receiving end circuit according to claim 18, characterized in that: The fourth patterned metal layer is connected to the second patterned metal layer through a plurality of first conductive connecting members.

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