Waveform generation system and method, and storage medium

Abstract

The invention discloses a waveform generation system and method and a storage medium, and the system comprises a programmable gate array, a sampling and holding module and a differential digital-to-analog conversion module, and the programmable gate array is connected with the differential digital-to-analog conversion module and the sampling and holding module. The output end of the differential digital-to-analog conversion module is connected with the input end of the sampling and holding module; the programmable gate array is used for controlling the sampling and holding module to switch working modes, and the working modes comprise holding and sampling; and the programmable gate array is also used for controlling the differential digital-to-analog conversion module to carry out digital-to-analog conversion and outputting a waveform under the condition that the sampling and holding module is in a holding state. According to the scheme provided by the invention, in the process of generating the waveform based on the digital signal, the situation that the output waveform is in a transient state due to voltage switching for controlling digital-to-analog conversion, and more irregular harmonics with higher amplitude are generated can be avoided, so that the high-quality waveform can be generated.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a waveform generation system, method and storage medium. Background Art

[0002] When testing low-speed analog-to-digital converters or audio devices, high-quality waveform signals are usually required.

[0003] In the related technical solutions, a digital-to-analog conversion network is usually constructed based on a binary weighted current generator or a resistor network, and the digital-to-analog conversion is performed based on the amplitude codeword output by the codeword generator through the above network to obtain an output waveform signal.

[0004] However, the waveform generated by the solution in the related art often has transients at the moment of digital-to-analog conversion (i.e. when the amplitude codeword is converted into voltage), generating irregular harmonic spurs. This transient is difficult to filter out through a filter, resulting in low quality of the generated waveform. Summary of the invention

[0005] The present application provides a waveform generation system, method and storage medium, the purpose of which is to eliminate the transient state of the output waveform caused by voltage changes when controlling digital-to-analog conversion, thereby obtaining a high-quality output waveform.

[0006] To achieve the above objectives, on the one hand, the present application provides a waveform generation system, the system comprising:

[0007] A programmable gate array, a sampling and holding module and a differential digital-to-analog conversion module, wherein the programmable gate array is connected to the differential digital-to-analog conversion module and the sampling and holding module, and an output end of the differential digital-to-analog conversion module is connected to an input end of the sampling and holding module;

[0008] The programmable gate array is used to control the sample and hold module to switch the working mode, and the working mode includes holding and sampling;

[0009] The programmable gate array is also used to control the differential digital-to-analog conversion module to perform digital-to-analog conversion and output a waveform when the sampling and holding module is in the holding state.

[0010] As a further improvement of the present application, the programmable gate array includes a timing unit and a control unit;

[0011] The timing unit is used to send a timing pulse;

[0012] The control unit is used to send a conversion control signal to the differential digital-to-analog conversion module when receiving the timing pulse, wherein the conversion control signal is used to instruct the differential digital-to-analog conversion module to perform digital-to-analog conversion;

[0013] The control unit is further configured to send a working mode control signal to the sampling and holding module when receiving the timing pulse.

[0014] As a further improvement of the present application, the differential digital-to-analog conversion module includes a first digital-to-analog conversion unit and a second digital-to-analog conversion unit;

[0015] The control unit is further configured to send a first conversion control signal to the first digital-to-analog conversion unit, and send a second conversion control signal to the second digital-to-analog conversion unit;

[0016] The first digital-to-analog conversion unit is configured to perform digital-to-analog conversion upon receiving the first conversion control signal;

[0017] The second digital-to-analog conversion unit is used to perform digital-to-analog conversion when receiving the second conversion control signal.

[0018] As a further improvement of the present application, the sampling and holding module includes a first sampling and holding unit and a second sampling and holding unit, the first sampling and holding unit is connected to the first digital-to-analog conversion unit, the second sampling and holding unit is connected to the second digital-to-analog conversion unit, and the initial working modes of the first sampling and holding unit and the second sampling and holding unit are different;

[0019] The control unit is used to control the first sampling and holding unit to switch to holding when receiving the timing pulse;

[0020] The control unit is further configured to control the second sampling and holding unit to switch to sampling after waiting for a first working time when the timing pulse is received.

[0021] As a further improvement of the present application, the control unit is further used to control the first sampling and holding unit to switch to sampling when the first sampling and holding unit is in a state of holding for a second working time;

[0022] The control unit is further configured to control the second sampling and holding unit to switch to holding when the sampling of the second sampling and holding unit reaches a third working time;

[0023] The second working time is greater than the third working time, and the difference between the second working time and the third working time is twice the first working time.

[0024] As a further improvement of the present application, the programmable gate array further includes a codeword generating unit and an inverse code unit, and the inverse code unit is connected to an output terminal of the codeword generating unit;

[0025] The codeword generating unit is configured to send the codeword to the first digital-to-analog conversion unit when the timing pulse is received, and to send the codeword to the inverse code unit when the timing pulse is received;

[0026] The inverse code unit is used to generate an inverse code word based on the code word, and send the inverse code word to the second digital-to-analog conversion unit.

[0027] As a further improvement of the present application, the system further includes a filtering module, which is connected to the sampling and holding module, and is used to filter the output waveform to obtain a filtered output waveform.

[0028] On the other hand, the present application provides a waveform generation method, the method comprising:

[0029] When the first timing duration reaches the first timing period, generating a code word;

[0030] Performing digital-to-analog conversion based on the codeword to obtain an original waveform;

[0031] When the first timing period is reached, obtaining the hold voltage of the original waveform at the most recent sampling moment before the digital-to-analog conversion is performed, and when in the hold phase, maintaining the hold voltage as the output amplitude at the sampling moment, wherein when the digital-to-analog conversion is performed, it is in the hold phase;

[0032] In the case of being in the sampling stage, outputting the original waveform at the sampling time to obtain the output amplitude;

[0033] An output waveform is generated based on the output amplitude.

[0034] As a further improvement of the present application, performing digital-to-analog conversion based on the codeword to obtain an original waveform includes:

[0035] When the timing duration reaches the first timing period, the code word is inverted to obtain an inverted code word;

[0036] Determining whether the most recent digital-to-analog conversion was performed based on the inverse codeword;

[0037] If yes, performing digital-to-analog conversion based on the codeword to obtain a first original waveform;

[0038] If not, digital-to-analog conversion is performed based on the inverse codeword to obtain a second original waveform.

[0039] As a further improvement of the present application, when the first timing period is reached, obtaining the hold voltage collected at the most recent sampling moment before the digital-to-analog conversion is performed includes:

[0040] In the case of being in the first holding stage, obtaining a first holding voltage of the first original waveform at the most recent sampling moment before performing the digital-to-analog conversion;

[0041] In the case of being in the second holding stage, obtaining a second holding voltage of the second original waveform at the most recent sampling moment before performing the digital-to-analog conversion;

[0042] In the case of being in the sampling stage, the original waveform is output at the sampling time to obtain the output amplitude, including:

[0043] In the case of being in the first sampling stage, outputting the first original waveform at the sampling moment, and taking the first original waveform at the sampling moment as the first output amplitude;

[0044] In the case of being in the second sampling stage, the second original waveform is output at the sampling moment, and the second original waveform at the sampling moment is used as the second output amplitude.

[0045] As a further improvement of the present application, the method further includes:

[0046] When the timing duration reaches the first timing period and is in the second holding stage, the first holding stage begins;

[0047] When the first holding phase starts for a period of time that reaches a second timing period, starting the second sampling phase;

[0048] When the timing duration reaches the first timing period and is in the first holding stage, the second holding stage begins;

[0049] When the start time of the second holding phase reaches the second timing time, the second sampling phase starts.

[0050] As a further improvement of the present application, when the codeword is obtained, the codeword is added to the tail of the first codeword queue;

[0051] When the inverted codeword is obtained, the inverted codeword is added to the tail of the second codeword queue;

[0052] Before performing digital-to-analog conversion based on the codeword, reading the codeword from the head of the first codeword queue;

[0053] Before performing digital-to-analog conversion based on the inverted codeword, the inverted codeword is read from the head of the second codeword queue.

[0054] On the other hand, the present application provides a storage medium having a computer program stored thereon, and when the computer program is executed by a processor, a humidity control method as described in any one of the above-mentioned waveform generation methods is executed.

[0055] The solution provided by the embodiment of the present application has at least the following beneficial effects: in the waveform generation system, the programmable gate array is based on the connection relationship between the differential digital-to-analog conversion module and the sampling and holding module, so that when the working mode of the sampling and holding module is hold, the differential digital-to-analog conversion module is controlled to perform digital-to-analog conversion, thereby avoiding the transient state of the output waveform when the amplitude codeword is converted into a voltage, avoiding the generation of more irregular harmonic spurs, and being able to reduce the harmonic amplitude, thereby improving the quality of the output waveform. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A schematic diagram of a waveform generation system provided by an exemplary embodiment of the present application is shown;

[0057] Figure 2 A schematic diagram of a programmable gate array provided by an exemplary embodiment of the present application is shown;

[0058] Figure 3 A schematic diagram of a waveform generation system provided by an exemplary embodiment of the present application is shown;

[0059] Figure 4 shows a waveform timing diagram provided by an exemplary embodiment of the present application;

[0060] Figure 5 A flowchart of a waveform generation method provided by an exemplary embodiment of the present application is shown;

[0061] Figure 6 A schematic diagram showing a sampling phase and a holding phase provided by an exemplary embodiment of the present application is shown;

[0062] Figure 7 A sine wave frequency domain comparison diagram provided by an exemplary embodiment of the present application is shown;

[0063] Figure 8 A comparison chart of THD+N test results provided by an exemplary embodiment of the present application is shown;

[0064] Fig. 9 A flow chart of a waveform generating method provided by another exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0065] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0066] Please refer to Figure 1 , which shows a schematic diagram of a waveform generation system provided by an exemplary embodiment of the present application, wherein the waveform generation system 100 includes a programmable gate array 110, a differential digital-to-analog conversion module 120 and a sampling and holding module 130.

[0067] In the figure, a programmable gate array (FPGA) 110 is connected to a differential digital-to-analog conversion module 120 and a sampling and holding module 130, respectively, and the programmable gate array 110 sends control signals to the differential digital-to-analog conversion module 120 and the sampling and holding module 130 through the connection. The output end of the differential digital-to-analog conversion module 120 is connected to the input end of the sampling and holding module 130, and the original waveform obtained after the differential digital-to-analog conversion module 120 performs digital-to-analog conversion based on the codeword is transmitted to the sampling and holding module 130, and the sampling and holding module 130 samples and holds the output of the differential digital-to-analog conversion module 120 based on the current working mode to obtain an output waveform.

[0068] The programmable gate array 110 is used to control the sampling and holding module to switch the working mode. When the working mode of the sampling and holding module 130 needs to be switched, the programmable gate array 110 sends a working mode control signal to the sampling and holding module 130, and the sampling and holding module 130 switches the working mode in response to the working mode control signal.

[0069] The sampling and holding module 130 has two working modes, namely sampling and holding. In the sampling state, the sampling and holding module 130 outputs the original waveform output by the digital-to-analog conversion module 120 to obtain an output waveform; in the holding state, the sampling and holding module 130 will maintain the waveform before switching to holding for output, and continue to output the held voltage in the holding state, thereby obtaining an output waveform based on the held voltage.

[0070] The programmable gate array 110 is also used to control the differential digital-to-analog conversion module 120 to perform digital-to-analog conversion when the sampling and holding module 130 is in the holding state. In the process of controlling the differential digital-to-analog conversion module 120 to perform digital-to-analog conversion, the programmable gate array 110 sends a conversion control signal to the differential digital-to-analog conversion module 120, and the differential digital-to-analog conversion module 120 performs digital-to-analog conversion based on the received codeword when receiving the conversion control signal.

[0071] Optionally, the programmable gate array 110 may be configured using a standard hardware description language such as Verilog or VHDL (Very-High-speed integrated circuit hardware Description Language).

[0072] In the waveform generation system provided in the embodiment of the present application, the programmable gate array is based on the connection relationship between the differential digital-to-analog conversion module and the sampling and holding module, so that when the working mode of the sampling and holding module is hold, the differential digital-to-analog conversion module is controlled to perform digital-to-analog conversion, thereby avoiding the transient state of the output waveform when the amplitude codeword is converted into a voltage, avoiding the generation of more irregular harmonic spurs, and being able to reduce the harmonic amplitude, thereby improving the quality of the output waveform.

[0073] Please refer to Figure 2 , which shows a schematic diagram of a programmable gate array provided by an exemplary embodiment of the present application, wherein the programmable gate array 200 includes a timing unit 201, a control unit 202 and a codeword generating unit 203.

[0074] The timing unit 201 is used to send timing pulses. After the waveform generation system starts to work, the timing unit sends timing pulses to the control unit 202 and the codeword generation unit 203 at a certain frequency.

[0075] Optionally, the timing unit is a timer, which generates timing pulses at a frequency of 1Mhz or 1Khz.

[0076] When the codeword generating unit 203 receives the timing pulse, the codeword generating unit 203 sends the codeword, so that the differential digital-to-analog conversion module performs digital-to-analog conversion based on the codeword.

[0077] The control unit 202 is used to send a conversion control signal to the differential conversion module A when receiving the timing pulse, wherein the conversion control signal is used to instruct the differential digital-to-analog conversion module A to perform digital-to-analog conversion. In addition, in order to ensure that a transient waveform with large fluctuations is not output at the moment of digital-to-analog conversion, the control unit 202 is used to send a working mode control signal to the sampling and holding module B when receiving the timing pulse, so that the sampling and holding module switches the working mode.

[0078] Optionally, the operating mode control signal sent by the control unit 202 to the sampling and holding module B is used to instruct the operating mode of the sampling and holding module B to switch to holding. Then, when the differential digital-to-analog conversion module A receives the codeword sent by the codeword generation unit 203 and receives the conversion control signal sent by the control unit 202, it can perform digital-to-analog conversion based on the codeword.

[0079] In an embodiment of the present application, the control unit is configured to control the conversion moment of the differential digital-to-analog conversion module and the working mode switching moment of the sampling and holding module, so as to ensure that the differential digital-to-analog conversion module can perform digital-to-analog conversion while keeping the sampling module in a holding state, thereby avoiding the occurrence of transient waveforms with large fluctuations.

[0080] Please refer to Figure 3 , which shows a schematic diagram of a waveform generation system provided by an exemplary embodiment of the present application. The waveform generation system 300 includes a programmable gate array 310, a differential digital-to-analog conversion module 320, a sampling and holding module 330, and a filtering module 340.

[0081] The programmable gate array 310 includes a timing unit 311, a control unit 312, a codeword generating unit 313 and an inverting unit 314. The differential digital-to-analog conversion module 320 includes a first digital-to-analog conversion unit 321 and a second digital-to-analog conversion unit 322.

[0082] like Figure 3 As shown, one output end of the codeword generating unit 313 is connected to the input end of the first digital-to-analog conversion unit 321, and the other output end of the codeword generating unit 313 is connected to the input end of the inverting unit 314, and the output end of the inverting unit 314 is connected to the input end of the first digital-to-analog conversion unit 321. In addition, the control unit 312 is respectively connected to the first digital-to-analog conversion unit 321 and the second digital-to-analog conversion unit 322, and is used to send conversion control signals to the first digital-to-analog conversion unit 321 and the second digital-to-analog conversion unit 322 respectively.

[0083] The control unit 312 is used to send a first conversion control signal to the first digital-to-analog conversion unit 321 , and to send a second conversion control signal to the second digital-to-analog conversion unit 322 .

[0084] Optionally, after the control unit 312 sends the first conversion control signal to the first digital-to-analog conversion unit 321, the first digital-to-analog conversion unit 321 performs digital-to-analog conversion in response to receiving the first conversion control signal. After the control unit 312 sends the second conversion control signal to the second digital-to-analog conversion unit 322, the second digital-to-analog conversion unit 322 performs digital-to-analog conversion in response to receiving the second conversion control signal.

[0085] In some embodiments, when a waveform is generated based on DAC (Digital to Analog Conver), the higher the DAC conversion rate, the worse the performance, and the worse the quality of the waveform finally generated. Therefore, in an embodiment of the present application, in order to reduce the conversion rate of the differential DAC, the control unit 312 can be used to send a control signal to the first digital-to-analog conversion unit 321 and the second digital-to-analog conversion unit 322, thereby reducing the digital-to-analog conversion frequency of a single digital-to-analog conversion unit in the differential digital-to-analog conversion module 320 and improving the DAC performance.

[0086] In one possible implementation, when receiving a timing pulse, the control unit 312 determines whether the most recently sent conversion control signal is the first conversion control signal. If so, it sends the second conversion control signal to the second digital-to-analog conversion unit 322; if not, it sends the first conversion control signal to the first digital-to-analog conversion unit 321.

[0087] Optionally, when receiving a timing pulse, the control unit 312 determines whether the most recently sent conversion control signal is the second conversion control signal. If so, it sends the first conversion control signal to the first digital-to-analog conversion unit 321; if not, it sends the second conversion control signal to the second digital-to-analog conversion unit 322.

[0088] It can be understood that the control unit 312 in the embodiment of the present application can also determine the sending object of the conversion control signal that was most recently sent when receiving the timing pulse. When the sending object is the first digital-to-analog conversion unit 321, the second conversion control signal is sent to the second digital-to-analog conversion unit 322. When the sending object is the second digital-to-analog conversion unit 322, the first conversion control signal is sent to the first digital-to-analog conversion unit.

[0089] Based on the above embodiment, when the control unit 312 receives the timing pulse, it sends control signals alternately to the first digital-to-analog conversion unit 321 and the second digital-to-analog conversion unit 322, that is, in two timing pulse transmission cycles, it controls the first digital-to-analog conversion unit 321 and the second digital-to-analog conversion unit 322 to perform a digital-to-analog conversion respectively, and reduces the conversion frequency of a single digital-to-analog conversion unit to half of the original frequency, thereby effectively reducing the digital-to-analog conversion frequency of a single digital-to-analog conversion unit, improving the conversion performance, and facilitating obtaining a higher quality output waveform.

[0090] In one possible implementation, the differential digital-to-analog conversion module 320 includes an internal register (not shown in the figure). When a codeword is received, the differential digital-to-analog conversion module 320 stores the codeword in the internal register, and when a conversion control signal is received from the programmable gate array 310, the codeword is read from the internal register, and digital-to-analog conversion is performed based on the codeword to obtain the original waveform.

[0091] Optionally, the first digital-to-analog conversion unit 321 includes a codeword register, and the second digital-to-analog conversion unit 322 includes an inverse code register. Then, when the first digital-to-analog conversion unit 321 receives a codeword, it temporarily stores the received codeword in the codeword register, and when it receives a first conversion control signal sent by the control unit 312, it reads the codeword from the codeword register, and performs digital-to-analog conversion based on the codeword to obtain a first original waveform; then, when the second digital-to-analog conversion unit 322 receives an inverse codeword, it temporarily stores the received inverse codeword in the inverse code register, and when it receives a second conversion control signal sent by the control unit 312, it reads the inverse codeword from the inverse code register, and then performs digital-to-analog conversion to obtain a second original waveform.

[0092] like Figure 3 As shown, the sampling and holding module 330 includes a first sampling and holding unit 331 and a second sampling and holding unit 332, wherein the first sampling and holding unit 331 is connected to the output end of the first digital-to-analog conversion unit 321, and the second sampling and holding unit 332 is connected to the output end of the second digital-to-analog conversion unit 322.

[0093] The control unit 312 is connected to the first sampling and holding unit 331 and the second sampling and holding unit 332 and is used to send a working mode control signal to the first sampling and holding unit 331 and the second sampling and holding unit 332 . The working mode control signal is used to control the working mode of the corresponding sampling and holding unit.

[0094] In some embodiments, noise is inevitably generated in the process of switching the working mode of the sampling and holding unit. In order to avoid the first sampling and holding unit 331 and the second sampling and holding unit 332 from interfering with each other when the working mode is switched at the same time, that is, inter-channel interference, the first sampling and holding unit 331 and the second sampling and holding unit 332 can be controlled to switch the working mode at different times.

[0095] Optionally, the control unit 312 controls the first sampling and holding unit 331 to switch to holding when receiving a timing pulse, and controls the second sampling and holding unit 332 to switch to sampling after waiting for a first working time when receiving a timing pulse.

[0096] The first digital-to-analog conversion unit 321 performs digital-to-analog conversion within the holding period of the first sampling and holding unit 331 , and the second digital-to-analog conversion unit 322 performs digital-to-analog conversion within the holding period of the second sampling and holding unit 332 .

[0097] Furthermore, since the first digital-to-analog conversion unit 321 and the second digital-to-analog conversion unit 322 perform digital-to-analog conversion alternately, and the digital-to-analog conversion needs to be performed when the corresponding sampling and holding unit is in the holding working mode, the sampling and holding unit needs to restore the sampling working mode after the output waveform of the corresponding digital-to-analog conversion unit stabilizes, and directly use the original waveform on the channel as the output waveform.

[0098] Optionally, when the first sampling and holding unit 331 is in the holding state for a second working time, the control unit controls the first sampling and holding unit 331 to switch to sampling, and when the second sampling and holding unit 332 is in the sampling state for a third working time, controls the second sampling and holding unit to switch to holding.

[0099] Optionally, the second working time is longer than the third working time, and the difference between the second working time and the third working time is twice the first working time. That is, the first sampling and holding unit 331 and the second sampling and holding unit 332 are in the holding working time for a longer time than the time they are in the sampling time. This is because, on the one hand, it is necessary to avoid the first sampling and holding unit 331 and the second sampling and holding unit 332 from switching the working mode at the same time, and reduce the noise in the circuit by switching the working mode of the sampling and holding units in the two channels in a time-sharing manner; on the other hand, the second sampling and holding unit 332 switches the working mode when the first sampling and holding unit 331 is in the holding state, so as to prevent the second sampling and holding unit from switching the working mode to affect the back-end circuit of the channel where the first sampling and holding unit is located, affect the waveform generated by the back-end circuit, and prevent interference between channels. Similarly, the first sampling and holding unit 331 switches the working mode when the second sampling and holding unit 332 is in the holding state.

[0100] like Figure 3 As shown in the figure, the control unit 312 controls the sampling and holding unit to switch the working state by controlling the switch in the sampling and holding unit. When the control unit sends a control signal of "0", that is, a low level, the circuit is turned on and the sampling and holding unit is in a sampling working mode. When the control unit sends a signal of "1", that is, a high level, the circuit is disconnected and the sampling and holding unit is in a holding working mode.

[0101] For example, when the control unit 312 controls the digital-to-analog conversion unit to perform digital-to-analog conversion, the conversion control signal sent is "0", indicating that the digital-to-analog conversion unit is controlled to perform digital-to-analog conversion. Then, when the control unit sends the conversion control signal as "0", it is necessary to ensure that the sent working mode control signal is "1".

[0102] like Figure 3 As shown, the waveform generation system 300 further includes a filtering module 340, which is connected to the output end of the sampling and holding module. The filtering module 340 is used to filter the output waveform to obtain a filtered output waveform.

[0103] Optionally, in the output waveform obtained by the sampling and holding module 330, a tiny waveform may be introduced when the working mode is switched. This fluctuation can be filtered out by the filtering module 340 to obtain a filtered high-quality output waveform.

[0104] Please refer to Figure 4, which shows a waveform timing diagram provided by an exemplary embodiment of the present application. Among them, TIMEPULSE is a timing pulse generated by a timing unit in a programmable gate array, DIGTAL DAC_P INPUT is a codeword sent by a codeword generating unit in a programmable gate array, DAC_P LOAD is a first conversion control signal sent by a control unit in a programmable gate array to a first digital-to-analog conversion unit, DIGITAL DAC_N INPU is an inverted codeword generated by an inverted code unit in a programmable gate array based on the codeword, DAC_N LOAD is a second conversion control signal sent by a control unit to a second digital-to-analog conversion unit, DAC_P OUTPUT is a first original waveform output by the first digital-to-analog conversion unit, DAC_N OUTPUT is a second original waveform output by the second digital-to-analog conversion unit, S&H_P CONTROL is a first operating mode control signal for controlling an operating mode of a first sampling and holding unit in a sampling and holding module, S&H_N CONTROL is a second operating mode control signal for controlling an operating mode of a second sampling and holding unit in a sampling and holding module, S&H_P OUTPUT is a first output waveform of the first sampling and holding unit, and S&H_N OUTPUT is a second output waveform of the second sampling and holding unit. WAVE_P ANALOG OUTPUT and WAVE_NANALOG OUTPUT are the first output waveform and the second output waveform respectively after filtering. Among them, every time a pulse signal is generated in TIMEPULSE, a code word is generated, and an inverse code word is generated accordingly. DAC_P LOAD and DAC_N LOAD alternately generate effective low-level pulse signals, that is, alternately generate the first conversion control signal and the second conversion control signal. It can be seen from the figure that when DAC_P LOAD is valid, the DAC_P OUTPUT waveform generates a transient waveform, and when DAC_N LOAD is valid, the DAC_N OUTPUT generates a transient waveform. Among them, t 1 The first working time.

[0105] As shown in the figure, when S&H_N CONTROL is '0', S&H_P CONTROL is '1', which is in the hold mode; when S&H_P CONTROL is '0', S&H_N CONTROL is '1'. In addition, both S&H_P CONTROL and S&H_N CONTROL are in the hold period. 1The overlap of the time periods can avoid the simultaneous switching of the first sampling and holding unit and the second sampling and holding unit. As can be seen from the figure, after the original waveform is sampled and held by the sampling and holding module, only a small fluctuation will be generated at the moment of digital-to-analog conversion. After filtering through the filter, the fluctuation is filtered out to obtain high-quality output waveforms WAVE_P ANALOG OUTPUT and WAVE_N ANALOG OUTPUT.

[0106] Please refer to Figure 5 , which shows a flowchart of a waveform generation method provided by an exemplary embodiment of the present application, the method can be executed by a processor, and the method includes the following steps:

[0107] Step S1, generating a code word when a first timing duration reaches a first timing period.

[0108] The length of the first timing period is related to the frequency of digital-to-analog conversion. Optionally, the first timing period is negatively correlated with the digital-to-analog conversion frequency, that is, the higher the required conversion frequency, the shorter the corresponding first timing period.

[0109] Step S2, performing digital-to-analog conversion based on the codeword to obtain an original waveform.

[0110] In a possible implementation, a differential digital-to-analog conversion circuit is used to perform digital-to-analog conversion based on a codeword. The differential digital-to-analog conversion circuit includes two channels. When the timing duration reaches the first timing period, the generated codeword needs to be inverted to obtain an inverted codeword. The codeword and the inverted codeword are respectively input into different channels in the differential digital-to-analog conversion circuit.

[0111] Optionally, when using a differential digital-to-analog conversion circuit for digital-to-analog conversion, since the higher the conversion frequency, the worse the conversion performance, the two channels of the differential digital-to-analog conversion circuit are used for alternating conversion, thereby reducing the digital-to-analog conversion frequency of a single channel, thereby achieving the purpose of improving the conversion performance and ensuring the quality of the output waveform.

[0112] Therefore, when the timing duration reaches the first timing period, the processor determines whether the most recent digital-to-analog conversion is based on the inverse codeword. If so, the digital-to-analog conversion is performed based on the codeword to obtain the first original waveform; if not, the digital-to-analog conversion is performed based on the inverse codeword to obtain the second original waveform.

[0113] Optionally, when the timing duration reaches the first timing period, the processor determines whether the most recent digital-to-analog conversion is based on the codeword. If so, digital-to-analog conversion is performed based on the inverse codeword to obtain the second original waveform; if not, digital-to-analog conversion is performed based on the codeword to obtain the first original waveform.

[0114] In another possible implementation, dual channels are used to alternately perform digital-to-analog conversion. Since digital-to-analog conversion is performed only when the timing duration reaches the first timing period, different queues are provided for temporarily storing the generated codewords and inverse codewords.

[0115] Optionally, for the first digital-to-analog conversion channel, when a codeword is obtained, the processor adds the codeword to the tail of the first codeword queue, and when the timing duration reaches the first timing period, that is, before performing digital-to-analog conversion based on the codeword, the codeword is first read from the head of the first codeword queue, and then digital-to-analog conversion is performed to obtain the first original waveform. Similarly, when an inverse codeword is obtained, the inverse codeword is added to the tail of the second codeword queue, and before performing digital-to-analog conversion based on the inverse codeword, the inverse codeword is read from the head of the second codeword queue, and then digital-to-analog conversion is performed to obtain the second original waveform.

[0116] Step S3, when the first timing period is reached, the holding voltage of the original waveform at the most recent sampling moment before the digital-to-analog conversion is performed is obtained, and when in the holding stage, the holding voltage is used as the output amplitude at the sampling moment.

[0117] Among them, when performing digital-to-analog conversion, it is in the holding stage.

[0118] When the first timing period is reached, it indicates that digital-to-analog conversion is required. In order to avoid transients in the original waveform at the time of digital-to-analog conversion, it is necessary to use the voltage of the original waveform most recently sampled before the digital-to-analog conversion as the holding voltage at the time of digital-to-analog conversion, and use the holding voltage as the output amplitude at the time of digital-to-analog conversion and during the period when the original waveform obtained by the digital-to-analog conversion is not stable, so as to avoid transients.

[0119] In a possible implementation, if dual channels are used to alternately perform digital-to-analog conversion, in order to make the digital-to-analog conversion in the holding stage of the corresponding channel, the holding period corresponding to the first channel is the first holding stage, and the holding period corresponding to the second channel is the second holding stage. In the case of the first holding stage, the processor obtains the first holding voltage of the first original waveform at the most recent sampling time before the digital-to-analog conversion is performed. Similarly, in the case of the second holding stage, the processor obtains the second holding voltage of the second original waveform at the most recent sampling time before the digital-to-analog conversion is performed.

[0120] Step S4: when in the sampling stage, output the original waveform at the sampling time.

[0121] After the digital-to-analog conversion, when the output original waveform is stable, the original waveform can continue to be used as the output waveform. When the sampling and holding module is in sampling, the original waveform output by the differential digital-to-analog converter is output as the output waveform.

[0122] In a possible implementation, dual channels are used to alternately perform digital-to-analog conversion, and the holding period corresponding to the first channel is the first sampling stage, and the holding period corresponding to the second channel is the second sampling stage. In the case of the first sampling stage, the processor outputs the first original waveform at the sampling moment; similarly, in the case of the second sampling stage, the processor samples and outputs the second original waveform at the sampling moment.

[0123] Please refer to Figure 6 , which shows a schematic diagram of the sampling phase and the holding phase provided by an exemplary embodiment of the present application. In the figure, when the first channel performs digital-to-analog conversion, it is in the first holding phase, and when the second channel performs digital-to-analog conversion, it is in the second holding phase, and the first holding phase and the second holding phase overlap in time, and the overlapping time is t 1 , which can avoid the inter-channel noise generated during the switching process between the holding phase and the sampling phase of one channel, thereby preventing the other channel from being affected.

[0124] Step S5, generating an output waveform based on the output amplitude.

[0125] A plurality of continuous output amplitudes are obtained at a plurality of continuous sampling moments, and the plurality of continuous amplitudes constitute an output waveform.

[0126] In a possible implementation, dual channels are used to alternately perform digital-to-analog conversion, and after the first channel obtains a first output amplitude, the processor generates a first output waveform based on the first output amplitude. After the second channel obtains a second output amplitude, the processor generates a second output waveform based on the second output amplitude.

[0127] In another possible implementation, since the output waveform is affected at the moment of switching between the holding phase and the sampling phase, resulting in a waveform with a smaller amplitude, when the output waveform is obtained, the output waveform is filtered to obtain a filtered output waveform.

[0128] In the embodiment of the present application, the processor controls the digital-to-analog conversion time, the holding period and the sampling period so that the digital-to-analog conversion is performed during the holding period, thereby avoiding the generation of harmonic noise in the output waveform at the digital-to-analog conversion time. In addition, the use of dual channels for alternating digital-to-analog conversion is conducive to reducing the frequency of digital-to-analog conversion of a single channel, thereby improving the performance of digital-to-analog conversion.

[0129] Please refer to Figure 7, which shows a sine wave frequency domain comparison diagram provided by an exemplary embodiment of the present application. The left side is a frequency domain diagram obtained by fast Fourier transforming the first sine wave signal generated by the relevant technology. It can be seen that the harmonic amplitude is high and the waveform quality is poor. The right side is a frequency domain diagram obtained by fast Fourier transforming the second sine wave signal generated by the waveform generation system provided by the present application. The frequencies of the first sine wave signal and the second sine wave signal are both 1KHz, and the effective amplitudes are both 0.707VRMS. It can be seen from the figure that the waveform generated by the waveform generation system provided by the present application has relatively few harmonics and a low harmonic amplitude, which is higher in quality than the sine waves generated by the relevant technology.

[0130] Please refer to Figure 8 , which shows a comparison chart of THD+N (Total Harmonic Distortion+Noise) test results provided by an exemplary embodiment of the present application. Among them, Ch1 corresponds to the test result of the waveform generation system provided by the present application, and Ch2 corresponds to the test result of the solution provided by the relevant technology. Among them, the waveform generation system provided by the present application and the solution provided by the prior art both generate a sine wave with a frequency of 1kHz and an amplitude of 0.707VRMS. It can be determined from the figure that the Ch1 THD+N corresponding to the system provided by the embodiment of the present application is -94.571dB, and the Ch2 THD+N corresponding to the solution provided by the relevant technology is -72.916dB, and the difference between the two is close to 20dB. It can be seen that the performance of the sine wave generated by the waveform generation system provided by the present application is significantly improved.

[0131] Please refer to Fig. 9 , which shows a flow chart of a waveform generation method provided by another exemplary embodiment of the present application, the method comprising the following steps:

[0132] Step 901: When a first timing duration reaches a first timing period, a programmable gate array generates a codeword.

[0133] Optionally, when the timing duration reaches the first timing period, the programmable gate array inverts the codeword to obtain an inverse codeword. Subsequently, the programmable gate array determines whether the most recent digital-to-analog conversion is based on the inverse codeword; if so, the digital-to-analog conversion is performed based on the codeword to obtain a first original waveform; if not, the digital-to-analog conversion is performed based on the inverse codeword to obtain a second original waveform.

[0134] Optionally, when the programmable gate array obtains the codeword, it adds the codeword to the tail of the first codeword queue, and when the inverse codeword is obtained, it adds the inverse codeword to the tail of the second codeword queue. In addition, before performing digital-to-analog conversion based on the codeword, the codeword is read from the head of the first codeword queue, and before performing digital-to-analog conversion based on the inverse codeword, the inverse codeword is read from the head of the second codeword queue.

[0135] Step 902: The differential digital-to-analog conversion module performs digital-to-analog conversion based on the codeword to obtain an original waveform.

[0136] Step 903, when the first timing period is reached, the sampling and holding module obtains the holding voltage of the original waveform at the most recent sampling moment before the digital-to-analog conversion and, when in the holding phase, maintains the holding voltage as the output amplitude at the sampling moment.

[0137] Among them, when performing digital-to-analog conversion, it is in the holding stage.

[0138] Optionally, the sampling and holding module includes a first sampling and holding unit and a second sampling and holding unit;

[0139] When the first sampling and holding unit is in the first holding stage, it obtains the first held voltage of the first original waveform at the most recent sampling moment before the digital-to-analog conversion is performed.

[0140] When the second sampling and holding unit is in the second holding stage, it obtains the second held voltage of the second original waveform at the most recent sampling moment before the digital-to-analog conversion is performed.

[0141] Optionally, when the timing duration reaches the first timing period and is in the second holding stage, the sampling and holding module starts the first holding stage; when the starting time of the first holding stage reaches the second timing period, the sampling and holding module starts the second sampling stage. When the timing duration reaches the first timing period and is in the first holding stage, the sampling and holding module starts the second holding stage; when the starting time of the second holding stage reaches the second timing duration, the sampling and holding module starts the second sampling stage.

[0142] Step 904: When the sample-and-hold module is in the sampling phase, the sample-and-hold module outputs the original waveform at the sampling time to obtain an output amplitude.

[0143] Optionally, when the first sampling and holding unit is in the first sampling phase, it outputs the first original waveform at the sampling moment, and uses the first original waveform at the sampling moment as the first output amplitude.

[0144] Optionally, when the second sampling and holding unit is in the second sampling phase, it outputs the second original waveform at the sampling moment, and uses the second original waveform at the sampling moment as the second output amplitude.

[0145] Step 905: The sample and hold module generates an output waveform based on the output amplitude.

[0146] In an embodiment of the present application, a programmable gate array outputs a codeword, a differential digital-to-analog conversion module performs digital-to-analog conversion based on the codeword, and a sampling and holding module controls whether the current phase is a sampling phase or a holding phase, so as to avoid a transient state in the output waveform when the amplitude codeword is converted into a voltage, avoid generating a large number of irregular harmonic spurs, and reduce the harmonic amplitude, thereby improving the quality of the output waveform.

[0147] In one embodiment of the present invention, a storage medium is further provided, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the steps in a waveform generation method shown in any one of the above embodiments are implemented.

[0148] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0149] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the present invention. They are not intended to limit the scope of protection of the present invention. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A waveform generation system, characterized in that: include: A programmable gate array, a sampling and holding module and a differential digital-to-analog conversion module, wherein the programmable gate array is connected to the differential digital-to-analog conversion module and the sampling and holding module, and an output end of the differential digital-to-analog conversion module is connected to an input end of the sampling and holding module; The programmable gate array is used to control the sample and hold module to switch the working mode, and the working mode includes holding and sampling; The programmable gate array is also used to control the differential digital-to-analog conversion module to perform digital-to-analog conversion and output a waveform when the sampling and holding module is in the holding state.

2. The system according to claim 1, characterized in that The programmable gate array includes a timing unit and a control unit; The timing unit is used to send a timing pulse; The control unit is used to send a conversion control signal to the differential digital-to-analog conversion module when receiving the timing pulse, wherein the conversion control signal is used to instruct the differential digital-to-analog conversion module to perform digital-to-analog conversion; The control unit is further configured to send a working mode control signal to the sampling and holding module when receiving the timing pulse.

3. The system according to claim 2, characterized in that The differential digital-to-analog conversion module includes a first digital-to-analog conversion unit and a second digital-to-analog conversion unit; The control unit is further configured to send a first conversion control signal to the first digital-to-analog conversion unit, and send a second conversion control signal to the second digital-to-analog conversion unit; The first digital-to-analog conversion unit is configured to perform digital-to-analog conversion upon receiving the first conversion control signal; The second digital-to-analog conversion unit is used to perform digital-to-analog conversion when receiving the second conversion control signal.

4. The system according to claim 3, characterized in that The sampling and holding module includes a first sampling and holding unit and a second sampling and holding unit, the first sampling and holding unit is connected to the first digital-to-analog conversion unit, the second sampling and holding unit is connected to the second digital-to-analog conversion unit, and the first sampling and holding unit and the second sampling and holding unit have different initial working modes; The control unit is used to control the first sampling and holding unit to switch to holding when receiving the timing pulse; The control unit is further configured to control the second sampling and holding unit to switch to sampling after waiting for a first working time when the timing pulse is received.

5. The system according to claim 4, characterized in that The control unit is further configured to control the first sampling and holding unit to switch to sampling when the first sampling and holding unit is in a state of holding for a second working time; The control unit is further configured to control the second sampling and holding unit to switch to holding when the sampling of the second sampling and holding unit reaches a third working time; The second working time is greater than the third working time, and the difference between the second working time and the third working time is twice the first working time.

6. The system according to claim 3, characterized in that The programmable gate array further comprises a codeword generating unit and an inverse code unit, wherein the inverse code unit is connected to an output terminal of the codeword generating unit; The codeword generating unit is configured to send the codeword to the first digital-to-analog conversion unit when the timing pulse is received, and to send the codeword to the inverse code unit when the timing pulse is received; The inverse code unit is used to generate an inverse code word based on the code word, and send the inverse code word to the second digital-to-analog conversion unit.

7. The system according to claim 1, characterized in that The system further comprises a filtering module, which is connected to the sampling and holding module, and is used for filtering the output waveform to obtain a filtered output waveform.

8. A waveform generation method, characterized in that: The method comprises: When the first timing duration reaches the first timing period, generating a code word; Performing digital-to-analog conversion based on the codeword to obtain an original waveform; When the first timing period is reached, obtaining the hold voltage of the original waveform at the most recent sampling moment before the digital-to-analog conversion is performed, and when in the hold phase, maintaining the hold voltage as the output amplitude at the sampling moment, wherein when the digital-to-analog conversion is performed, it is in the hold phase; In the case of being in the sampling stage, outputting the original waveform at the sampling time to obtain the output amplitude; An output waveform is generated based on the output amplitude.

9. The method according to claim 8, characterized in that The performing digital-to-analog conversion based on the codeword to obtain an original waveform includes: When the timing duration reaches the first timing period, the code word is inverted to obtain an inverted code word; Determining whether the most recent digital-to-analog conversion was performed based on the inverse codeword; If yes, performing digital-to-analog conversion based on the codeword to obtain a first original waveform; If not, digital-to-analog conversion is performed based on the inverse codeword to obtain a second original waveform.

10. The method according to claim 9, characterized in that When the first timing period is reached, obtaining the hold voltage of the original waveform at the most recent sampling moment before the digital-to-analog conversion is performed, comprises: In the case of being in the first holding stage, obtaining a first holding voltage of the first original waveform at the most recent sampling moment before performing the digital-to-analog conversion; In the case of being in the second holding stage, obtaining a second holding voltage of the second original waveform at the most recent sampling moment before performing the digital-to-analog conversion; In the case of being in the sampling stage, the original waveform is output at the sampling time to obtain the output amplitude, including: In the case of being in the first sampling stage, outputting the first original waveform at the sampling moment, and taking the first original waveform at the sampling moment as the first output amplitude; In the case of being in the second sampling stage, the second original waveform is output at the sampling moment, and the second original waveform at the sampling moment is used as the second output amplitude.

11. The method according to claim 10, characterized in that The method further comprises: When the timing duration reaches the first timing period and is in the second holding stage, the first holding stage begins; When the first holding phase starts for a period of time that reaches a second timing period, starting the second sampling phase; When the timing duration reaches the first timing period and is in the first holding stage, the second holding stage begins; When the start time of the second holding phase reaches the second timing time, the second sampling phase starts.

12. The method according to claim 9, characterized in that The method further comprises: When the codeword is obtained, the codeword is added to the tail of the first codeword queue; When the inverted codeword is obtained, the inverted codeword is added to the tail of the second codeword queue; Before performing digital-to-analog conversion based on the codeword, reading the codeword from the head of the first codeword queue; Before performing digital-to-analog conversion based on the inverted codeword, the inverted codeword is read from the head of the second codeword queue.

13. A storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the humidity control method according to any one of claims 8 to 12 is executed.

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