Transmission gate switch sampling circuit with substrate bias

Abstract

The invention relates to a transmission gate switch sampling circuit with substrate bias, which adopts a substrate bias technology for a transistor NMOS1 and a transistor PMOS1 to reduce the bulk effect of a sampling tube, and utilizes an NMOS tube gate voltage bootstrap circuit and a PMOS tube gate voltage bootstrap circuit to ensure that the VGS of the sampling tube is a constant value in the whole input range. The structural form of the sampling tube is a transmission gate switch with a substrate bias technology, channel charges flowing into the holding capacitor are counteracted when the sampling tube is turned off to reduce the channel charge injection effect, the influence of an input signal on the threshold voltage of the sampling tube can be reduced, the influence of the bulk effect of the sampling tube on the non-linearity of the switch is reduced, and the sampling tube is more stable in switching. Meanwhile, the influence of the channel charge injection effect on the sampling circuit is effectively inhibited, the dynamic range and the sampling precision of the sampling circuit are effectively improved when the sampling circuit is actually applied to the sampling / holding circuit, and the effect of improving the sampling performance of the sampling / holding circuit is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of sampling circuit design, and relates to a transmission gate switch sampling circuit with substrate bias. Background Art

[0002] In the context of the rapid development of electronic technology today, the application scale of sample / hold circuits continues to grow. With the rapid development of fields such as the Internet of Things, artificial intelligence, autonomous driving, and 5G communications, the demand for sample / hold circuits continues to increase, driving them to develop in the direction of high precision, low power consumption, high speed, and miniaturization. High-performance sample / hold circuits are one of the key technologies in many integrated circuit applications. As a crucial component in the sample / hold circuit, the performance of the switch determines the accuracy and linearity of the entire sample / hold circuit. However, with the increase of sampling frequency and the decrease of power supply voltage, the linearity of traditional MOS switches continues to decrease, limiting the dynamic range and sampling accuracy of the sample / hold circuit. Therefore, it is urgent to develop a sample / hold circuit with excellent sampling performance. Summary of the invention

[0003] In view of the problems existing in the above-mentioned conventional technology, the present invention proposes a transmission gate switch sampling circuit with substrate bias, which can effectively improve the sampling performance of the sample / hold circuit.

[0004] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: Provided is a transmission gate switch sampling circuit with substrate bias, comprising an inverter, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor PMOS1, a holding capacitor, an NMOS tube gate voltage bootstrap circuit and a PMOS tube gate voltage bootstrap circuit; The first clock terminal of the NMOS tube gate voltage bootstrap circuit and the input terminal of the inverter are both used to connect to the sampling control input terminal, the output terminal of the inverter is respectively connected to the second clock terminal of the NMOS tube gate voltage bootstrap circuit and the clock terminal of the PMOS tube gate voltage bootstrap circuit, the input terminal of the NMOS tube gate voltage bootstrap circuit, the input terminal of the PMOS tube gate voltage bootstrap circuit, the source of the transistor NMOS1, the source of the transistor NMOS2 and the source of the transistor PMOS1 are all used to connect to the signal input terminal, the output terminal of the NMOS tube gate voltage bootstrap circuit is respectively connected to the gate of the transistor NMOS1, the gate of the transistor NMOS2 and the second gate driving terminal of the PMOS tube gate voltage bootstrap circuit, the NMOS The control end of the tube gate voltage bootstrap circuit is connected to the first gate driving end of the PMOS tube gate voltage bootstrap circuit, the bias end of the PMOS tube gate voltage bootstrap circuit is connected to the substrate electrode of the transistor PMOS1, the output end of the PMOS tube gate voltage bootstrap circuit is connected to the gate of the transistor PMOS1, the drain of the transistor NMOS1 and the drain of the transistor PMOS1 are connected as the sampling output end, the drain of the transistor NMOS2 is respectively connected to the substrate electrode of the transistor NMOS1 and the drain of the transistor NMOS3, the source of the transistor NMOS3 is grounded, the gate of the transistor NMOS3 is used to connect the sampling control input end, one end of the holding capacitor is connected to the sampling output end, and the other end of the holding capacitor is grounded; The transistor NMOS2 and the transistor NMOS3 are used to reduce the body effect of the transistor NMOS1 through the substrate bias effect. The NMOS tube gate voltage bootstrap circuit is used to keep the gate-source voltage of the transistor NMOS1 constant during the sampling phase. The PMOS tube gate voltage bootstrap circuit is used to reduce the body effect of the transistor PMOS1 through the substrate bias effect and keep the gate-source voltage of the transistor PMOS1 constant during the sampling phase. The transistor NMOS1 and the transistor PMOS1 constitute a transmission gate switch.

[0005] In one embodiment, the NMOS gate voltage bootstrap circuit includes transistors NMOS4 to NMOS9, transistors PMOS2 to PMOS5 and capacitor C1; The source of transistor NMOS4 is the input end of the NMOS tube gate voltage bootstrap circuit, the substrate of transistor NMOS4 is grounded, the drain of transistor NMOS4 is respectively connected to the source of transistor NMOS5, the source of transistor NMOS6, the drain of transistor NMOS7 and one end of capacitor C1, the source of transistor NMOS7 is grounded, the gate of transistor NMOS7 is the first clock end of the NMOS tube gate voltage bootstrap circuit, the other end of capacitor C1 is connected to the source of transistor PMOS3 and serves as the control end of the NMOS tube gate voltage bootstrap circuit, the drain of transistor PMOS3 is used to connect to the power supply, and the gate of transistor PMOS3 is respectively connected to the drain of transistor PMOS4, the source of transistor NMOS8 and the gate of transistor NMOS4; The source of transistor PMOS4 is connected to the source of transistor PMOS3, the gate of transistor PMOS4 is respectively connected to the drain of transistor NMOS5, the drain of transistor NMOS6 and the source of transistor PMOS2, the drain and substrate of transistor PMOS2 are both used to connect to the power supply, the substrate of transistor NMOS5 and the substrate of transistor NMOS6 are both grounded, the gate of transistor NMOS5 is connected to the gate of transistor NMOS4 and serves as the output end of the NMOS tube gate voltage bootstrap circuit, and the gate of transistor NMOS6 is connected to the gate of transistor PMOS2 and serves as the second clock end of the NMOS tube gate voltage bootstrap circuit; The substrate electrode of transistor NMOS8 is grounded, the gate electrode of transistor NMOS8, the substrate electrode of transistor PMOS5 and the drain electrode of transistor PMOS5 are all used to connect to the power supply, the source electrode of transistor PMOS5 is respectively connected to the drain electrode of transistor NMOS8 and the drain electrode of transistor NMOS9, the source electrode of transistor NMOS9 is grounded, and the gate electrode of transistor PMOS5 is connected to the gate electrode of transistor NMOS9 and connected to the first clock terminal of the NMOS tube gate voltage bootstrap circuit.

[0006] In one embodiment, the PMOS gate voltage bootstrap circuit includes transistors NMOS10 to NMOS14, transistors PMOS6 to PMOS12, capacitors C2 and C3; The gate of transistor NMOS10 is connected to the gate of transistor PMOS6 and serves as the clock end of the PMOS gate voltage bootstrap circuit, the source of transistor NMOS10 is grounded, the drain of transistor NMOS10 is respectively connected to the source of transistor PMOS6, one end of capacitor C2 and the source of transistor NMOS11, the substrate of transistor PMOS6, the drain of transistor PMOS6 and the drain of transistor PMOS7 are all used to connect to the power supply, the source of transistor PMOS7 is respectively connected to the source of transistor PMOS8, the other end of capacitor C2 and the source of transistor PMOS9, the gate of transistor PMOS7 is respectively connected to the drain of transistor PMOS8 and the drain of transistor NMOS11, and the gate of transistor PMOS8 and the gate of transistor NMOS11 are both used to connect to the power supply; The gate of transistor PMOS9 is used to connect to the power supply, the drain of transistor PMOS9 is respectively connected to the source of transistor NMOS12 and one end of capacitor C3, the gate of NMOS12 is the first gate driving end of the PMOS tube gate voltage bootstrap circuit, the drain of transistor NMOS12, the source of transistor NMOS13 and the drain of transistor PMOS11 are connected as the bias end of the PMOS tube gate voltage bootstrap circuit, the drain of transistor NMOS13 is the input end of the PMOS tube gate voltage bootstrap circuit, the gate of transistor NMOS13 is the second gate driving end of the PMOS tube gate voltage bootstrap circuit, and the transistor PMOS11 is connected to the gate of transistor NMOS13. The source of transistor PMOS11 and the source of transistor PMOS12 are used to connect to the power supply, the gate of transistor PMOS11, the gate of transistor PMOS12 and the gate of transistor NMOS14 are all connected to the clock end of the PMOS tube gate voltage bootstrap circuit, the drain of transistor PMOS12 is respectively connected to the drain of transistor NMOS14 and the drain of transistor PMOS10, the source of transistor NMOS14 and the gate of transistor PMOS10 are both grounded, the substrate of transistor PMOS10 is used to connect to the power supply, and the source of transistor PMOS10 is connected to the other end of capacitor C3 and serves as the output end of the PMOS tube gate voltage bootstrap circuit.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The transmission gate switch sampling circuit with substrate bias adopts substrate bias technology to transistor NMOS1 and transistor PMOS1 to reduce the body effect of the sampling tube. At the same time, the gate voltage bootstrap circuit of the NMOS tube and the gate voltage bootstrap circuit of the PMOS tube are used to ensure that the VGS of the sampling tube is a constant value in the entire input range. The sampling tube structure is a transmission gate switch with substrate bias technology. The channel charge injection effect is reduced by offsetting the channel charge flowing into the holding capacitor when the sampling tube is turned off. It can not only reduce the influence of the input signal on the threshold voltage of the sampling tube, but also reduce the influence of the body effect of the sampling tube on the nonlinearity of the switch. At the same time, it effectively suppresses the influence of the channel charge injection effect on the sampling circuit. When it is actually applied to the sampling / holding circuit, its dynamic range and sampling accuracy are effectively improved, and the sampling performance of the sampling / holding circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1is a schematic structural diagram of a transmission gate switch sampling circuit with substrate bias in one embodiment; Figure 2 A schematic diagram of the structure of an NMOS tube gate voltage bootstrap circuit in one embodiment; Figure 3 FIG. 4 is a schematic diagram of the structure of a PMOS tube gate voltage bootstrap circuit in an embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In one embodiment, Figure 1 As shown, a transmission gate switch sampling circuit with substrate bias is provided, including an inverter INV1, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor PMOS1, a holding capacitor C0, an NMOS tube gate voltage bootstrap circuit and a PMOS tube gate voltage bootstrap circuit.

[0014] The first clock terminal (CLK) of the NMOS tube gate voltage bootstrap circuit (i.e. BTSP_NMOS) and the input terminal of the inverter INV1 are used to connect the sampling control input terminal (VSAMP), and the output terminal of the inverter INV1 is respectively connected to the second clock terminal (CLKB) of the NMOS tube gate voltage bootstrap circuit and the clock terminal (CLK) of the PMOS tube gate voltage bootstrap circuit (i.e. BTSP_PMOS). The input terminal (VIN) of the NMOS tube gate voltage bootstrap circuit, the input terminal (VIN) of the PMOS tube gate voltage bootstrap circuit, the source of the transistor NMOS1, the source of the transistor NMOS2 and the source of the transistor PMOS1 are all used to connect the signal input terminal (i.e. VSIG). The output terminal (VOUT) of the NMOS tube gate voltage bootstrap circuit is respectively connected to the gate of the transistor NMOS1, the gate of the transistor NMOS2 and the second gate driving terminal (i.e. VG2) of the PMOS tube gate voltage bootstrap circuit. The control end (VC) of the NMOS tube gate voltage bootstrap circuit is connected to the first gate driving end (VG1) of the PMOS tube gate voltage bootstrap circuit, the bias end (VB) of the PMOS tube gate voltage bootstrap circuit is connected to the substrate of the transistor PMOS1, and the output end (OUT) of the PMOS tube gate voltage bootstrap circuit is connected to the gate of the transistor PMOS1. The drain of the transistor NMOS1 and the drain of the transistor PMOS1 are connected as the sampling output end OUT. The drain of the transistor NMOS2 is respectively connected to the substrate of the transistor NMOS1 and the drain of the transistor NMOS3, the source of the transistor NMOS3 is grounded, and the gate of the transistor NMOS3 is used to connect the sampling control input end VSAMP, one end of the holding capacitor C0 is connected to the sampling output end OUT, and the other end of the holding capacitor C0 is grounded.

[0015] The transistor NMOS2 and the transistor NMOS3 are used to reduce the body effect of the transistor NMOS1 through the substrate bias effect. The NMOS tube gate voltage bootstrap circuit is used to keep the gate-source voltage of the transistor NMOS1 constant during the sampling phase. The PMOS tube gate voltage bootstrap circuit is used to reduce the body effect of the transistor PMOS1 through the substrate bias effect and keep the gate-source voltage of the transistor PMOS1 constant during the sampling phase. The transistor NMOS1 and the transistor PMOS1 constitute a transmission gate switch.

[0016] It can be understood that the power supply end of the NMOS tube gate voltage bootstrap circuit and the PMOS tube gate voltage bootstrap circuit is used to access the power supply VDD, and the ground end of the NMOS tube gate voltage bootstrap circuit and the PMOS tube gate voltage bootstrap circuit are both used for grounding (VSS). Among them, the transistor NMOS and the transistor PMOS are two metal-oxide-semiconductors with different channel types, respectively. The transistor NMOS is an N-type metal-oxide-semiconductor, and the transistor PMOS is a P-type metal-oxide-semiconductor. The same transistor devices below can be understood in the same way. For the NMOS tube gate voltage bootstrap circuit, its CLK and CLKB signals are a pair of complementary clock signals. When CLK is high, CLKB is low, and vice versa. The CLK and CLKB signal control is used for the NMOS tube gate voltage bootstrap circuit to ensure that it is turned on or off at the right time to achieve gate voltage bootstrap. For the PMOS tube gate voltage bootstrap circuit, its working clock follows the CLKB signal to achieve the corresponding gate voltage bootstrap function.

[0017] Specifically, transistor NMOS1 and transistor PMOS1 are used as sampling tubes to form a transmission gate switch. Transistor NMOS2 and transistor NMOS3 perform substrate bias on transistor NMOS1, thereby reducing the body effect of transistor NMOS1. PMOS tube gate voltage bootstrap circuit performs substrate bias on transistor PMOS1, thereby reducing the body effect of transistor PMOS1. Channel charge injection effect is reduced by offsetting the channel charge flowing into the holding capacitor C0 when the transmission gate switch is turned off, so as to effectively suppress the influence of the channel charge injection effect on the sampling circuit. At the same time, the VGS (gate-source voltage) of transistor NMOS1 is made a constant value in the sampling stage through the NMOS tube gate voltage bootstrap circuit BTSP_NMOS, and the VGS of transistor PMOS1 is made a constant value in the sampling stage through the PMOS tube gate voltage bootstrap circuit BTSP_PMOS, so as to achieve a constant value of the VGS of the sampling tube in the entire input range, and reduce the degree of change of the sampling resistance of the sampling circuit with the change of the input signal.

[0018] The transmission gate switch sampling circuit with substrate bias adopts substrate bias technology to transistor NMOS1 and transistor PMOS1 to reduce the body effect of the sampling tube. At the same time, the gate voltage bootstrap circuit of the NMOS tube and the gate voltage bootstrap circuit of the PMOS tube are used to ensure that the VGS of the sampling tube is a constant value in the entire input range. The sampling tube structure is a transmission gate switch with substrate bias technology. The channel charge injection effect is reduced by offsetting the channel charge flowing into the holding capacitor C0 when the sampling tube is turned off. It can not only reduce the influence of the input signal on the threshold voltage of the sampling tube, but also reduce the influence of the body effect of the sampling tube on the nonlinearity of the switch. At the same time, it effectively suppresses the influence of the channel charge injection effect on the sampling circuit. When it is actually applied to the sampling / holding circuit, its dynamic range and sampling accuracy are effectively improved, and the sampling performance of the sampling / holding circuit is improved.

[0019] In one embodiment, Figure 2 As shown, the NMOS tube gate voltage bootstrap circuit may include transistors NMOS4 to NMOS9, transistors PMOS2 to PMOS5 and capacitor C1. The source of transistor NMOS4 is the input terminal VIN of the NMOS tube gate voltage bootstrap circuit, the substrate of transistor NMOS4 is grounded to VSS, the drain of transistor NMOS4 is respectively connected to the source of transistor NMOS5, the source of transistor NMOS6, the drain of transistor NMOS7 and one end of capacitor C1, the source of transistor NMOS7 is grounded to VSS, and the gate of transistor NMOS7 is the first clock terminal CLK of the NMOS tube gate voltage bootstrap circuit. The other end of capacitor C1 is connected to the source of transistor PMOS3 and serves as the control terminal VC of the NMOS tube gate voltage bootstrap circuit. The drain of transistor PMOS3 is used to connect to the power supply VDD, and the gate of transistor PMOS3 is respectively connected to the drain of transistor PMOS4, the source of transistor NMOS8 and the gate of transistor NMOS4.

[0020] The source of transistor PMOS4 is connected to the source of transistor PMOS3, the gate of transistor PMOS4 is respectively connected to the drain of transistor NMOS5, the drain of transistor NMOS6 and the source of transistor PMOS2, the drain and substrate of transistor PMOS2 are both used to connect to power supply VDD, and the substrate of transistor NMOS5 and the substrate of transistor NMOS6 are both grounded to VSS. The gate of transistor NMOS5 is connected to the gate of transistor NMOS4 and serves as the output terminal OUT of the NMOS gate voltage bootstrap circuit. The gate of transistor NMOS6 is connected to the gate of transistor PMOS2 and serves as the second clock terminal CLKB of the NMOS gate voltage bootstrap circuit. The substrate of transistor NMOS8 is grounded to VSS, and the gate of transistor NMOS8, the substrate of transistor PMOS5 and the drain of transistor PMOS5 are all used to connect to power supply VDD. The source of transistor PMOS5 is connected to the drain of transistor NMOS8 and the drain of transistor NMOS9 respectively, the source of transistor NMOS9 is grounded to VSS, and the gate of transistor PMOS5 is connected to the gate of transistor NMOS9 and to the first clock terminal CLK of the NMOS gate voltage bootstrap circuit.

[0021] It can be understood that in this embodiment, the Figure 2 The structural design of the NMOS tube gate voltage bootstrap circuit shown provides the required gate voltage bootstrap function with a more streamlined and efficient circuit structure design. It adopts an almost all-transistor structure design, which can effectively reduce the circuit area and improve the circuit response speed.

[0022] Among them, the specific implementation process of maintaining a constant value of VGS in the sampling stage can be as follows: in the reset stage, that is, when CLK is at a high level, transistors NMOS7, NMOS8, NMOS9, PMOS2 and PMOS3 are turned on, and transistor PMOS4 is turned off. At this time, the current charges the capacitor C1 through the transistor PMOS3, so that the voltage difference of the capacitor C1 reaches VDD. When CLK is at a low level, transistors NMOS4 and NMOS6 are turned on, transistors NMOS7 and NMOS9 are turned off, transistors PMOS2 and PMOS3 are turned off, and transistors PMOS4 and PMOS5 are turned on. Based on the law of conservation of charge, since the voltage value of capacitor C1 has been charged to VDD in the reset phase, the voltage of the VC node is VIN+VDD in the sampling phase, so that the potential of the OUT node of the gate voltage bootstrap circuit is also VIN+VDD, so that the gate potential of transistor (sampling tube) NMOS1 is VIN+VDD, and the input signal of the source of transistor NMOS1 in the sampling phase is VIN, so the VGS of transistor NMOS1 in the sampling phase can be made a constant value through the NMOS gate voltage bootstrap voltage.

[0023] In one embodiment, Figure 3 As shown, the PMOS tube gate voltage bootstrap circuit includes transistors NMOS10 to NMOS14, transistors PMOS6 to PMOS12, capacitors C2 and C3. The gate of transistor NMOS10 is connected to the gate of transistor PMOS6 and serves as the clock terminal CLK of the PMOS tube gate voltage bootstrap circuit. The source of transistor NMOS10 is grounded, and the drain of transistor NMOS10 is respectively connected to the source of transistor PMOS6, one end of capacitor C2 and the source of transistor NMOS11. The substrate of transistor PMOS6, the drain of transistor PMOS6 and the drain of transistor PMOS7 are all used to connect to the power supply VDD. The source of transistor PMOS7 is respectively connected to the source of transistor PMOS8, the other end of capacitor C2 and the source of transistor PMOS9, and the gate of transistor PMOS7 is respectively connected to the drain of transistor PMOS8 and the drain of transistor NMOS11. The gate of transistor PMOS8 and the gate of transistor NMOS11 are both used to connect to the power supply VDD.

[0024] The gate of transistor PMOS9 is used to connect to the power supply VDD, the drain of transistor PMOS9 is respectively connected to the source of transistor NMOS12 and one end of capacitor C3, and the gate of NMOS12 is the first gate driving terminal VG1 of the PMOS tube gate voltage bootstrap circuit. The drain of transistor NMOS12, the source of transistor NMOS13 and the drain of transistor PMOS11 are connected as the bias terminal VB of the PMOS tube gate voltage bootstrap circuit. The drain of transistor NMOS13 is the input terminal VIN of the PMOS tube gate voltage bootstrap circuit. The gate of transistor NMOS13 is the second gate driving terminal VG2 of the PMOS tube gate voltage bootstrap circuit. The source of transistor PMOS11 and the source of transistor PMOS12 are both used to connect to the power supply VDD, and the gate of transistor PMOS11, the gate of transistor PMOS12 and the gate of transistor NMOS14 are all connected to the clock terminal CLK of the PMOS tube gate voltage bootstrap circuit. The drain of transistor PMOS12 is respectively connected to the drain of transistor NMOS14 and the drain of transistor PMOS10, the source of transistor NMOS14 and the gate of transistor PMOS10 are both grounded, the substrate of transistor PMOS10 is used to connect to the power supply VDD, and the source of transistor PMOS10 is connected to the other end of capacitor C3 and serves as the output end OUT of the PMOS gate voltage bootstrap circuit.

[0025] It can be understood that in this embodiment, the Figure 3The structural design of the PMOS tube gate voltage bootstrap circuit shown provides the other gate voltage bootstrap function required above with a more streamlined and efficient circuit structure design. It also adopts an almost all-transistor structure design, which can effectively reduce the circuit area and improve the circuit response speed.

[0026] Among them, in the PMOS tube gate voltage bootstrap circuit, the substrate level of transistor PMOS1 is controlled by transistor NMOS12, transistor NMOS13 and transistor PMOS11 to achieve the required substrate bias effect. At the same time, the constant control of VGS of transistor PMOS1 is achieved by transistor PMOS7, transistor PMOS9, transistor PMOS10, transistor PMOS12 and transistor NMOS14 in conjunction with capacitor C3 (i.e., bootstrap capacitor), and its control principle can be understood by referring to the same principle of NMOS tube gate voltage bootstrap circuit. Those skilled in the art can adopt the specific structural design of other PMOS tube gate voltage bootstrap circuits that can achieve the same function according to the above implementation principle, as long as the same control purpose can be achieved.

[0027] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0028] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A transmission gate switch sampling circuit with substrate bias, characterized in that: It includes an inverter, a transistor NMOS1, a transistor NMOS2, a transistor NMOS3, a transistor PMOS1, a holding capacitor, an NMOS tube gate voltage bootstrap circuit and a PMOS tube gate voltage bootstrap circuit; The first clock end of the NMOS tube gate voltage bootstrap circuit and the input end of the inverter are both used to connect to the sampling control input end, the output end of the inverter is respectively connected to the second clock end of the NMOS tube gate voltage bootstrap circuit and the clock end of the PMOS tube gate voltage bootstrap circuit, the input end of the NMOS tube gate voltage bootstrap circuit, the input end of the PMOS tube gate voltage bootstrap circuit, the source of the transistor NMOS1, the source of the transistor NMOS2 and the source of the transistor PMOS1 are all used to connect to the signal input end, the output end of the NMOS tube gate voltage bootstrap circuit is respectively connected to the gate of the transistor NMOS1, the gate of the transistor NMOS2 and the second gate driving end of the PMOS tube gate voltage bootstrap circuit, the NMOS The control end of the tube gate voltage bootstrap circuit is connected to the first gate driving end of the PMOS tube gate voltage bootstrap circuit, the bias end of the PMOS tube gate voltage bootstrap circuit is connected to the substrate electrode of the transistor PMOS1, the output end of the PMOS tube gate voltage bootstrap circuit is connected to the gate of the transistor PMOS1, the drain of the transistor NMOS1 and the drain of the transistor PMOS1 are connected as a sampling output end, the drain of the transistor NMOS2 is respectively connected to the substrate electrode of the transistor NMOS1 and the drain of the transistor NMOS3, the source of the transistor NMOS3 is grounded, the gate of the transistor NMOS3 is used to connect the sampling control input end, one end of the holding capacitor is connected to the sampling output end, and the other end of the holding capacitor is grounded; The transistor NMOS2 and the transistor NMOS3 are used to reduce the body effect of the transistor NMOS1 through the substrate bias effect. The NMOS tube gate voltage bootstrap circuit is used to keep the gate-source voltage of the transistor NMOS1 constant during the sampling phase. The PMOS tube gate voltage bootstrap circuit is used to reduce the body effect of the transistor PMOS1 through the substrate bias effect and keep the gate-source voltage of the transistor PMOS1 constant during the sampling phase. The transistor NMOS1 and the transistor PMOS1 constitute a transmission gate switch.

2. The transmission gate switch sampling circuit with substrate bias according to claim 1, characterized in that: The NMOS gate voltage bootstrap circuit comprises transistors NMOS4 to NMOS9, transistors PMOS2 to PMOS5 and a capacitor C1; The source of the transistor NMOS4 is the input end of the NMOS tube gate voltage bootstrap circuit, the substrate of the transistor NMOS4 is grounded, the drain of the transistor NMOS4 is respectively connected to the source of the transistor NMOS5, the source of the transistor NMOS6, the drain of the transistor NMOS7 and one end of the capacitor C1, the source of the transistor NMOS7 is grounded, the gate of the transistor NMOS7 is the first clock end of the NMOS tube gate voltage bootstrap circuit, the other end of the capacitor C1 is connected to the source of the transistor PMOS3 and serves as the control end of the NMOS tube gate voltage bootstrap circuit, the drain of the transistor PMOS3 is used to connect to the power supply, and the gate of the transistor PMOS3 is respectively connected to the drain of the transistor PMOS4, the source of the transistor NMOS8 and the gate of the transistor NMOS4; The source of the transistor PMOS4 is connected to the source of the transistor PMOS3, the gate of the transistor PMOS4 is respectively connected to the drain of the transistor NMOS5, the drain of the transistor NMOS6 and the source of the transistor PMOS2, the drain and substrate of the transistor PMOS2 are both used to connect to the power supply, the substrate of the transistor NMOS5 and the substrate of the transistor NMOS6 are both grounded, the gate of the transistor NMOS5 is connected to the gate of the transistor NMOS4 and serves as the output end of the NMOS tube gate voltage bootstrap circuit, and the gate of the transistor NMOS6 is connected to the gate of the transistor PMOS2 and serves as the second clock end of the NMOS tube gate voltage bootstrap circuit; The substrate electrode of the transistor NMOS8 is grounded, the gate electrode of the transistor NMOS8, the substrate electrode of the transistor PMOS5 and the drain electrode of the transistor PMOS5 are all used to connect to a power supply, the source electrode of the transistor PMOS5 is respectively connected to the drain electrode of the transistor NMOS8 and the drain electrode of the transistor NMOS9, the source electrode of the transistor NMOS9 is grounded, and the gate electrode of the transistor PMOS5 is connected to the gate electrode of the transistor NMOS9 and to the first clock terminal of the NMOS tube gate voltage bootstrap circuit.

3. The transmission gate switch sampling circuit with substrate bias according to claim 1 or 2, characterized in that: The PMOS gate voltage bootstrap circuit includes transistors NMOS10 to NMOS14, transistors PMOS6 to PMOS12, capacitors C2 and C3; The gate of the transistor NMOS10 is connected to the gate of the transistor PMOS6 and serves as the clock end of the PMOS gate voltage bootstrap circuit. The source of the transistor NMOS10 is grounded. The drain of the transistor NMOS10 is respectively connected to the source of the transistor PMOS6, one end of the capacitor C2 and the source of the transistor NMOS11. The substrate of the transistor PMOS6, the drain of the transistor PMOS6 and the drain of the transistor PMOS7 are all used to connect to a power supply. The source of the transistor PMOS7 is respectively connected to the source of the transistor PMOS8, the other end of the capacitor C2 and the source of the transistor PMOS9. The gate of the transistor PMOS7 is respectively connected to the drain of the transistor PMOS8 and the drain of the transistor NMOS11. The gate of the transistor PMOS8 and the gate of the transistor NMOS11 are both used to connect to a power supply. The gate of the transistor PMOS9 is used to connect to the power supply, the drain of the transistor PMOS9 is respectively connected to the source of the transistor NMOS12 and one end of the capacitor C3, the gate of the transistor NMOS12 is the first gate driving end of the PMOS tube gate voltage bootstrap circuit, the drain of the transistor NMOS12, the source of the transistor NMOS13 and the drain of the transistor PMOS11 are connected as the bias end of the PMOS tube gate voltage bootstrap circuit, the drain of the transistor NMOS13 is the input end of the PMOS tube gate voltage bootstrap circuit, the gate of the transistor NMOS13 is the second gate driving end of the PMOS tube gate voltage bootstrap circuit, and the transistor PMOS The source of transistor 11 and the source of transistor PMOS12 are both used to connect to the power supply, the gate of transistor PMOS11, the gate of transistor PMOS12 and the gate of transistor NMOS14 are all connected to the clock end of the PMOS tube gate voltage bootstrap circuit, the drain of transistor PMOS12 is respectively connected to the drain of transistor NMOS14 and the drain of transistor PMOS10, the source of transistor NMOS14 and the gate of transistor PMOS10 are both grounded, the substrate of transistor PMOS10 is used to connect to the power supply, the source of transistor PMOS10 is connected to the other end of capacitor C3 and serves as the output end of the PMOS tube gate voltage bootstrap circuit.

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