Switch compensation R-2R digital-to-analog converter

Abstract

The invention relates to the technical field of digital-to-analog converters, in particular to a switch compensation R-2R digital-to-analog converter. The switch compensation R-2R digital-to-analog converter comprises a digital-to-analog converter main circuit, a switch circuit, a switch PMOS (P-channel Metal Oxide Semiconductor) grid voltage generation circuit and a switch NMOS (N-channel Metal Oxide Semiconductor) grid voltage generation circuit, a circuit comprising an MOS (Metal Oxide Semiconductor), a resistor, a current source and an amplifier is used for generating switch grid control voltage, and the switch on resistance is controlled to be a preset value; therefore, the nonlinearity of the digital-to-analog converter is reduced.

Description

Technical Field

[0001] The invention relates to the technical field of digital-to-analog converters, and in particular to a switch-compensated R-2R digital-to-analog converter. Background Art

[0002] The R-2R DAC is composed of resistors and switches. The resistors have two resistance values, R and 2R. The linearity of the DAC is determined by the matching of the resistors. The closer the ratio of the two resistors is to 2 times, the better the linearity. One end of the 2R resistor is connected to the positive reference voltage VREFP or the negative reference voltage VREFN through the switch according to the input code value. The switch connected to VREFP is usually implemented by PMOS, and the switch connected to VREFN is usually implemented by NMOS.

[0003] The prior art (CN103166645A) discloses an R-2R type digital-to-analog converter circuit, which includes a control logic, an R-2R type digital-to-analog converter and a switch connected in series, and also has a grounded capacitor at the output end. When any adjacent 4 bits of an n-bit binary digital signal include at least one bit changing from 0 to 1, and at least one bit changing from 1 to 0; and at least one of the bits that change is located in each bit of the n-bit binary digital signal except the lower four bits, it is a condition for disconnecting the switch. When the control logic finds that the condition for disconnecting the switch has been met, it first outputs the control signal of the switch to disconnect the switch, and then outputs the converted 2n-4 one-bit binary digital signals to the R-2R type digital-to-analog converter. After the digital-to-analog conversion time of the R-2R type digital-to-analog converter is reached, the control signal of the switch is output again to close the switch. However, the switch connected to the reference voltage of the above-mentioned digital-to-analog converter has a non-zero on-resistance, and the on-resistance of the PMOS is different from that of the NMOS. This on-resistance is connected to the resistor 2R, which changes the resistance value of 2R, resulting in a larger nonlinearity of the digital-to-analog converter. Summary of the invention

[0004] In view of this, the present invention proposes a switch-compensated R-2R digital-to-analog converter, which controls the on-resistance of the transistor switch to a preset value by setting the gate voltage of the transistor switches PMOS and NMOS, and simultaneously connects a resistor of corresponding resistance in series to the resistor R, so that the combined R and 2R are still twice the relationship, thereby reducing the nonlinearity of the digital-to-analog converter.

[0005] In order to achieve the above-mentioned purpose, a switch-compensated R-2R digital-to-analog converter is provided, comprising: a digital-to-analog converter main circuit, a switching circuit, a PMOS switch gate voltage generating circuit, and an NMOS switch gate voltage generating circuit; wherein the digital-to-analog converter main circuit is respectively connected to the switching circuit, the PMOS switch gate voltage generating circuit, and the NMOS switch gate voltage generating circuit.

[0006] Preferably, the main circuit of the digital-to-analog converter is composed of resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10 and a plurality of switches (SW), wherein the switches include a PMOS switch MP1 and an NMOS switch MN1, and the resistors R1, R4, R7, R10 have a resistance value of 2R U The resistor is connected between VOUT and the switch. The resistors R2, R3, R5, R6, R8, and R9 have a resistance value of R U A resistor is connected between the switch and ground; VREFP and VREFN are positive and negative reference voltages for determining the output range of the digital-to-analog converter, VOUT is the output voltage of the digital-to-analog converter, and the output value of VOUT is determined by the input binary signal and the resistor network, b11, b10, b9, b0, b11b, b10b, b9b, b0b are binary input codes for controlling the switch (SW); the control switch (SW) is connected to the positive reference voltage VREFP, the negative reference voltage VREFN, the PMOS gate control voltage VBP, and the NMOS gate control voltage VBN.

[0007] Preferably, the switching circuit includes a PMOS switch MP1 and an NMOS switch MN1; the PMOS switch MP1 is connected to VREFP, the NMOS switch MN1 is connected to VREFN, the gate of the PMOS switch MP1 is connected to VBP or VDD under the control of an input code value, and the gate of the NMOS switch MN1 is connected to VBN or GND under the control of an input code value.

[0008] Preferably, the PMOS switch gate voltage generating circuit comprises a current source I1, a current source I2, a resistor R1, a PMOS switch MP1, and an operational amplifier; wherein the resistor R1 is connected in parallel with the current source I1, and the resistance value of the resistor R1 is 200*R S The source of the PMOS switch MP1 is connected to the resistor R1, the drain of the PMOS switch MP1 is connected to the positive input terminal (V2) of the operational amplifier, the negative input terminal of the operational amplifier is grounded, and the output terminal (VBP) of the operational amplifier is used to provide a gate voltage of the PMOS switch; the current source I2 is connected in parallel to the drain of the PMOS switch MP1.

[0009] Preferably, the NMOS switch gate voltage generating circuit comprises a current source I1, a current source I2, a resistor R1, an NMOS switch MN1, and an operational amplifier; wherein the resistor R1 is connected in parallel with the current source I1, and the resistance value of the resistor R1 is 200*R S, the source of the NMOS switch MN1 is connected to the resistor R1, the drain of the NMOS switch MN1 is connected to the positive input terminal (V2) of the operational amplifier, the negative input terminal of the operational amplifier is grounded, and the output terminal (VBN) of the operational amplifier is used to provide the gate voltage of the PMOS switch; the current source I2 is connected in parallel with the drain of the NMOS switch MN1.

[0010] The advantages and beneficial effects of the present invention are:

[0011] The switch-compensated R-2R digital-to-analog converter of the present invention comprises: a digital-to-analog converter main circuit, a switch circuit, a switch PMOS gate voltage generating circuit, and a switch NMOS gate voltage generating circuit. The present invention uses a circuit including MOS, a resistor, a current source and an amplifier to generate a switch gate control voltage, controls the switch on-resistance to a preset value, thereby reducing the nonlinearity of the digital-to-analog converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the description of the present invention or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0013] Figure 1 A schematic diagram of a switch-compensated R-2R digital-to-analog converter provided by an embodiment of the present invention;

[0014] Figure 2 A schematic diagram of a switch circuit provided by an embodiment of the present invention;

[0015] Figure 3 A schematic diagram of a PMOS switch gate voltage generating circuit provided by an embodiment of the present invention;

[0016] Figure 4 A schematic diagram of an NMOS switch gate voltage generating circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Attached Figure 1A schematic diagram of a switch-compensated R-2R digital-to-analog converter is shown in the attached Figure 1 As shown, a switch-compensated R-2R digital-to-analog converter comprises: a digital-to-analog converter main circuit, a switch circuit, a switch PMOS gate voltage generating circuit, and a switch NMOS gate voltage generating circuit; wherein the digital-to-analog converter main circuit is respectively connected to the switch circuit, the switch PMOS gate voltage generating circuit, and the switch NMOS gate voltage generating circuit.

[0019] The main circuit of the digital-to-analog converter is composed of resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10 and a plurality of switches (SW), wherein the switches (SW) include a PMOS switch MP1 and an NMOS switch MN1, and the resistors R1, R4, R7, and R10 have a resistance value of 2R U The resistor is connected between VOUT and the switch. The resistors R2, R3, R5, R6, R8, and R9 have a resistance value of R U The resistor is connected between the switch and the ground; VREFP and VREFN are positive and negative reference voltages for determining the output range of the DAC, VOUT is the output voltage of the digital-to-analog converter, and the output value of VOUT is determined by the input binary signal and the resistor network. b11, b10, b9, b0, b11b, b10b, b9b, b0b are binary input codes for controlling the switch (SW); the control switch (SW) is connected to the positive reference voltage VREFP, the negative reference voltage VREFN, the PMOS gate control voltage VBP, and the NMOS gate control voltage VBN; the switch SW is used to: no matter it is connected to VREFP or VREFN, the on-resistance of the switch is 2R U ;

[0020] The working principle of the digital-to-analog converter is as follows: according to the input binary bit, the switch will add the corresponding voltage (VREFP, VREFN or 0) to VOUT. Due to the R-2R configuration of the resistor, the contribution of each bit to VOUT is different, the highest bit (b11) contributes the most, and the lowest bit (b0) contributes the least. The output voltage VOUT is the weighted sum of the contributions of all bits, and the weight is determined by the value of the binary bit and the resistor network.

[0021] Among them, Figure 2 A schematic diagram of the switch circuit is shown in FIG. Figure 2As shown, the switch circuit includes a PMOS switch MP1 and an NMOS switch MN1; the PMOS switch MP1 is connected to VREFP, the NMOS switch MN1 is connected to VREFN, the gate of the PMOS switch MP1 is connected to VBP or VDD under the control of an input code value (bn, bnb), and the gate of the NMOS switch MN1 is connected to VBN or GND under the control of an input code value (bn, bnb);

[0022] When the gate of the PMOS switch MP1 is connected to VBP, VBP controls the NMOS switch MP1 so that the on-resistance of the PMOS switch MP1 is 2*RS; when the gate of the PMOS switch MP1 is connected to VDD, the PMOS switch MP1 is turned off; when the gate of the NMOS switch MN1 is connected to VBN, VBN controls the NMOS switch MN1 so that the on-resistance of the NMOS switch MN1 is 2*RS; when the gate of the NMOS switch MN1 is connected to GND, the NMOS switch MN1 is turned off.

[0023] Among them, Figure 3 The schematic diagram of the PMOS switch gate voltage generating circuit is shown in FIG. Figure 3 As shown, the PMOS switch gate voltage generating circuit includes a current source I1, a current source I2, a resistor R1, a PMOS switch MP1, and an operational amplifier; wherein the resistor R1 is connected in parallel with the current source I1, and the resistance value of the resistor R1 is 200*R s , the source of the PMOS switch MP1 is connected to the resistor R1, the drain of the PMOS switch MP1 is connected to the positive input terminal (V2) of the operational amplifier, the negative input terminal of the operational amplifier is grounded, and the output terminal (VBP) of the operational amplifier is used to provide a gate voltage of the PMOS switch; the current source I2 is connected in parallel with the drain of the PMOS switch MP1;

[0024] The currents of the current sources I1 and I2 are the same, and the feedback of the amplifier forces the node voltages V1 and V2 to be the same, so the voltage drop across the resistor R1 is the same as that of the PMOS switch MP1. The resistance value of the PMOS switch MP1 is R W / 100*L Equal to the resistance value of R1, as shown in formula (1):

[0025] R W / 100*L =200*R S ——(1)

[0026] The amplifier output VBP controls the PMOS switch MP1, Figure 3In the figure, the width-to-length ratio of the PMOS switch MP1 is W / L. According to the fact that the on-resistance of MOS in the linear region is inversely proportional to the width-to-length ratio, the resistance R of the PMOS switch with a width-to-length ratio of W / L is W / L yes:

[0027]

[0028] Among them, Figure 4 The schematic diagram of the NMOS switch gate voltage generating circuit is shown in FIG. Figure 4 As shown, the NMOS switch gate voltage generating circuit includes a current source I1, a current source I2, a resistor R1, an NMOS switch MN1, and an operational amplifier; wherein the resistor R1 is connected in parallel with the current source I1, and the resistance value of the resistor R1 is 200*R S , the source of the NMOS switch MN1 is connected to the resistor R1, the drain of the NMOS switch MN1 is connected to the positive input terminal (V2) of the operational amplifier, the negative input terminal of the operational amplifier is grounded, and the output terminal (VBN) of the operational amplifier is used to provide the gate voltage of the PMOS switch; the current source I2 is connected in parallel with the drain of the NMOS switch MN1;

[0029] The current sources I1 and I2 have the same current. The feedback of the amplifier forces the node voltages V1 and V2 to be the same. Therefore, the voltage drop across resistor R1 is the same as that of NMOS switch MN1. The resistance of NMOS switch MN1 is equal to the resistance of R1. The output VBN of the amplifier also controls NMOS switch MN1. The resistance of NMOS switch MN1 is also 2*R, which is the same as that of PMOS switch MP1. S .

[0030] Thus, the on-resistance of the two switches MN1 and MP1 is controlled to be 2*R S , and the resistance is R U The resistance increases the series resistance R S , so the combined resistance of the two resistors still conforms to the 2-fold relationship, thus maintaining the linearity of the digital-to-analog converter.

[0031] It will be appreciated by those skilled in the art that the embodiments herein may be provided as methods, devices (equipment), or computer program products. Therefore, this article may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Including but not limited to RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store desired information and can be accessed by a computer, etc. In addition, it is well known to those of ordinary skill in the art that communication media generally contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0032] This document is described with reference to flowcharts and / or block diagrams of methods, apparatuses (devices) and computer program products according to the embodiments of this document. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0033] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0034] The embodiments and / or implementation methods described above are only used to illustrate the preferred embodiments and / or implementation methods of the technology of the present invention, and are not intended to impose any formal restrictions on the implementation methods of the technology of the present invention. Any person skilled in the art may make some changes or modifications to other equivalent embodiments without departing from the scope of the technical means disclosed in the content of the present invention, but they should still be regarded as the technology or embodiments that are essentially the same as the present invention. Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described here, and that various obvious changes, readjustments and substitutions can be made to those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention is described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A switch-compensated R-2R digital-to-analog converter, characterized in that: include: A digital-to-analog converter main circuit, a switch circuit, a PMOS switch gate voltage generating circuit, and an NMOS switch gate voltage generating circuit; wherein the digital-to-analog converter main circuit is respectively connected to the switch circuit, the PMOS switch gate voltage generating circuit, and the NMOS switch gate voltage generating circuit.

2. A switch-compensated R-2R digital-to-analog converter according to claim 1, characterized in that: The main circuit of the digital-to-analog converter is composed of resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10 and a plurality of switches (SW), wherein the switches include a PMOS switch MP1 and an NMOS switch MN1, and the resistors R1, R4, R7, and R10 have a resistance value of 2R U The resistor is connected between VOUT and the switch. The resistors R2, R3, R5, R6, R8, and R9 have a resistance value of R U A resistor is connected between the switch and ground; VREFP and VREFN are positive and negative reference voltages for determining the output range of the digital-to-analog converter, VOUT is the output voltage of the digital-to-analog converter, and the output value of VOUT is determined by the input binary signal and the resistor network, b11, b10, b9, b0, b11b, b10b, b9b, b0b are binary input codes for controlling the switch (SW); the control switch (SW) is connected to the positive reference voltage VREFP, the negative reference voltage VREFN, the PMOS gate control voltage VBP, and the NMOS gate control voltage VBN.

3. The switch-compensated R-2R digital-to-analog converter according to claim 1, characterized in that: The switch circuit includes a PMOS switch MP1 and an NMOS switch MN1; the PMOS switch MP1 is connected to VREFP, the NMOS switch MN1 is connected to VREFN, the gate of the PMOS switch MP1 is connected to VBP or VDD under the control of an input code value, and the gate of the NMOS switch MN1 is connected to VBN or GND under the control of an input code value.

4. The switch-compensated R-2R digital-to-analog converter according to claim 1, characterized in that: The PMOS switch gate voltage generating circuit includes a current source I1, a current source I2, a resistor R1, a PMOS switch MP1, and an operational amplifier; wherein the resistor R1 is connected in parallel with the current source I1, and the resistance value of the resistor R1 is 200*R S The source of the PMOS switch MP1 is connected to the resistor R1, the drain of the PMOS switch MP1 is connected to the positive input terminal (V2) of the operational amplifier, the negative input terminal of the operational amplifier is grounded, and the output terminal (VBP) of the operational amplifier is used to provide a gate voltage of the PMOS switch; the current source I2 is connected in parallel to the drain of the PMOS switch MP1.

5. The switch-compensated R-2R digital-to-analog converter according to claim 1, characterized in that: The NMOS switch gate voltage generating circuit includes a current source I1, a current source I2, a resistor R1, an NMOS switch MN1, and an operational amplifier; wherein the resistor R1 is connected in parallel with the current source I1, and the resistance value of the resistor R1 is 200*R S , the source of the NMOS switch MN1 is connected to the resistor R1, the drain of the NMOS switch MN1 is connected to the positive input terminal (V2) of the operational amplifier, the negative input terminal of the operational amplifier is grounded, and the output terminal (VBN) of the operational amplifier is used to provide the gate voltage of the PMOS switch; the current source I2 is connected in parallel with the drain of the NMOS switch MN1.

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