SAR-SS type ADC circuit and module with pre-judgment logic

Abstract

The invention relates to the technical field of image sensor design, and particularly discloses an SAR-SS type ADC circuit and module with pre-judgment logic. On the basis of digital correlation multi-sampling, the SAR-SS hybrid architecture is adopted to decompose 12-bit quantization of two columns of pixel signals {Vref, n} and {Vsig, n} into coarse quantization through the SAR-ADC part and fine quantization through the SS-ADC part, the overall quantization speed of the ADC is improved under the condition that low noise is achieved, and the power consumption is lower than that of a traditional CMS ADC adopting a single-architecture SS type ADC. The circuit provided by the invention is provided with a pre-judgment logic part for judging whether the pixel readout signal Vsig, 2 needs to be coarsely quantized or not, so that unnecessary time consumption and power consumption of the coarsely quantized signal are reduced, and the overall speed and power consumption of the ADC are further improved.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor design, and more specifically to: 1. a SAR-SS type ADC circuit with pre-judgment logic; 2. a SAR-SS type ADC module with pre-judgment logic. Background Art

[0002] CMOS image sensor (Complementary Metal Oxide Semiconductor Image Sensor), referred to as CIS, is widely used in digital cameras, mobile phone cameras, surveillance cameras, etc. As a key component of CMOS, the analog-to-digital converter (ADC) is responsible for converting the electrical signal generated by the photosensitive element into a digital signal, and its performance directly determines the imaging quality of CMOS.

[0003] At present, three types of ADCs are mainly used in CIS: pixel-level ADC, column-level ADC and chip-level ADC. Among them, column-level ADC has become the mainstream choice due to its advantages such as low power consumption, relatively simple design and high conversion efficiency. Common column-level ADCs include successive approximation ADC (SAR ADC), cyclic ADC and single slope ADC (SS ADC). Each structure has its own characteristics in terms of accuracy, speed and power consumption, and can be selected according to specific needs.

[0004] The quantization results of ADCs working in dark environments are extremely susceptible to the influence of surrounding noise, so low-noise designs are required. In recent years, correlated multi-sampling technology (CMS) has become the mainstream in the design of low-noise ADCs. Single-slope ADCs (SS ADCs) have become the main type used in CMS ADCs due to their simple structure, low power consumption and small area.

[0005] However, the traditional CMS ADC only uses a single SS-type structure. Although this can achieve very good noise reduction effects, the ADC quantization time is very long, which leads to high power consumption. In addition, there is an obvious exponential relationship between the conversion speed, power consumption and bit number of the traditional SS ADC. Improving the conversion accuracy by 1 bit requires a nearly exponential increase in speed and power consumption, and these indicators are particularly important for CIS. Therefore, improving speed and reducing power consumption while ensuring low noise has become an important research point for CMS ADC. Summary of the invention

[0006] Based on this, it is necessary to provide a SAR-SS ADC circuit and module with pre-judgment logic to address the problem that traditional CMS ADC needs to increase speed and reduce power consumption while ensuring low noise.

[0007] The present invention is implemented by the following technical solutions: In a first aspect, the present invention provides a SAR-SS type ADC circuit with pre-judgment logic for processing two columns of pixel signals {V ref,n}、{V sig,n}12bit quantization is performed to obtain [V ref,n ,V sig,n ]'s 12-bit quantization result F n <11:0>; n∈{1,2}.

[0008] A SAR-SS type ADC circuit with pre-judgment logic comprises: a signal input part, a gain amplification part, a pre-judgment logic part, a SAR-ADC part, a SS-ADC part, and a data processing part.

[0009] 1. The signal input section is used to convert V ref,1 、V sig,1 、V ref,2 、V sig,2 Enter in order.

[0010] 2. The gain amplifier is used to perform gain amplification on the output of the signal input unit.

[0011] 3. The pre-judgment logic is used to sig,2 After input, determine whether coarse quantization is required.

[0012] 4. SAR-ADC is used for: ref,1 、V sig,1 、V ref,2 After the input, the corresponding output of the gain amplifier is coarsely quantized to obtain the corresponding 6-bit code value D ref,1 <5:0>, D sig,1 <5:0>, D ref,2 <5:0>; at V sig,2 After input, the corresponding operation is performed according to the judgment result of the pre-judgment logic unit; If it is determined that coarse quantization is not necessary, D is retained. sig,1 <5:0> as V sig,2 The corresponding 6-bit code value D sig,2 <5:0>; otherwise, coarse quantization is performed based on the output corresponding to the gain amplifier to obtain the corresponding 6-bit code value D sig,2 <5:0>.

[0013] 5. The SS-ADC section is used to compare V ref,n 、V sig,n After the coarse quantization is completed, based on V ref,n 、V sig,n Perform digital correlated multi-sampling to obtain a 9-bit code value En <8:0>.

[0014] 6. Data processing unit is used for: ref,n <5:0>, D sig,n <5:0> Perform digital correlated double sampling to obtain a 6-bit coarse quantization result F n <5:0>, based on D sig,n The highest bit D in <5:0> sig,n <0> For E n <8:0> Perform conditional multi-sampling selection to obtain a 6-bit fine quantization result F n <11:6>; Among them, F n <5:0>, F n <11:6> constitutes F n <11:0>.

[0015] The implementation of the SAR-SS type ADC circuit with pre-judgment logic is based on the method or process of the embodiment of the present disclosure.

[0016] In a second aspect, the present invention discloses a SAR-SS type ADC module with pre-judgment logic, which adopts the layout of a SAR-SS type ADC circuit with pre-judgment logic disclosed in the first aspect.

[0017] The implementation of the SAR-SS type ADC module with pre-judgment logic is based on the method or process of the embodiment of the present disclosure.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention adopts SAR-SS hybrid architecture based on digital correlated multi-sampling to convert two columns of pixel signals {V ref,n}、{V sig,n The 12-bit quantization of the ADC is decomposed into coarse quantization by the SAR-ADC part and fine quantization by the SS-ADC part, which improves the overall quantization speed of the ADC while achieving low noise and has lower power consumption than the traditional CMSADC using a single-architecture SS-type ADC.

[0019] 2. The circuit of the present invention is provided with a pre-judgment logic unit to determine whether the pixel readout signal V sig,2 Coarse quantization is performed to make judgments in order to reduce unnecessary time and power consumption of coarse quantization, thereby further improving the overall speed and power consumption of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 A schematic diagram of the structure of a SAR-SS type ADC circuit with pre-judgment logic provided by the present invention; Figure 2 for Figure 1 Circuit connection diagram of signal input part and gain amplifier part; Figure 3 for Figure 1 Circuit connection diagram of SAR-ADC part; Figure 4 for Figure 1 Circuit connection diagram of SS-ADC part; Figure 5 for Figure 4 Circuit connection diagram of the ramp generator RAMP_generator; Figure 6 for Figure 1 Circuit connection diagram of the pre-judgment logic unit; Figure 7 for Figure 1 A schematic diagram of a SAR-SS type ADC circuit for pre-judgment logic selection; Figure 8 for Figure 1 The circuit diagram of the data processing unit; Fig. 9 For Figure 1 The simulation results of the SAR-SS ADC circuit Figure 1 ; Fig.10 For Figure 1 The simulation results of the SAR-SS ADC circuit Figure 2 ; Fig.11 For Figure 1 The simulation results of the SAR-SS ADC circuit Figure 3 . DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more related listed items.

[0025] Example 1 This embodiment 1 provides a SAR-SS type ADC circuit with pre-judgment logic.

[0026] First of all, it should be noted that this SAR-SS ADC circuit is designed to convert 2 columns of pixel signals {V ref,n}、{V sig,n}12bit quantization is performed to obtain [V ref,n ,V sig,n ]'s 12-bit quantization result F n <11:0>.

[0027] Among them, {V ref,n} represents a pixel reset signal for one column; {V sig,n} represents 1 column of pixel readout signals.

[0028] [V ref,n ,V sig,n ] represents a pixel group consisting of 1 pixel reset signal and 1 pixel readout signal.

[0029] It should be noted that the number of components of a single column of pixel signals can be increased or decreased in theory, for example, n is taken as an integer greater than 2, but as the value of n increases, the processing speed of the entire row of pixels (i.e., the CIS frame rate) is not significantly improved. Therefore, in this embodiment 1, a single column of pixel signals is set to be composed of two signals (i.e., n∈{1,2}, {Vref,n That is, {V ref,1 ,V ref,2}、{V sig,n That is, {V sig,1 ,V sig,2}), which can achieve an optimal balance between efficiency and area.

[0030] Next see Figure 1 , which shows the structural diagram of the SAR-SS type ADC circuit. According to the functional division, the SAR-SS type ADC circuit includes: a signal input part, a gain amplification part, a pre-judgment logic part, a SAR-ADC part, a SS-ADC part, and a data processing part.

[0031] The following is an introduction to each part (considering that the pre-judgment logic part, SAR-ADC part, and SS-ADC part are closely related, they are introduced together): 1. The signal input section is used to convert V ref,1 、V sig,1 、V ref,2 、V sig,2 Enter in order.

[0032] See also Figure 2 The signal input section can be designed to include: 2 input switches S P1 ~S P2 ; S P1 The first end of the ref,n}, the second end is connected to the input end of the gain amplifier; S P2 The first end of the sig,n}, and the second end is connected to the input end of the gain amplifier.

[0033] In this way, by P1 , S P2 Control is performed so that they are not closed simultaneously but sequentially.

[0034] Specifically, first turn on S P1 , disconnect S P2 , V ref,1 That is, through the signal input part, and output to the gain amplifier part; then turn on S P2 , disconnect S P1 , V sig,1 That is, through the signal input part, and output to the gain amplifier part; V ref,2 and V sig,2 The input control is similar and will not be repeated.

[0035] Of course, the signal input part may also adopt other circuit designs, but they need to meet the above-mentioned signal input requirements.

[0036] 2. The gain amplifier is used to perform gain amplification on the output of the signal input unit.

[0037] See also Figure 2 The gain amplifier can be designed to include: 1 high gain op amp Amp, 1 fixed capacitor C H1 , 1 programmable capacitor C H2 , 1 switch S C .

[0038] C H2 The first end is used as the input end of the gain amplifier, and the second end is connected to C H1 The first end, S C The first end of , the input end of Amp; C H1 The second end, S C The second end is connected to the output end of Amp; The output end of Amp serves as the output end of the gain amplifier and is used to output a gain signal Vin.

[0039] Specifically, S. C Closed, the signal is reset; S C If disconnected, the signal is amplified.

[0040] Among them, the gain amplification factor of the gain amplifier is k With C H2 / C H1 is positively correlated, then by H2 To adjust the capacitance, you can adjust k , in order to reduce the impact of noise on subsequent signal quantization.

[0041] So, for Vin, it has gone through four stages of changes: In V ref,1 After input, Vin is k *V ref,1 ; In V sig,1 After input, Vin is k *V sig,1 ; In V ref,2 After input, Vin is k *V ref,2 ; In V sig,2 After input, Vin is k *V sig,2 .

[0042] Of course, the gain amplifier may also adopt other circuit designs, but they need to meet the above-mentioned signal gain requirements.

[0043] 3. For the pre-judgment logic part, SAR-ADC part, and SS-ADC part, in general: The pre-judgment logic section is used to sig,2 After input, determine whether coarse quantization is needed; The SAR-ADC section is used to: ref,1 、V sig,1 、V ref,2 After the input, the corresponding output of the gain amplifier is coarsely quantized to obtain the corresponding 6-bit code value D ref,1 <5:0>, D sig,1 <5:0>, D ref,2 <5:0>; at V sig,2 After input, the corresponding operation is performed according to the judgment result of the pre-judgment logic unit; SS-ADC section, which is used in the SAR-ADC section to V ref,n 、V sig,n After the coarse quantization is completed, based on V ref,n 、V sig,n Perform digital correlated multi-sampling to obtain a 9-bit code value E n <8:0>.

[0044] Then we have: In Vin k *V ref,1 , will first perform coarse quantization, and then perform fine quantization based on digital correlated multi-sampling; In Vin k *V sig,1 , will first perform coarse quantization, and then perform fine quantization based on digital correlated multi-sampling; In Vin k *V ref,2 , will first perform coarse quantization, and then perform fine quantization based on digital correlated multi-sampling; In Vin k *V sig,2 , will first determine whether coarse quantization is needed, and then perform corresponding operations based on the judgment result (if it is determined that coarse quantization is not necessary, D sig,1 <5:0> as V sig,2 The corresponding 6-bit code value D sig,2 <5:0>; otherwise, coarse quantization is performed based on the output corresponding to the gain amplifier to obtain the corresponding 6-bit code value D sig,2 <5:0>), followed by fine quantization based on digital correlated multi-sampling.

[0045] That is to say, if one quantization cycle of Vin is divided into stages, it can be divided into: pre-judgment logic selection stage (when Vin is k *Vsig,2 must be carried out when Vin is k *V ref,1 , k *V sig,1 , k *V ref,2 It must be carried out when Vin is k *V sig,2 The result of the pre-judgment logic selection stage determines whether to proceed), the quantization stage (when Vin is k *V ref,1 , k *V sig,1 , k *V ref,2 , k *V sig,2 must be carried out when necessary).

[0046] 301, first introduce the SAR-ADC part: See also Figure 3 The SAR-ADC part performs 6-bit coarse quantization, and can be designed to include: a SAR logic part SAR-logic, a signal selection part MUX, a capacitor array part, a switch array part, 1 comparator COMP0, 1 latch Latch, and 1 switching switch S1.

[0047] The first terminal of S1 is connected to the control voltage V CM , the second end is connected to the output voltage V DAC .

[0048] When the gain amplifier performs gain amplification, S1 is closed; when quantization starts, S1 is opened.

[0049] The negative input of COMP0 is connected to V DAC The positive input terminal is connected to Vin, the output terminal is used to output comparison signals VP and VN, and the control terminal is connected to the timing signal CLK_REAL.

[0050] Among them, COMP0 adopts a dynamic comparator, which only adopts a one-stage pre-amplifier design.

[0051] The capacitor array includes: 7 capacitors C in parallel G ~C A ; C G ~C A The upper board connects V DAC .

[0052] Among them, C G ~C A The capacitance ratio is 1:1:2:4:8:16:32; C G Redundant capacitor.

[0053] The switch array section includes: 18 switches S A0 ~S F0 , S A1 ~S F1 , S A2 ~S F2 ; Among them, the switch S σ0 The first end of the switch S σ1 The first end of the switch S σ2 The first end of the capacitor C σ The lower board of S σ0 The second end is connected to V CM ; S σ1 The second end is connected to the control voltage V H ; S σ2 The second end is connected to the control voltage V L ;σ∈[A,B,C,D,E,F].

[0054] The control end of SAR-logic is connected to VP and VN, the output end 1 is used to output the timing signal CLK, and the output end 2 is used to output the control signal Ctrl to the switch array part and MUX.

[0055] It should be noted that SAR-logic uses asynchronous SAR logic. Since there are 18 switches in the switch array, Ctrl actually contains 18 corresponding switch control signals (i.e. Ctrl_S A0 ~Ctrl_S F0 , Ctrl+S A1 ~Ctrl_S EF1 , Ctrl+S A2 ~Ctrl_S F2 ), 2 gate control signals (i.e. Ctrl_mux2 ~ Ctrl_mux3) to respectively A0 ~S F0 , S A1 ~S F1 , S A2 ~S F2 , mux2~mux3 for control.

[0056] The input end of the latch is connected to the output end 3 of the SAR-logic, and the output end is used to output the 6-bit code value obtained by coarse quantization.

[0057] MUX includes a two-to-one selector mux2 and a three-to-one selector mux3; the input end of mux2 is connected to V CM , input terminal 2 is connected to the ramp signal V ramp ; Input 1 of mux3 is connected to the output of mux2, and input 2 is connected to VH , input terminal three connected to V L , the output terminal is connected to C G The lower level board.

[0058] It should be noted that in coarse quantization, mux2 selects V CM ; In fine quantization, mux2 selects V ramp .

[0059] In general, the capacitor array part cooperates with the switch array part and MUX to adjust V DAC ; SAR-logic controls the switch array unit based on the comparison result of COMP0.

[0060] 302. Next, we will introduce the SS-ADC unit: See also Figure 4 The SS-ADC part performs 6-bit fine quantization, which can be designed to include: 1 comparator COMP1, 1 counter Counter, and 1 ramp generator RAMP_generator.

[0061] The negative input of COMP1 is connected to V DAC , the positive input terminal is connected to Vin, and the output terminal is used to output the control signal V COM .

[0062] Among them, COMP1 adopts a static comparator, which adopts a three-stage pre-amplifier structure design to reduce the offset voltage by eliminating the input offset.

[0063] The input of Counter is connected to V COM .

[0064] It should be noted that although the SS-ADC part performs 6-bit fine quantization, a 3-bit redundant counter is used to compensate for the possible error between coarse and fine quantization. Therefore, Counter is a 9-bit bidirectional counter, which is used to count Vin up and down to obtain E n <8:0>.

[0065] Among them, Counter in Vin is k *V ref,1 When Vin is k *V sig,1 When Vin is k *V ref,2 When Vin is k *V sig,2 Count up at the same time to get E2<8:0>.

[0066] Then, E n The extra 3 bits of <8:0> include: a sign bit in the highest bit (9th bit), a redundant bit in the second highest bit (8th bit), and a redundant bit in the third highest bit (7th bit).

[0067] That is, the SS-ADC part adopts a digital correlated multi-sampling method, which can reduce the influence of noise.

[0068] RAMP_generator is used to generate V ramp RAMP_generator is a 6-bit ramp generator, which can be used as follows: Figure 5 The design shown includes: a conversion circuit part, a current source part, a differential switch part, and an operational amplifier array part.

[0069] Specifically, the conversion circuit unit includes: 1 resistor R, 1 resistor R dummy ; The second end of R is connected to R dummy The first end of R is used as the output end of RAMP_generator to output V ramp .

[0070] The current source section includes: 17 current sources I0~I 16 ; Among them, I0~I 16 The current ratio is 1:2:4:4:4:4:4:4:4:4:4:4:4:4:4:4:4. In other words, I0 uses i0 current source (i0 represents standard current), I1 uses 2i0 current source, and I2~I 16 All use 4i0 current source.

[0071] The differential switch section includes: 34 switches S W,0 ~S W,33 ; Among them, I x By S W,x Connect the first end of R through S W,y Connect R dummy The first end of ; x∈{0,2,4,…,32}, y∈{1,3,5,…,33}.

[0072] The operational amplifier array includes: 1 operational amplifier A0, 1 capacitor C x , 1 NMOS tube N1; the negative input terminal of A0 is connected to the reference voltage V th , the positive input terminal is connected to C x The first end of R, the second end of R, the drain of N1, and the output end is connected to C x The second end of N1 and the gate of N1; the source of N1 is grounded.

[0073] The RAMP_generator of the above structure adopts a combination of binary coding and thermometer coding, which can combine the advantages of low complexity and small area of ​​binary coding circuit with high linearity and small burrs of thermometer decoding: the lower 2 bits adopt binary coding to reduce the number of thermometer coding bits, thereby reducing the area of ​​the thermometer coding circuit, and at the same time add an inverter chain to transmit the input signal to ensure delay synchronization; the upper 4 bits adopt thermometer coding to reduce the noise generated by too many flipping bits during the carry process; and A0 and N1 are used to form a negative feedback circuit, and the negative feedback principle of the operational amplifier is used to clamp the initial voltage of the ramp to a fixed value V th , so that V ramp V th As the starting point, gradually rise.

[0074] Of course, RAMP_generator can also use other circuit designs, but it is necessary to ensure that V ramp signal stability.

[0075] 303. Then introduce the pre-judgment logic part: See also Figure 6 The pre-judgment logic part can be designed to include: 2 latches LATCH1~LATCH2, 1 inverter INV, 1 exclusive OR gate XOR, 1 AND gate AND, and 1 two-to-one selector mux1.

[0076] The input terminals of LATCH1 and LATCH2 are connected to V COM ; The output end of LATCH1 is used to output the control signal PRE1, the output end of LATCH2 is connected to the input end of INV, and the output end of INV is used to output the control signal PRE2; Input terminal 1 of AND is connected to PRE1, input terminal 2 is connected to PRE2, and the output terminal is used to output the selection signal PRE; Input 1 of XOR is connected to PRE, and input 2 is connected to CLK; Input 1 of mux1 is connected to the output of XOR, input 2 is connected to CLK, and the output is used to output CLK_REAL.

[0077] Refer to the above record, the pre-judgment logic is in V sig,2 After input, LATCH1 latches C G The lower substrate is connected to V H The comparison result of COMP1 is used as PRE1, and LATCH2 latches C G The lower substrate is connected to V L The comparison result of COMP1 is obtained by inverting it through INV as PRE2, and PRE1 and PRE2 are ANDed to generate PRE.

[0078] If PRE is high, it means that PRE1 is high and PRE2 is low, then D sig1 <5:0> as D sig2 <5:0>, V sig,2 The value of is also within the range of fine quantization, so the coarse quantization process can be skipped; Since SAR-logic uses asynchronous SAR logic, it relies on the CLK (also called asynchronous comparator clock signal) generated by the asynchronous SAR logic. At the beginning of quantization, CLK is low level; if the pre-judgment logic unit determines that coarse quantization is not necessary, PRE is high level, PRE is different from CLK or obtains high level CLK_REAL, so that COMP0 cannot be compared, making V sig,2 Of course, if the levels of PRE1, PRE2, and PRE are not as discussed above, it is necessary to adjust V sig,2 The SAR-ADC unit is used for coarse quantization.

[0079] It should be noted that the power consumption of the SAR-ADC part mainly comes from switch switching and DAC charge transfer, which naturally has a power consumption advantage over the SS-ADC part. Moreover, after using the pre-judgment logic part, the power consumption of the SAR-ADC part can be further saved and the quantization time of the entire ADC can be shortened.

[0080] In addition, a single-architecture SS-type ADC requires about 512 clock cycles to perform 12-bit quantization, but the SAR-SS-type ADC circuit only requires about 266 clock cycles, nearly doubling the A / D conversion speed.

[0081] So far, based on the above-mentioned pre-judgment logic unit, SAR-ADC unit, and SS-ADC unit, the quantization cycle is specifically described: (1) In the coarse quantization stage: In the coarse quantization Vin (i.e. Vin is k *V ref,1 or k *V sig,1 or k *V ref,2 ), V DAC Connect to COMP0 and compare with Vin, output VP and VN to SAR-logic, and the pre-judgment logic part does not work at this time.

[0082] On the one hand, SAR-logic is based on asynchronous SAR logic, which adjusts the switch array according to VP and VN, and then adjusts V DAC .

[0083] The specific method is as follows: the initial state of the switch array is S A0 ~S F0 Closed, S A1 ~S F1 , S A2 ~S F2 Disconnect; SAR-logic generates Ctrl according to VP and VN, making S A0 Disconnect, S A1 or S A2 Closed, the other switches in the switch array remain in their previous states, V DAC If the value changes, VP and VN will also change; SAR-Logic will first generate a new Ctrl based on the new VP and VN to control S B0 Disconnect, S B1 or S B2 Close, the other switches in the switch array remain in the previous state; and so on, until S F0 ~S F2 Complete strobe; in S F0 ~S F2 After the selection is completed, SAR-logic will first generate a new Ctrl based on the new VP and VN to control the MUX switch to turn on V CM or V H or V L .

[0084] On the other hand, Latch latches the output signal of SAR-logic and outputs a 6-bit code value. It should be noted that if the 6-bit code value here is represented as D n <5:0>, then we have: Vin k *V ref,1 When D n <5:0> is D ref,1 <5:0>; Vin k *V sig1 When D n <5:0> is D sig,1 <5:0>; Vin k *V ref,2 When D n <5:0> is D ref,2 <5:0>; Vin k *V sig,2 When D n <5:0> is D sig,2 <5:0>.

[0085] (2) In the fine quantification stage: The lower board of C0 is connected to V ramp (V ramp The initial value is V th , V th Typically set to V L equal), then at the beginning of refinement, V DAC Less than Vin; when V ramp After access, V DAC Increase V per clock cycle ramp / 64 method. V DAC Connect to COMP1 and compare with Vin to output V COM Drive Counter to start counting for digital correlated multi-sampling until V COM When a reversal occurs, the Counter stops counting and the count value is E. n <8:0>.

[0086] (3) In the pre-judgment logic selection stage: For a more intuitive understanding of how this phase works, see Figure 7 , which shows several situations: In T p0 period, S1 is disconnected, S A1 ~S F1 , S A2 ~S F2 Keep the switch state of the previous coarse quantization unchanged; In T p1 Period, C G The lower plate is connected to V H ; In T p2 Period, C G The lower plate is connected to V L ; In T p1 、T p2 Period, V DAC , Vin is compared in COMP1: T p1 The comparison result is latched and used as PRE1; T p2 The comparison result is latched and inverted as PRE2; ​​PRE1 and PRE2 are ANDed to generate PRE.

[0087] If PRE is 1, corresponding Figure 7 For the situation in area (a), we can make a preliminary judgment. A1 ~S F1 , S A2 ~S F2 Keep the switch state after the previous coarse quantization, and no longer adjust V sig,2 Perform rough quantization; In addition to this, Figure 7 As shown in the (b) and (c) areas, it is necessary to p3 Period V sig,2 Perform coarse quantization.

[0088] 4. Data processing unit is used for: ref,n <5:0>, D sig,n <5:0> Perform digital correlated double sampling to obtain a 6-bit coarse quantization result F n <5:0>, based on D sig,n The highest bit D in <5:0> sig,n <0> For E n <8:0> Perform conditional multi-sampling selection to obtain a 6-bit fine quantization result F n <11:6>.

[0089] Among them, F n <5:0>, F n <11:6> constitutes F n <11:0>.

[0090] That is to say, the data processing unit uses a combination of digital correlated double sampling and conditional multi-sampling, which can effectively reduce noise.

[0091] See also Figure 8 The data processing unit can be designed to include: 1 subtractor, 3 latches LATCH3~LATCH5, and 1 adaptive multi-sampling unit.

[0092] Among them, LATCH3 is used to latch D sig,n <5:0>; LATCH4 is used to latch D ref,n <5:0>.

[0093] like Figure 8 As shown, the input end of LATCH3 is connected to the output end of Latch, and the output end 1 is used to output D sig,n <5:0>, output terminal 2 is used to output D sig,n <0> The input end of LATCH4 is connected to the output end of Latch.

[0094] Subtractor is used to perform subtraction operations on the output of LATCH3 and LATCH4, and according to E n <8:0>The most significant bit E n <8> The subtraction result is sign-corrected to obtain F n <5:0>.

[0095] like Figure 8As shown, the input terminal 1 of Subtractor is connected to the output terminal of LATCH3, the input terminal 2 is connected to the output terminal of LATCH4, and the input terminal 3 is connected to the output terminal 2 of Counter (the output terminal 1 of Counter is used to output E n <8:0>The most significant bit E n <8> ).

[0096] It should be noted that Subtractor first converts the output of LATCH3 (i.e. D sig,n <5:0>) minus the output of LATCH4 (i.e., D ref,n <5:0>) to get the subtraction result. Considering that the subtraction result may be negative, a sign bit E is introduced. n <8> :If E n <8> If it is 0, the subtraction result remains unchanged and is used as F n <5:0>; if E n <8> If it is 1, add 1 to the subtraction result (000001 in binary) and use it as F n <5:0>.

[0097] The adaptive multi-sampling unit is used to sig,n <0> Generate a selection signal choose to implement Counter and then perform conditional multi-sampling according to choose.

[0098] like Figure 8 As shown, the input end of the adaptive multi-sampling unit is connected to the output end 1 of LATCH3, and the output end is connected to the control end of Counter. The output end 1 of Counter is used to output E_6.

[0099] Specific: If D sig,n <0> If it is 1, Counter performs one sampling count and outputs the sampling count result as E_6, which is equivalent to outputting E n <5:0> (i.e. E n <8:0>) as E_6.

[0100] If D sig,n <0> If it is 0, Counter performs 4 sampling counts and takes the average of the sampling count results as E_6 for output, which is equivalent to E_6. n <7:2> (i.e. E n The 3rd to 8th bits of <8:0> are used as E_6.

[0101] LATCH5 is used to latch E_6 and convert it into F n <11:6>.

[0102] like Figure 8 As shown, the input terminal of LATCH5 is connected to the output terminal 1 of Counter.

[0103] Specifically, due to E_6, F n <11:6> are both 6 bits, so synchronously shifting E_6 by 6 bits will yield F n <11:6>.

[0104] Then, F n <11:6> is the high 6 bits, F n <5:0> is the lower 6 bits, and the F n <11:0> is [V ref,n ,V sig,n ]’s 12-bit quantization result.

[0105] Simulation Verification In order to illustrate the effect of this SAR-SS ADC circuit, a circuit simulation was performed. The results are as follows Figure 9~Figure 11 .

[0106] See also Fig. 9 , showing the differential nonlinearity (DNL) of this SAR-SS ADC circuit; see Fig.10 , showing the differential nonlinearity error (INL) of this SAR-SS ADC circuit.

[0107] It can be seen that DNL and INL basically fluctuate within ±0.5LSB, indicating that the quantization accuracy of the SAR-SS ADC circuit meets the requirements and no further correction is required.

[0108] See also Fig.11 , showing the noise of the SAR-SS ADC circuit. It can be seen that the noise of the SAR-SS ADC circuit is reduced to 122.503μVrms, indicating that the SAR-SS ADC circuit achieves a low noise effect.

[0109] Example 2 This embodiment 2 discloses a SAR-SS type ADC module with pre-judgment logic, which adopts the layout of a SAR-SS type ADC circuit with pre-judgment logic disclosed in embodiment 1. The packaging mode makes it easier to promote and apply the above circuit.

[0110] The SAR-SS type ADC module with pre-judgment logic includes: a signal input module (corresponding to the signal input part), a gain amplification module (corresponding to the gain amplification part), a pre-judgment logic module (corresponding to the pre-judgment logic part), a SAR-ADC module (corresponding to the SAR-ADC part), a SS-ADC module (corresponding to the SS-ADC), and a data processing module (corresponding to the data processing part). For the specific circuit distribution, please refer to Example 1, which will not be repeated here.

[0111] This embodiment 2 also discloses a CMOS image sensor, which adopts the above-mentioned SAR-SS type ADC module with pre-judgment logic.

[0112] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SAR-SS type ADC circuit with pre-judgment logic, characterized in that: It is used to compare the pixel signals of two columns {V ref,n }、{V sig,n }12bit quantization is performed to obtain [V ref,n ,V sig,n ]'s 12-bit quantization result F n <11:0>; n∈{1,2}; It includes: Signal input section, which is used to V ref,1 、V sig,1 、V ref,2 、V sig,2 Enter in order; A gain amplifier, which is used to perform gain amplification on the output of the signal input unit; The pre-judgment logic section is used to sig,2 After input, determine whether coarse quantization is needed; SAR-ADC section, which is used to: ref,1 、V sig,1 、V ref,2 After the input, the corresponding output of the gain amplifier is coarsely quantized to obtain the corresponding 6-bit code value D ref,1 <5:0>, D sig,1 <5:0>, D ref,2 <5:0>; at V sig,2 After input, the corresponding operation is performed according to the judgment result of the pre-judgment logic unit; if it is judged that coarse quantization is not necessary, D is retained. sig,1 <5:0> as V sig,2 The corresponding 6-bit code value D sig,2 <5:0>; otherwise, coarse quantization is performed based on the output corresponding to the gain amplifier to obtain the corresponding 6-bit code value D sig,2 <5:0>; SS-ADC section, which is used in the SAR-ADC section to V ref,n 、V sig,n After the coarse quantization is completed, based on V ref,n 、V sig,n Perform digital correlated multi-sampling to obtain a 9-bit code value E n <8:0>; as well as The data processing unit is used to: ref,n <5:0>, D sig,n <5:0> Perform digital correlated double sampling to obtain a 6-bit coarse quantization result F n <5:0>, based on D sig,n The highest bit D in <5:0> sig,n <0> For E n <8:0> Perform conditional multi-sampling selection to obtain a 6-bit fine quantization result F n <11:6>; among them, F n <5:0>, F n <11:6> constitutes F n <11:0>.

2. A SAR-SS type ADC circuit with pre-judgment logic according to claim 1, characterized in that: The signal input section includes: 2 input switches S P1 ~S P2 ; S P1 The first end of the ref,n }, the second end is connected to the input end of the gain amplifier; S P2 The first end of the sig,n }, the second end is connected to the input end of the gain amplifier; Among them, S P1 , S P2 Not closed simultaneously and sequentially.

3. The SAR-SS type ADC circuit with pre-judgment logic according to claim 1, characterized in that: The gain amplifier includes: 1 high gain amplifier Amp, 1 fixed capacitor C H1 , 1 programmable capacitor C H2 , 1 switch S C ; C H2 The first end is used as the input end of the gain amplifier, and the second end is connected to C H1 The first end, S C The first end of , the input end of Amp; C H1 The second end, S C The second end is connected to the output end of Amp; The output end of Amp serves as the output end of the gain amplifier and is used to output a gain signal Vin.

4. The SAR-SS type ADC circuit with pre-judgment logic according to claim 1, characterized in that: The SAR-ADC unit includes: a SAR logic unit SAR-logic, a signal selection unit MUX, a capacitor array unit, a switch array unit, a comparator COMP0, a latch Latch, and a switching switch S1; The first terminal of S1 is connected to the control voltage V CM , the second end is connected to the output voltage V DAC ; The negative input of COMP0 is connected to V DAC , the positive input terminal is connected to Vin, the output terminal is used to output comparison signals VP and VN, and the control terminal is connected to the timing signal CLK_REAL; The capacitor array includes: 7 capacitors C in parallel G ~C A ; C G ~C A The upper board connects V DAC ; The switch array section includes: 18 switches S A0 ~S F0 , S A1 ~S F1 , S A2 ~S F2 ; Among them, switch S σ0 The first end of the switch S σ1 The first end of the switch S σ2 The first end of the capacitor C σ The lower board of S σ0 The second end is connected to V CM ; S σ1 The second end is connected to the control voltage V H ; S σ2 The second end is connected to the control voltage V L ;σ∈[A,B,C,D,E,F]; The control end of SAR-logic is connected to VP and VN, the output end 1 is used to output the timing signal CLK, and the output end 2 is used to output the control signal Ctrl for the switch array part and MUX; The input end of the latch is connected to the output end 3 of the SAR-logic, and the output end is used to output the 6-bit code value obtained by coarse quantization; MUX includes a two-to-one selector mux2 and a three-to-one selector mux3; the input end of mux2 is connected to V CM , input terminal 2 is connected to the ramp signal V ramp ; Input 1 of mux3 is connected to the output of mux2, and input 2 is connected to V H , input terminal three connected to V L , the output terminal is connected to C G The lower level board; Among them, in the coarse quantization, mux2 selects V CM ; In fine quantization, mux2 selects V ramp .

5. The SAR-SS type ADC circuit with pre-judgment logic according to claim 4, characterized in that: The SS-ADC section includes: 1 comparator COMP1, 1 counter Counter, and 1 ramp generator RAMP_generator; The negative input of COMP1 is connected to V DAC , the positive input terminal is connected to Vin, and the output terminal is used to output the control signal V COM ; The input of Counter is connected to V COM ; Among them, Counter is a 9-bit bidirectional counter, which is used to count Vin up and down to get E n <8:0>; RAMP_generator is used to generate V ramp .

6. The SAR-SS type ADC circuit with pre-judgment logic according to claim 5, characterized in that: RAMP_generator includes: a conversion circuit part, a current source part, a differential switch part, and an operational amplifier array part; The conversion circuit includes: 1 resistor R, 1 resistor R dummy ; The second end of R is connected to R dummy The first end of R is used as the output end of RAMP_generator to output V ramp ; The current source section includes: 17 current sources I0~I 16 ; The differential switch section includes: 34 switches S W,0 ~S W,33 ; Among them, I x By S W,x Connect the first end of R through S W,y Connect R dummy The first end of ; x∈{0,2,4,…,32}, y∈{1,3,5,…,33}; The operational amplifier array includes: 1 operational amplifier A0, 1 capacitor C x , 1 NMOS tube N1; the negative input terminal of A0 is connected to the reference voltage V th , the positive input terminal is connected to C x The first end of R, the second end of R, the drain of N1, and the output end is connected to C x The second end of N1 and the gate of N1; the source of N1 is grounded.

7. The SAR-SS type ADC circuit with pre-judgment logic according to claim 5, characterized in that: The pre-judgment logic unit includes: 2 latches LATCH1~LATCH2, 1 inverter INV, 1 XOR gate XOR, 1 AND gate AND, 1 two-to-one selector mux1; The input terminals of LATCH1 and LATCH2 are connected to V COM ; The output end of LATCH1 is used to output the control signal PRE1, the output end of LATCH2 is connected to the input end of INV, and the output end of INV is used to output the control signal PRE2; Input terminal 1 of AND is connected to PRE1, input terminal 2 is connected to PRE2, and the output terminal is used to output the selection signal PRE; Input 1 of XOR is connected to PRE, and input 2 is connected to CLK; Input 1 of mux1 is connected to the output of XOR, input 2 is connected to CLK, and the output is used to output CLK_REAL.

8. The SAR-SS type ADC circuit with pre-judgment logic according to claim 5, characterized in that: The data processing unit includes: 1 subtractor, 3 latches LATCH3~LATCH5, and 1 adaptive multi-sampling unit; LATCH3 is used to latch D sig,n <5:0>; LATCH4 is used to latch D ref,n <5:0>; Subtractor is used to perform subtraction operations on the output of LATCH3 and LATCH4, and according to E n The highest bit E of <8:0> n <8> The subtraction result is sign corrected to obtain F n <5:0>; The adaptive multi-sampling unit is used to sig,n <0> Generate a selection signal choose to implement Counter and then perform conditional multi-sampling based on choose; Among them, if D sig,n <0> is 1, Counter performs one sampling count and outputs the sampling count result as E_6; if D sig,n <0> If it is 0, Counter performs 4 sampling counts and takes the average of the sampling count results as E_6 for output; LATCH5 is used to latch E_6 and convert it into F n <11:6>.

9. The SAR-SS type ADC circuit with pre-judgment logic according to claim 8, characterized in that: The input end of LATCH3 is connected to the output end of Latch, and the output end is used to output D sig,n <5:0>, output terminal 2 is used to output D sig,n <0> ; The input end of LATCH4 is connected to the output end of Latch; The input end of the adaptive multi-sampling unit is connected to the output end 1 of LATCH3, and the output end is connected to the control end of Counter; Counter output terminal 1 is used to output E_6, and output terminal 2 is used to output E n The highest bit E of <8:0> n <8> ; Input 1 of Subtractor is connected to the output of LATCH3, input 2 is connected to the output of LATCH4, and input 3 is connected to the output 2 of Counter; The input terminal of LATCH5 is connected to the output terminal 1 of Counter.

10. A SAR-SS type ADC module with pre-judgment logic, characterized in that: A layout of a SAR-SS type ADC circuit with pre-judgment logic as described in any one of claims 1 to 9 is adopted.

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